From d5cc78f339dacf5813a66755a973e85c885002a1 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Thu, 28 Nov 2013 21:48:24 +0100 Subject: [PATCH] Trigger from peripheral FPGAs --- cts/source/cts.vhd | 8 +++++++ cts/source/cts_pkg.vhd | 11 +++++++-- cts/source/cts_trigger.vhd | 49 ++++++++++++++++++++++++++++++++++++-- cts/trb3_central.vhd | 10 ++++++-- 4 files changed, 72 insertions(+), 6 deletions(-) mode change 100644 => 100755 cts/source/cts.vhd mode change 100644 => 100755 cts/source/cts_pkg.vhd mode change 100644 => 100755 cts/trb3_central.vhd diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd old mode 100644 new mode 100755 index 6cd5823..76e6370 --- a/cts/source/cts.vhd +++ b/cts/source/cts.vhd @@ -109,6 +109,8 @@ entity CTS is ADDON_GROUPS : integer range 1 to 8 := 5; ADDON_GROUP_UPPER : CTS_GROUP_CONFIG_T := (3,7,11,12,13, others=>'0'); + PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1; + EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00"; TIME_REFERENCE_COUNT : positive := 10; @@ -127,6 +129,8 @@ entity CTS is ADDON_TRIGGERS_IN : in std_logic_vector(ADDON_LINE_COUNT-1 downto 0) := (others => '0'); ADDON_GROUP_ACTIVITY_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); ADDON_GROUP_SELECTED_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); + + PERIPH_TRIGGER_IN : in std_logic_vector(3 downto 0) := (others => '0'); -- External trigger logic EXT_TRIGGER_IN : in std_logic; @@ -723,6 +727,8 @@ begin ADDON_GROUPS => ADDON_GROUPS, ADDON_GROUP_UPPER => ADDON_GROUP_UPPER, + PERIPH_TRIGGER_COUNT => PERIPH_TRIGGER_COUNT, + TRIGGER_ADDON_COUNT => TRIGGER_ADDON_COUNT, EXTERNAL_TRIGGER_ID => EXTERNAL_TRIGGER_ID ) @@ -736,6 +742,8 @@ begin ADDON_GROUP_ACTIVITY_OUT => ADDON_GROUP_ACTIVITY_OUT, ADDON_GROUP_SELECTED_OUT => ADDON_GROUP_SELECTED_OUT, + PERIPH_TRIGGER_IN => PERIPH_TRIGGER_IN, + EXT_TRIGGER_IN => EXT_TRIGGER_IN, EXT_STATUS_IN => EXT_STATUS_IN, EXT_CONTROL_OUT => EXT_CONTROL_OUT, diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd old mode 100644 new mode 100755 index 0aa1826..64b9e8d --- a/cts/source/cts_pkg.vhd +++ b/cts/source/cts_pkg.vhd @@ -9,7 +9,7 @@ package cts_pkg is generic ( -- The total number of trigger units below has to be below 16 TRIGGER_INPUT_COUNT : integer range 1 to 8 := 4; - TRIGGER_COIN_COUNT : integer range 0 to 15 := 4; + TRIGGER_COIN_COUNT : integer range 0 to 15 := 3; TRIGGER_PULSER_COUNT: integer range 0 to 15 := 4; TRIGGER_RAND_PULSER : integer range 0 to 15 := 1; @@ -18,6 +18,8 @@ package cts_pkg is ADDON_GROUPS : integer range 1 to 8 := 5; ADDON_GROUP_UPPER : CTS_GROUP_CONFIG_T := (3,7,11,12,13, others=>'0'); + PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1; + EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00"; TIME_REFERENCE_COUNT: positive := 10; -- Number of clock cycles the time reference needs to stay asserted (100ns) @@ -37,6 +39,8 @@ package cts_pkg is ADDON_GROUP_ACTIVITY_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); ADDON_GROUP_SELECTED_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); + PERIPH_TRIGGER_IN : in std_logic_vector(3 downto 0) := (others => '0'); + -- External trigger logic EXT_TRIGGER_IN : in std_logic; EXT_STATUS_IN : in std_logic_vector(31 downto 0) := X"00000000"; @@ -173,6 +177,7 @@ package cts_pkg is ADDON_GROUPS : integer range 1 to 8 := 5; ADDON_GROUP_UPPER : CTS_GROUP_CONFIG_T := (3,7,11,12,13, others=>'0'); + PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1; EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00" ); @@ -187,7 +192,9 @@ package cts_pkg is ADDON_TRIGGERS_IN : in std_logic_vector(ADDON_LINE_COUNT-1 downto 0) := (others => '0'); ADDON_GROUP_ACTIVITY_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); ADDON_GROUP_SELECTED_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); - + + PERIPH_TRIGGER_IN : in std_logic_vector(3 downto 0) := (others => '0'); + -- External EXT_TRIGGER_IN : in std_logic; EXT_STATUS_IN : in std_logic_vector(31 downto 0) := X"00000000"; diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd index dbd39f9..99cf30b 100755 --- a/cts/source/cts_trigger.vhd +++ b/cts/source/cts_trigger.vhd @@ -17,6 +17,8 @@ entity CTS_TRIGGER is ADDON_LINE_COUNT : integer range 0 to 255 := 22; ADDON_GROUPS : integer range 1 to 8 := 5; ADDON_GROUP_UPPER : CTS_GROUP_CONFIG_T := (3,7,11,12,13, others=>'0'); + + PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1; EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00" ); @@ -32,6 +34,8 @@ entity CTS_TRIGGER is ADDON_TRIGGERS_IN : in std_logic_vector(ADDON_LINE_COUNT-1 downto 0) := (others => '0'); ADDON_GROUP_ACTIVITY_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); ADDON_GROUP_SELECTED_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); + + PERIPH_TRIGGER_IN : in std_logic_vector(3 downto 0) := (others => '0'); -- External EXT_TRIGGER_IN : in std_logic; @@ -81,7 +85,8 @@ architecture RTL of CTS_TRIGGER is constant ITC_BASE_PULSER : integer := ITC_BASE_EXT + ITC_NUM_EXT; constant ITC_BASE_RAND_PULSER : integer := ITC_BASE_PULSER + TRIGGER_PULSER_COUNT; constant ITC_BASE_INPUTS : integer := ITC_BASE_RAND_PULSER + TRIGGER_RAND_PULSER; - constant ITC_BASE_COINS : integer := ITC_BASE_INPUTS + ITL_NUM; + constant ITC_BASE_PERIPH : integer := ITC_BASE_INPUTS + ITL_NUM; + constant ITC_BASE_COINS : integer := ITC_BASE_PERIPH + PERIPH_TRIGGER_COUNT; constant ITC_NUM_USED : integer := ITC_BASE_COINS + TRIGGER_COIN_COUNT; @@ -96,7 +101,7 @@ architecture RTL of CTS_TRIGGER is alias rand_pulsers_i : std_logic_vector(TRIGGER_RAND_PULSER - 1 downto 0) is channels_i(ITC_BASE_RAND_PULSER + TRIGGER_RAND_PULSER - 1 downto ITC_BASE_RAND_PULSER); - + type channel_counters_t is array(channels_i'HIGH downto 0) of unsigned(31 downto 0); signal channel_counters_i : channel_counters_t; signal channel_edge_counters_i : channel_counters_t; @@ -125,6 +130,10 @@ architecture RTL of CTS_TRIGGER is type rand_pulser_threshold_t is array(TRIGGER_RAND_PULSER - 1 downto 0) of std_logic_vector(31 downto 0); signal rand_pulser_threshold_i : rand_pulser_threshold_t := (others => (others => '0')); + +-- Peripheral Trigger Inputs + signal periph_trigger_mask_i : std_logic_vector(3 downto 0) := (others => '0'); + -- Add On type trigger_addon_configs_t is array(TRIGGER_ADDON_COUNT - 1 downto 0) of std_logic_vector(7 downto 0); signal trigger_addon_configs_i : trigger_addon_configs_t; @@ -202,6 +211,13 @@ begin ); end generate; + proc_periph: process(CLK_IN) is + begin + if rising_edge(clk_in) and PERIPH_TRIGGER_COUNT > 0 then + channels_i(ITC_BASE_PERIPH) <= OR_ALL( periph_trigger_mask_i and PERIPH_TRIGGER_IN ); + end if; + end process; + proc_pulser: process(CLK_IN) is begin if rising_edge(CLK_IN) then @@ -532,6 +548,35 @@ begin end loop; end if; +-- PERIPH TRIGGER + if PERIPH_TRIGGER_COUNT > 0 then + if addr = ref_addr then + REGIO_UNKNOWN_ADDR_OUT <= REGIO_WRITE_ENABLE_IN; + REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN; + REGIO_DATA_OUT <= CTS_BLOCK_HEADER( + id => 16#13#, + len => 1, + itc_base => ITC_BASE_PERIPH, + itc_num => 1 + ); + end if; + ref_addr := ref_addr + 1; + + if addr=ref_addr then + REGIO_UNKNOWN_ADDR_OUT <= '0'; + REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN; + REGIO_WRITE_ACK_OUT <= REGIO_WRITE_ENABLE_IN; + + REGIO_DATA_OUT <= (others => '0'); + REGIO_DATA_OUT(periph_trigger_mask_i'range) <= periph_trigger_mask_i; + + if REGIO_WRITE_ENABLE_IN = '1' then + periph_trigger_mask_i <= REGIO_DATA_IN(periph_trigger_mask_i'range); + end if; + end if; + ref_addr := ref_addr + 1; + end if; + -- TRIGGER_PULSER_COUNT CONFIGURATION if TRIGGER_PULSER_COUNT > 0 then if addr = ref_addr then diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd old mode 100644 new mode 100755 index f53c1ae..99eeb5e --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -334,6 +334,8 @@ architecture trb3_central_arch of trb3_central is signal cts_addon_triggers_in : std_logic_vector(CTS_ADDON_LINE_COUNT-1 downto 0); signal cts_addon_activity_i, cts_addon_selected_i : std_logic_vector(4 downto 0); + + signal cts_periph_trigger_i : std_logic_vector(3 downto 0); signal cts_trg_send : std_logic; signal cts_trg_type : std_logic_vector(3 downto 0); @@ -484,13 +486,15 @@ begin THE_CTS: CTS generic map ( - EXTERNAL_TRIGGER_ID => X"60"+ETM_CHOICE_type'pos(ETM_CHOICE), --, fill in trigger logic enumeration id of external trigger logic + EXTERNAL_TRIGGER_ID => X"60"+ETM_CHOICE_type'pos(ETM_CHOICE), -- fill in trigger logic enumeration id of external trigger logic TRIGGER_INPUT_COUNT => 4, TRIGGER_COIN_COUNT => 4, TRIGGER_PULSER_COUNT => 2, TRIGGER_RAND_PULSER => 1, TRIGGER_ADDON_COUNT => 2, + PERIPH_TRIGGER_COUNT => 1, + ADDON_LINE_COUNT => CTS_ADDON_LINE_COUNT, ADDON_GROUPS => 5, ADDON_GROUP_UPPER => (3,7,11,12,13, others=>0) @@ -512,6 +516,8 @@ begin EXT_CONTROL_OUT => cts_ext_control, EXT_HEADER_BITS_IN => cts_ext_header, + PERIPH_TRIGGER_IN => cts_periph_trigger_i, + CTS_TRG_SEND_OUT => cts_trg_send, CTS_TRG_TYPE_OUT => cts_trg_type, CTS_TRG_NUMBER_OUT => cts_trg_number, @@ -572,7 +578,7 @@ begin others => '0' ); - + cts_periph_trigger_i <= FPGA4_COMM(10) & FPGA3_COMM(10) & FPGA2_COMM(10) & FPGA1_COMM(10); -- cts_rdo_trg_status_bits <= cts_rdo_trg_status_bits_cts OR cts_rdo_trg_status_bits_additional; -- 2.43.0