From d60c619fe30bebe4b94b95fc00ef265e774ed1f7 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 26 Jul 2017 18:26:22 +0200 Subject: [PATCH] Update ADC AddOn design --- adcaddon/trb3sc_adc.prj | 2 +- adcaddon/trb3sc_adc.vhd | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj index 6138d95..c89cf14 100644 --- a/adcaddon/trb3sc_adc.prj +++ b/adcaddon/trb3sc_adc.prj @@ -191,4 +191,4 @@ add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_handler.vhd" add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_slowcontrol_data_buffer.vhd" add_file -vhdl -lib "work" "trb3sc_adc.vhd" -add_file -constraint "trb3sc_adc.sdc" +#add_file -constraint "trb3sc_adc.sdc" diff --git a/adcaddon/trb3sc_adc.vhd b/adcaddon/trb3sc_adc.vhd index a17289f..a5e3c1c 100644 --- a/adcaddon/trb3sc_adc.vhd +++ b/adcaddon/trb3sc_adc.vhd @@ -338,6 +338,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record --------------------------------------------------------------------------- gen_reallogic : if USE_DUMMY_READOUT = 0 generate THE_ADC : entity work.adc_handler + generic map( + IS_TRB3 = 0 + ) port map( CLK => clk_sys, CLK_ADCRAW => CLK_CORE_PCLK, --clk_full_osc, -- 2.43.0