From d6d252b49fe8267c7952bcec71627238aae4f29c Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 28 Jul 2022 08:40:30 +0200 Subject: [PATCH] cleanups, bugfixes --- gbe_trb/base/tx_fifo.vhd | 1 + gbe_trb_ecp5/media/gbe_med_fifo.vhd | 129 +++++++++++++++++++--------- 2 files changed, 88 insertions(+), 42 deletions(-) diff --git a/gbe_trb/base/tx_fifo.vhd b/gbe_trb/base/tx_fifo.vhd index 5d7bf39..e2cf503 100644 --- a/gbe_trb/base/tx_fifo.vhd +++ b/gbe_trb/base/tx_fifo.vhd @@ -9,6 +9,7 @@ library work; -- BUG: use dynamic ALMOSTFULL to accommodate for pipelining inside the data -- multiplexer of hub. +-- FIX: ALMOSTFULL is set at 4092, so we have at least three clocks -- OPTIMIZE: we can start transfering data to the MAC once 16bytes (or similar) -- have been written. diff --git a/gbe_trb_ecp5/media/gbe_med_fifo.vhd b/gbe_trb_ecp5/media/gbe_med_fifo.vhd index 8b4bd1f..3e1eac8 100644 --- a/gbe_trb_ecp5/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp5/media/gbe_med_fifo.vhd @@ -62,7 +62,7 @@ entity gbe_med_fifo is ); end entity gbe_med_fifo; -architecture RTL of gbe_med_fifo is +architecture gbe_med_fifo_arch of gbe_med_fifo is component sgmii_gbe_core -- checked for ECP5-5G core port( @@ -251,7 +251,15 @@ architecture RTL of gbe_med_fifo is signal SD_TXD_N : std_logic; signal fifo_full_i : std_logic; + + signal rx_bsm : std_logic_vector(3 downto 0); +-- -- just a check to see if something goes wrong.... +-- attribute HGROUP : string; +-- attribute HGROUP of gbe_med_fifo_arch : architecture is "media_interface_group"; +-- attribute syn_hier : string; +-- attribute syn_hier of gbe_med_fifo_arch : architecture is "fixed"; + begin -- Some notes on clocks: the SerDes uses TX and RX bridge FIFO, with RX FIFO being clocked on @@ -297,13 +305,13 @@ begin tx_pwrup_c => '1', serdes_pdb => '1', -- DUAL is powered up -- Resets - sli_rst => CLEAR, --'0', -- soft logic reset (?) + sli_rst => CLEAR, -- soft logic reset (?) rst_dual_c => CLEAR, rx_pcs_rst_c => rx_pcs_rst_q, rx_serdes_rst_c => rx_serdes_rst_q, tx_pcs_rst_c => tx_pcs_rst, - serdes_rst_dual_c => '0', - tx_serdes_rst_c => '0' + serdes_rst_dual_c => CLEAR, --'0', + tx_serdes_rst_c => CLEAR --'0' ); end generate GEN_SERDES_0; @@ -343,13 +351,13 @@ begin tx_pwrup_c => '1', serdes_pdb => '1', -- DUAL is powered up -- Resets - sli_rst => CLEAR, --'0', -- soft logic reset (?) + sli_rst => CLEAR, -- soft logic reset (?) rst_dual_c => CLEAR, rx_pcs_rst_c => rx_pcs_rst_q, rx_serdes_rst_c => rx_serdes_rst_q, tx_pcs_rst_c => tx_pcs_rst, - serdes_rst_dual_c => '0', - tx_serdes_rst_c => '0' + serdes_rst_dual_c => CLEAR, --'0', + tx_serdes_rst_c => CLEAR --'0' ); end generate GEN_SERDES_1; @@ -379,7 +387,7 @@ begin rx_disp_err => sd_rx_disp_error, rx_cv_err => sd_rx_cv_error, lsm_status_s => lsm_status, - signal_detect_c => '1', -- enable internal LSM + signal_detect_c => '1', -- enable internal LSM6500933585 -- Status signals pll_lol => pll_lol, rx_cdr_lol_s => rx_cdr_lol, @@ -389,13 +397,13 @@ begin tx_pwrup_c => '1', serdes_pdb => '1', -- DUAL is powered up -- Resets - sli_rst => CLEAR, --'0', -- soft logic reset (?) + sli_rst => CLEAR, -- soft logic reset (?) rst_dual_c => CLEAR, rx_pcs_rst_c => rx_pcs_rst_q, rx_serdes_rst_c => rx_serdes_rst_q, tx_pcs_rst_c => tx_pcs_rst, - serdes_rst_dual_c => '0', - tx_serdes_rst_c => '0' + serdes_rst_dual_c => CLEAR, --'0', + tx_serdes_rst_c => CLEAR --'0' ); end generate GEN_SERDES_2; @@ -435,13 +443,13 @@ begin tx_pwrup_c => '1', serdes_pdb => '1', -- DUAL is powered up -- Resets - sli_rst => CLEAR, --'0', -- soft logic reset (?) + sli_rst => CLEAR, -- soft logic reset (?) rst_dual_c => CLEAR, rx_pcs_rst_c => rx_pcs_rst_q, rx_serdes_rst_c => rx_serdes_rst_q, tx_pcs_rst_c => tx_pcs_rst, - serdes_rst_dual_c => '0', - tx_serdes_rst_c => '0' + serdes_rst_dual_c => CLEAR, --'0', + tx_serdes_rst_c => CLEAR --'0' ); end generate GEN_SERDES_3; @@ -476,9 +484,46 @@ begin RX_SERDES_RST_OUT => rx_serdes_rst, -- CLK_REF based RX_PCS_RST_OUT => rx_pcs_rst, -- CLK_REF based LINK_RX_READY_OUT => link_rx_ready, -- CLK_REF based - STATE_OUT => open + STATE_OUT => rx_bsm --open ); - + + -- "Good" debugging pins + debug(0) <= pll_lol; + debug(1) <= rx_cdr_lol; + debug(2) <= rx_los_low; + debug(3) <= sd_rx_cv_error(0); + debug(4) <= lsm_status; + debug(5) <= tx_pcs_rst; + debug(6) <= rx_serdes_rst; + debug(7) <= rx_pcs_rst; + debug(8) <= link_rx_ready; + debug(9) <= link_tx_ready; + debug(10) <= rx_bsm(0); --'0'; + debug(11) <= rx_bsm(1); --'0'; + debug(12) <= rx_bsm(2); --'0'; + debug(13) <= rx_bsm(3); --'0'; + debug(14) <= '0'; + debug(15) <= '0'; + debug(16) <= '0'; + debug(17) <= '0'; + debug(18) <= '0'; + debug(19) <= '0'; + -- "Bad" debugging pins + debug(20) <= RESET; + debug(21) <= CLEAR; + debug(22) <= '0'; + debug(23) <= '0'; + debug(24) <= '0'; + debug(25) <= '0'; + debug(26) <= '0'; + debug(27) <= '0'; + debug(28) <= '0'; + debug(29) <= '0'; + debug(30) <= '0'; + debug(31) <= '0'; + debug(32) <= '0'; + debug(33) <= CLK_125; + -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5 SYNC_RST_SIGS: entity work.signal_sync generic map( WIDTH => 2 ) @@ -565,29 +610,6 @@ begin pulse <= not delay_q(7) and delay_q(6); --- /SIMPLE --- - -- "Good" debugging pins - debug(7 downto 0) <= pcs_txd; - debug(15 downto 8) <= pcs_rxd; - debug(16) <= pcs_tx_en; - debug(17) <= pcs_rx_en; - debug(18) <= pcs_tx_er; - debug(19) <= pcs_rx_er; - -- "Bad" debugging pins - debug(20) <= mr_restart_an; - debug(21) <= mr_page_rx; - debug(22) <= an_complete; - debug(23) <= link_rx_ready; - debug(24) <= link_tx_ready; - debug(25) <= xmit(0); - debug(26) <= sd_tx_correct_disp(0); - debug(27) <= mac_ready_conf; - debug(28) <= mac_reconf; - debug(29) <= link_active; - debug(30) <= fifo_full_i; - debug(31) <= mac_rx_fifofull; - debug(32) <= '0'; - debug(33) <= CLK_125; - MAC: tsmac_gbe port map( ----------------- clock and reset port declarations ------------------ @@ -768,7 +790,7 @@ begin -- 32 = CLK1 (white/blue) -------------------------------------------------------------------- -------------------------------------------------------------------- - + -- -- "Good" debugging pins -- debug(7 downto 0) <= sd_tx_data; -- debug(15 downto 8) <= sd_rx_data; @@ -791,5 +813,28 @@ begin -- debug(31) <= link_active; -- debug(32) <= '0'; -- debug(33) <= CLK_125; - -end architecture RTL; + +-- -- "Good" debugging pins +-- debug(7 downto 0) <= pcs_txd; +-- debug(15 downto 8) <= pcs_rxd; +-- debug(16) <= pcs_tx_en; +-- debug(17) <= pcs_rx_en; +-- debug(18) <= pcs_tx_er; +-- debug(19) <= pcs_rx_er; +-- -- "Bad" debugging pins +-- debug(20) <= mr_restart_an; +-- debug(21) <= mr_page_rx; +-- debug(22) <= an_complete; +-- debug(23) <= link_rx_ready; +-- debug(24) <= link_tx_ready; +-- debug(25) <= xmit(0); +-- debug(26) <= sd_tx_correct_disp(0); +-- debug(27) <= mac_ready_conf; +-- debug(28) <= mac_reconf; +-- debug(29) <= link_active; +-- debug(30) <= fifo_full_i; +-- debug(31) <= mac_rx_fifofull; +-- debug(32) <= '0'; +-- debug(33) <= CLK_125; + +end architecture gbe_med_fifo_arch; -- 2.43.0