From d73f7068a2d3151b1632c44aad1003dc6671d16f Mon Sep 17 00:00:00 2001 From: Ingo Froehlich Date: Tue, 22 Aug 2017 16:16:12 +0200 Subject: [PATCH] new dirich flash scheme, IF --- thresholds/thresholds.vhd | 486 ++++++-------------------------------- 1 file changed, 68 insertions(+), 418 deletions(-) diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd index 1f4d8e0..86a45ec 100644 --- a/thresholds/thresholds.vhd +++ b/thresholds/thresholds.vhd @@ -23,7 +23,8 @@ end entity; architecture arch of thresholds is type ram_t is array (15 downto 0) of std_logic_vector(15 downto 0); - + signal ram_data : ram_t := (others =>("0000000000100001")); + signal clk_osc, clk_i : std_logic; signal spi_rx_data : std_logic_vector(15 downto 0); @@ -34,52 +35,25 @@ architecture arch of thresholds is signal bus_ready : std_logic; --signal spi_busy : std_logic; + signal spi_data_out : std_logic_vector(15 downto 0); + signal spi_data_in : std_logic_vector(15 downto 0); + signal spi_addr_out : std_logic_vector(7 downto 0); + signal spi_write_out : std_logic; + signal spi_read_out : std_logic; + signal spi_ready_in : std_logic; + + signal sed_error : std_logic; signal sed_debug : std_logic_vector(31 downto 0); signal controlsed_i : std_logic_vector(3 downto 0); - signal pwm_data_i : std_logic_vector(15 downto 0):= x"6000"; - signal pwm_write_i : std_logic; - signal pwm_addr_i : std_logic_vector(4 downto 0); - signal pwm_data_ii : std_logic_vector(15 downto 0); - signal pwm_write_ii : std_logic; - signal pwm_addr_ii : std_logic_vector(4 downto 0); - signal pwm_data_iii : std_logic_vector(15 downto 0); - signal pwm_write_iii : std_logic; - signal pwm_addr_iii : std_logic_vector(4 downto 0); - --- signal flashram_reset : std_logic; - --signal flashram_write_i: std_logic; - signal flashram_data_i : std_logic_vector(7 downto 0); - signal flashram_data_o : std_logic_vector(7 downto 0) := "00000010"; - signal ram_data : ram_t := (others =>("0000000000100001"));--: std_logic_vector(15 downto 0); - --signal ram_data_o : ram_t := (others =>("0000000000000000"));--std_logic_vector(15 downto 0); - - signal flash_command : std_logic := '0'; - --signal flash_page : std_logic_vector(12 downto 0); - signal flash_go : std_logic := '1'; - signal flash_busy : std_logic; - signal flash_err : std_logic; + signal pwm_data : std_logic_vector(15 downto 0):= x"6000"; + signal pwm_write : std_logic; + signal pwm_addr : std_logic_vector(4 downto 0); signal compensate_i : signed(15 downto 0) := (others =>'0'); signal pwm_i : std_logic_vector(16 downto 1); - signal ufm_bus_ready_in : std_logic; - signal ufm_bus_ready_out : std_logic; - signal ufm_databyte_counter : unsigned(14 downto 0); - - signal ram_spi_addr : std_logic_vector( 7 downto 0); - signal ram_spi_data : std_logic_vector(15 downto 0):= "0000111100001111"; - signal ram_spi_write : std_logic; - signal show_flash_err : std_logic := '0'; - signal ram_spi_read :std_logic := '0'; - signal flash_temp : std_logic_vector(7 downto 0); - - --type state_type is (Start,IDLE,c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15); --type of state machine. - --signal state: state_type := Start; - --signal init : std_logic:='1'; - --- signal temp : std_logic_vector(3 downto 0):= "0000"; component OSCH generic (NOM_FREQ: string := "33.25"); @@ -112,180 +86,85 @@ clk_i <= clk_osc; THE_SPI : entity work.spi_slave port map( CLK => clk_i, + SPI_CLK => SCLK_IN, SPI_CS => CS_IN , SPI_IN => MOSI_IN, SPI_OUT => MISO_OUT, - - DATA_OUT => spi_rx_data, - DATA_IN => spi_tx_data, - ADDR_OUT => spi_addr, - WRITE_OUT => bus_write, - READ_OUT => bus_read, - READY_IN => bus_ready, + + DATA_OUT => spi_data_out, + DATA_IN => spi_data_in, + ADDR_OUT => spi_addr_out, + WRITE_OUT => spi_write_out, + READ_OUT => spi_read_out, + READY_IN => spi_ready_in, + +-- DATA_OUT => spi_rx_data, +-- DATA_IN => spi_tx_data, +-- ADDR_OUT => spi_addr, +-- WRITE_OUT => bus_write, +-- READ_OUT => bus_read, +-- READY_IN => bus_ready, DEBUG => open ); - --- count : process (clk_i) --- begin --- if rising_edge(clk_i) then --- if temp="1001" then --- temp<="0000"; --- else --- temp <= std_logic_vector(unsigned(temp) + 1); --- end if; --- end if; --- --- end process; - --- state_machine : process (clk_i) --- begin --- if rising_edge(clk_i) then --- pwm_write_i <= '0'; --- --pwm_data_i <= x"6000"; --- case state is --- when Start => --when current state is "s0" --- if init = '1' then --- pwm_write_i <= '0'; --- state <= c0; --- end if; --- --- when c0 => pwm_write_i <= '1'; --- pwm_addr_i <= "00000"; --- state <= c1; --- --- when c1 => pwm_write_i <= '1'; --- pwm_addr_i <= "00001"; --- state <= c2; --- --- when c2 => pwm_write_i <= '1'; --- pwm_addr_i <= "00010"; --- state <= c3; --- --- when c3 => pwm_write_i <= '1'; --- pwm_addr_i <= "00011"; --- state <= c4; --- --- when c4 => pwm_write_i <= '1'; --- pwm_addr_i <= "00100"; --- state <= c5; --- --- when c5 => pwm_write_i <= '1'; --- pwm_addr_i <= "00101"; --- state <= c6; --- --- when c6 => pwm_write_i <= '1'; --- pwm_addr_i <= "00110"; --- state <= c7; --- --- when c7 => pwm_write_i <= '1'; --- pwm_addr_i <= "00111"; --- state <= c8; --- --- when c8 => pwm_write_i <= '1'; --- pwm_addr_i <= "01000"; --- state <= c9; --- --- when c9 => pwm_write_i <= '1'; --- pwm_addr_i <= "01001"; --- state <= c10; --- --- when c10 => pwm_write_i <= '1'; --- pwm_addr_i <= "01010"; --- state <= c11; --- --- when c11 => pwm_write_i <= '1'; --- pwm_addr_i <= "01011"; --- state <= c12; --- --- when c12 => pwm_write_i <= '1'; --- pwm_addr_i <= "01100"; --- state <= c13; --- --- when c13 => pwm_write_i <= '1'; --- pwm_addr_i <= "01101"; --- state <= c14; --- --- when c14 => pwm_write_i <= '1'; --- pwm_addr_i <= "01110"; --- state <= c15; --- --- when c15 => pwm_write_i <= '1'; --- pwm_addr_i <= "01111"; --- init <= '0'; --- state <= IDLE; --- init <= '0'; --- --- when IDLE => pwm_write_i <= pwm_write_ii; --- pwm_addr_i <= pwm_addr_ii; --- pwm_data_i <= pwm_data_ii; --- --- end case; --- --- end if; --- end process; - - -PWM_select : process begin - wait until rising_edge(clk_i); - - pwm_write_i <= '0'; - if pwm_write_ii = '1' then - pwm_data_i <= pwm_data_ii; - pwm_addr_i <= pwm_addr_ii; - pwm_write_i <= pwm_write_ii; - else - pwm_data_i <= pwm_data_iii; - pwm_addr_i <= pwm_addr_iii; - pwm_write_i <= pwm_write_iii; - end if; - -end process; +THE_FLASH_CONTROLLER : entity generic_flash_ctrl + port map( + CLK => clk_i, + RESET => '0', + + SPI_DATA_IN => spi_data_out, + SPI_DATA_OUT => spi_data_in, + SPI_ADDR_IN => spi_addr_out, + SPI_WRITE_IN => spi_write_out, + SPI_READ_IN => spi_read_out, + SPI_READY_OUT => spi_ready_in, + LOC_DATA_OUT => spi_rx_data, + LOC_DATA_IN => spi_tx_data, + LOC_ADDR_OUT => spi_addr, + LOC_WRITE_OUT => bus_write, + LOC_READ_OUT => bus_read, + LOC_READY_IN => bus_ready + + ); + PROC_REGS : process begin wait until rising_edge(clk_i); bus_ready <= '0'; - pwm_write_iii <= '0'; - flash_go <= '0'; - ram_spi_write <= '0'; - ram_spi_read <= '0'; + pwm_write <= '0'; if bus_read = '1' then bus_ready <= '1'; - if (spi_addr >= x"10") and (spi_addr < X"20") then - spi_tx_data <= ram_data(to_integer(unsigned(spi_addr(4 downto 0)))); -- Read RAM + spi_tx_data <= ram_data(to_integer(unsigned(spi_addr(3 downto 0)))); -- Read RAM + --spi_tx_data <= "00000000" & spi_addr; else case spi_addr is - --when x"10" => spi_tx_data <= reg_spi_o(15 downto 0); - --when x"11" => spi_tx_data <= reg_spi_o(31 downto 16); when x"ee" => spi_tx_data <= sed_debug(15 downto 0); when x"ef" => spi_tx_data <= sed_debug(31 downto 16); - -- when others => null; end case; end if; + elsif bus_write = '1' then if (spi_addr >= x"00") and (spi_addr < x"10") then -- write directly to PWM - pwm_data_iii <= spi_rx_data; - pwm_addr_iii <= spi_addr(4 downto 0); - pwm_write_iii <= '1'; - elsif ( spi_addr >= x"10") and (spi_addr < x"20") then -- write to RAM - ram_spi_data(15 downto 0) <= spi_rx_data; - ram_spi_write <= '1'; - ram_spi_addr <= "0000" & spi_addr(3 downto 0); - pwm_data_iii <= spi_rx_data; - pwm_addr_iii <= spi_addr(4 downto 0); - pwm_write_iii <= '1'; + pwm_data <= spi_rx_data; + pwm_addr <= spi_addr(4 downto 0); + pwm_write <= '1'; + elsif (spi_addr >= x"10") and (spi_addr < x"20") then -- write to RAM + ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data; + pwm_data <= spi_rx_data; + pwm_addr <= spi_addr(4 downto 0); + pwm_write <= '1'; else case spi_addr is - when x"20" => flash_command <= '1'; --write to flash; - flash_go <= '1'; - when x"21" => flash_command <= '0'; --read from flash; - flash_go <= '1'; +-- when x"20" => flash_command <= '1'; --write to flash; +-- flash_go <= '1'; +-- when x"21" => flash_command <= '0'; --read from flash; +-- flash_go <= '1'; when x"22" => compensate_i <= signed(spi_rx_data(15 downto 0));--signed(uart_rx_data(15 downto 0); when x"ee" => controlsed_i <= spi_rx_data(3 downto 0); when others => null; @@ -294,38 +173,6 @@ PROC_REGS : process begin end if; end process; --- ManSel : process begin --- wait until rising_edge(clk_i); --- flash_go <= '0'; --- ram_spi_write <= '0'; --- --ram_spi_read <= '0'; --- if pwm_write_ii = '1' then --- pwm_data_i <= pwm_data_ii; --- pwm_addr_i <= pwm_addr_ii; --- pwm_write_i <= pwm_write_ii; --- elsif DIPSW(0) = '0' then --- case DIPSW(3 downto 1) is --- when "000" => ram_spi_data(15 downto 0) <= "1100011100111000"; --- ram_spi_write <= '1'; --- ram_spi_addr <= "00000" & DIPSW(3 downto 1); --- --when "010" => ram_spi_read <= '1'; --- when "011" => flash_command <= '0'; --read from flash; --- flash_go <= '1'; --- when "100" => flash_command <= '1'; --write to flash; --- flash_go <= '1'; --- when "101" => ram_spi_data(15 downto 0) <= "0000011000101010"; --- ram_spi_write <= '1'; --- ram_spi_addr <= "00000" & DIPSW(3 downto 1); --- when others => null; --- end case; --- else --- LED <= not ram_data(to_integer(unsigned(DIPSW(3 downto 1))))(7 downto 0); --- end if; --- --- --- end process; - - THE_SED : entity work.sedcheck generic map( DEV_DENSITY =>"4300L" @@ -347,11 +194,11 @@ THE_PWM_GEN : entity work.pwm_generator ) port map( CLK => clk_i, - DATA_IN => pwm_data_i, -- 16 Bits + DATA_IN => pwm_data, -- 16 Bits DATA_OUT => open, COMP_IN => compensate_i, -- 16 Bits - WRITE_IN => pwm_write_i, -- 16 Bits - ADDR_IN => pwm_addr_i, -- 5 Bits + WRITE_IN => pwm_write, -- 16 Bits + ADDR_IN => pwm_addr, -- 5 Bits PWM => pwm_i -- 16 Bits ); @@ -380,204 +227,7 @@ process(pwm_i,DAC_FLAG) end if; end process; - - ---------------------------------------------------------------------------- --- Flash Controller ---------------------------------------------------------------------------- - -THE_UFM : entity work.UFM_control - generic map( - NO_DATAPAGES => 2, - UFM_STARTPAGE => "00"&x"00" - ) - port map( - CLK => clk_i, - CMD => flash_command, - GO => flash_go, - BUSY => flash_busy, - RESET => '0', - DATA_IN => flashram_data_i, - DATA_OUT => flashram_data_o, - DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte - BUS_READY_IN => ufm_bus_ready_in, - BUS_READY_OUT => ufm_bus_ready_out, - FLASH_ERROR => flash_err - ); - - --- PROC_REGS_FLASH: process begin --- wait until rising_edge( clk_i ); --- ufm_bus_ready_in <= '0'; --- pwm_write_ii <= '0'; --- --- if flash_command = '0' and ufm_bus_ready_out = '1' then --- -- copy data from UFM to registers --- ufm_bus_ready_in <= '1'; --- case to_integer ( ufm_databyte_counter ) is --- when 0 => ram_temp <= flashram_data_o; --- when 1 => ram_data(0)(15 downto 0) <= flashram_data_o & ram_temp; --- when 2 => ram_temp <= flashram_data_o; --- when 3 => ram_data(1)(15 downto 0) <= flashram_data_o & ram_temp; --- when others => null; --- end case ; --- --- elsif flash_command = '1' and ufm_bus_ready_out = '1' then --- -- save data from registers to UFM --- ufm_bus_ready_in <= '1'; --- case to_integer ( ufm_databyte_counter ) is --- when 0 => flashram_data_i <= ram_data(1)( 7 downto 0); --- when 1 => flashram_data_i <= ram_data(1)(15 downto 8); --- --when 2 => flashram_data_i <= ram_data(1)( 7 downto 0); --- --when 3 => flashram_data_i <= ram_data(1)(15 downto 8); --- when others => null ; --- end case ; --- --- elsif ram_data_f_spi_write = '1' then --- ram_data(1) <= reg_spi; --- elsif ram_data_f_spi_read = '1' then --- reg_spi_o <= ram_data(1); --- end if ; - - - -PROC_REGS_FLASH: process begin -wait until rising_edge( clk_i ); - ufm_bus_ready_in <= '0'; - pwm_write_ii <= '0'; - if flash_command = '0' and ufm_bus_ready_out = '1' then - -- copy data from UFM to registers - ufm_bus_ready_in <= '1'; - case to_integer ( ufm_databyte_counter ) is - when 0 => flash_temp <= flashram_data_o; - when 1 => ram_data( 0) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "00000"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 2 => flash_temp <= flashram_data_o; - when 3 => ram_data( 1) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "00001"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 4 => flash_temp <= flashram_data_o; - when 5 => ram_data( 2) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "00010"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 6 => flash_temp <= flashram_data_o; - when 7 => ram_data( 3) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "00011"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 8 => flash_temp <= flashram_data_o; - when 9 => ram_data( 4) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "00100"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 10 => flash_temp <= flashram_data_o; - when 11 => ram_data( 5) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "00101"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 12 => flash_temp <= flashram_data_o; - when 13 => ram_data( 6) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "00110"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 14 => flash_temp <= flashram_data_o; - when 15 => ram_data( 7) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "00111"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 16 => flash_temp <= flashram_data_o; - when 17 => ram_data( 8) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "01000"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 18 => flash_temp <= flashram_data_o; - when 19 => ram_data( 9) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "01001"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 20 => flash_temp <= flashram_data_o; - when 21 => ram_data(10) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "01010"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 22 => flash_temp <= flashram_data_o; - when 23 => ram_data(11) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "01011"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 24 => flash_temp <= flashram_data_o; - when 25 => ram_data(12) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "01100"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 26 => flash_temp <= flashram_data_o; - when 27 => ram_data(13) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "01101"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 28 => flash_temp <= flashram_data_o; - when 29 => ram_data(14) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "01110"; - pwm_data_ii <= flashram_data_o & flash_temp; - when 30 => flash_temp <= flashram_data_o; - when 31 => ram_data(15) <= flashram_data_o & flash_temp; - pwm_write_ii <= '1'; - pwm_addr_ii <= "01111"; - pwm_data_ii <= flashram_data_o & flash_temp; - when others => null; - end case ; - - elsif flash_command = '1' and ufm_bus_ready_out = '1' then - -- save data from registers to UFM - ufm_bus_ready_in <= '1'; - case to_integer ( ufm_databyte_counter ) is - when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0); - when 1 => flashram_data_i <= ram_data( 0)(15 downto 8); - when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0); - when 3 => flashram_data_i <= ram_data( 1)(15 downto 8); - when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0); - when 5 => flashram_data_i <= ram_data( 2)(15 downto 8); - when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0); - when 7 => flashram_data_i <= ram_data( 3)(15 downto 8); - when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0); - when 9 => flashram_data_i <= ram_data( 4)(15 downto 8); - when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0); - when 11 => flashram_data_i <= ram_data( 5)(15 downto 8); - when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0); - when 13 => flashram_data_i <= ram_data( 6)(15 downto 8); - when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0); - when 15 => flashram_data_i <= ram_data( 7)(15 downto 8); - when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0); - when 17 => flashram_data_i <= ram_data( 8)(15 downto 8); - when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0); - when 19 => flashram_data_i <= ram_data( 9)(15 downto 8); - when 20 => flashram_data_i <= ram_data(10)( 7 downto 0); - when 21 => flashram_data_i <= ram_data(10)(15 downto 8); - when 22 => flashram_data_i <= ram_data(11)( 7 downto 0); - when 23 => flashram_data_i <= ram_data(11)(15 downto 8); - when 24 => flashram_data_i <= ram_data(12)( 7 downto 0); - when 25 => flashram_data_i <= ram_data(12)(15 downto 8); - when 26 => flashram_data_i <= ram_data(13)( 7 downto 0); - when 27 => flashram_data_i <= ram_data(13)(15 downto 8); - when 28 => flashram_data_i <= ram_data(14)( 7 downto 0); - when 29 => flashram_data_i <= ram_data(14)(15 downto 8); - when 30 => flashram_data_i <= ram_data(15)( 7 downto 0); - when 31 => flashram_data_i <= ram_data(15)(15 downto 8); - when others => null ; - end case ; - - elsif ram_spi_write = '1' then - ram_data(to_integer(unsigned(ram_spi_addr))) <= ram_spi_data; - end if ; -end process ; - - - + end architecture; -- 2.43.0