From d78402a97887a51f7311350e5adbae6ab16ceebf Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 4 Feb 2022 13:39:19 +0100 Subject: [PATCH] SCI poll time changed, cleanup --- media_interfaces/sync/main_rx_reset_RS.vhd | 17 ++--------------- media_interfaces/sync/sci_reader_RS.vhd | 2 +- 2 files changed, 3 insertions(+), 16 deletions(-) diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd index 96bc90b..aec6701 100644 --- a/media_interfaces/sync/main_rx_reset_RS.vhd +++ b/media_interfaces/sync/main_rx_reset_RS.vhd @@ -30,13 +30,9 @@ architecture main_rx_reset_RS_arch of main_rx_reset_RS is -- Without this piece of code, many things would have been a real pain. constant Tshort_bit : integer := 4; -- count up to 2^4 = 16 --- constant Tshort : unsigned(31 downto 0) := x"0000000a"; constant Tplol_bit : integer := 22; --- constant Tplol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; constant Tcdr_bit : integer := 22; --- constant Tcdr : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; constant Tviol_bit : integer := 22; --- constant Tviol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; signal pll_lol_s : std_logic; signal cdr_lol_s : std_logic; @@ -100,7 +96,6 @@ begin if( (pll_lol_s = '1') or (sd_los_s = '1') ) then cnt <= (others => '0'); else --- if( cnt = Tplol ) then if( cnt(Tplol_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= APPLY_CDR_RST; @@ -114,7 +109,6 @@ begin RX_SERDES_RST_OUT <= '1'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; --- if( cnt = Tshort ) then if( cnt(Tshort_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= WAIT_CDR_LOCK; @@ -127,7 +121,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; --- if( cnt = Tcdr ) then if( cnt(Tcdr_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= TEST_CDR; @@ -144,7 +137,6 @@ begin cnt <= (others => '0'); rx_sm <= APPLY_CDR_RST; else --- if( cnt = Tcdr ) then if( cnt(Tcdr_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= APPLY_RXPCS_RST; @@ -158,7 +150,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; --- if( cnt = Tshort ) then if( cnt(Tshort_bit) ) then cnt <= (others => '0'); rx_sm <= WAIT_RXPCS_LOCK; @@ -171,7 +162,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; --- if( cnt = Tviol ) then if( cnt(Tviol_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= TEST_RXPCS; @@ -188,7 +178,6 @@ begin cnt <= (others => '0'); rx_sm <= APPLY_RXPCS_RST; else --- if( cnt = Tviol ) then if( cnt(Tviol_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= CHECK_WAP; @@ -203,7 +192,6 @@ begin RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; cnt <= (others => '0'); --- if( cnt = Tshort ) then if( cnt(Tshort_bit) = '1' ) then cnt <= (others => '0'); if( wap_zero_s = '1' ) then @@ -238,8 +226,6 @@ begin end case; ------------------------------------------------ --- if (pll_lol_s = '1') or (los_s = '1') then --- if( pll_lol_s = '1' ) then if( (pll_lol_s = '1') or (sd_los_s = '1') ) then rx_sm <= POWERUP; cnt <= (others => '0'); @@ -248,6 +234,7 @@ begin end if; end process rx_reset_proc; - WAP_REQ_OUT <= '1' when ((rx_sm = WAIT_RXPCS_LOCK) or (rx_sm = TEST_RXPCS)) else '0'; +-- WAP_REQ_OUT <= '1' when ((rx_sm = WAIT_RXPCS_LOCK) or (rx_sm = TEST_RXPCS)) else '0'; + WAP_REQ_OUT <= '1' when ((rx_sm = TEST_RXPCS)) else '0'; end architecture; diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd index 3178438..0898aaf 100644 --- a/media_interfaces/sync/sci_reader_RS.vhd +++ b/media_interfaces/sync/sci_reader_RS.vhd @@ -39,7 +39,7 @@ architecture sci_reader_arch of sci_reader_RS is type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); signal sci_state : sci_ctrl; -signal sci_timer : unsigned(14 downto 0) := (others => '0'); +signal sci_timer : unsigned(16 downto 0) := (others => '0'); signal sci_reg_i : std_logic; signal wa_position : std_logic_vector(15 downto 0); -- 2.43.0