From d7ae7bcf25abf6f54ca179c4bfaf7c93991ad330 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Fri, 22 Mar 2013 14:16:48 +0000
Subject: [PATCH] added link for txt files

---
 base/linkdesignfiles.sh  | 19 +++++++++++++++++++
 base/trb3_components.vhd | 11 +++++++++++
 2 files changed, 30 insertions(+)
 create mode 100755 base/linkdesignfiles.sh

diff --git a/base/linkdesignfiles.sh b/base/linkdesignfiles.sh
new file mode 100755
index 0000000..4d26041
--- /dev/null
+++ b/base/linkdesignfiles.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+#These files should be linked in your workdir for new projects
+#they have to be in the directory were all the reports and bitfiles end up!
+#usually ./workdir (command line script) or ./$PROJECTNAME (Diamond)
+
+
+ln -s ../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ngo
+ln -s ../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.ngo
+ln -s ../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn208256208256.ngo
+ln -s ../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn96649664.ngo
+ln -s ../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.txt
+ln -s ../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt
+ln -s ../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.txt
+ln -s ../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt
+ln -s ../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.txt
+ln -s ../../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.txt
+ln -s ../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.txt
+ln -s ../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_125_0.txt
+
diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index f7c16b9..07a5716 100644
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -24,6 +24,17 @@ package trb3_components is
 --       );
 --   end component;
 
+
+component oddr is
+    port (
+        clk: in  std_logic; 
+        clkout: out  std_logic; 
+        da: in  std_logic_vector(0 downto 0); 
+        db: in  std_logic_vector(0 downto 0); 
+        q: out  std_logic_vector(0 downto 0));
+end component;
+
+
   component pll_in125_out125
     port (
       CLK   : in  std_logic;
-- 
2.43.0