From d7eee48f7453f4a9b44fdc4457cdbfcc8d02817d Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Mon, 14 Nov 2011 15:33:11 +0000
Subject: [PATCH] *** empty log message ***

---
 base/trb3_periph.lpf             |  8 +++++---
 base/trb3_periph.vhd             | 15 ++++++++++++++-
 base/trb3_periph_ada.lpf         |  6 +++---
 base/trb3_periph_constraints.lpf |  4 ++--
 4 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/base/trb3_periph.lpf b/base/trb3_periph.lpf
index 4276f17..92a7d52 100644
--- a/base/trb3_periph.lpf
+++ b/base/trb3_periph.lpf
@@ -7,10 +7,11 @@ BLOCK RD_DURING_WR_PATHS ;
 #################################################################
 
   SYSCONFIG MCCLK_FREQ = 2.5;
+
   FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
   FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  100 MHz;
+  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 
 #################################################################
 # Clock I/O
@@ -33,8 +34,9 @@ IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25;
 #Trigger from fan-out
 LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
 LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
-IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25; 
-IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25;
+IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; 
+IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 ;
+
 
 
 
diff --git a/base/trb3_periph.vhd b/base/trb3_periph.vhd
index 8986c17..72dccf8 100644
--- a/base/trb3_periph.vhd
+++ b/base/trb3_periph.vhd
@@ -139,7 +139,12 @@ architecture trb3_periph_arch of trb3_periph is
   signal trg_code_i            : std_logic_vector(7 downto 0);
   signal trg_information_i     : std_logic_vector(23 downto 0);
   signal trg_int_number_i      : std_logic_vector(15 downto 0);
-
+  signal trg_multiple_trg_i    : std_logic;
+  signal trg_timeout_detected_i: std_logic;
+  signal trg_spurious_trg_i    : std_logic;
+  signal trg_missing_tmg_trg_i : std_logic;
+  signal trg_spike_detected_i  : std_logic;
+  
   --Data channel
   signal fee_trg_release_i    : std_logic;
   signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
@@ -248,6 +253,7 @@ begin
 ---------------------------------------------------------------------------
 -- Clock Handling
 ---------------------------------------------------------------------------
+
   THE_MAIN_PLL : pll_in200_out100
     port map(
       CLK   => CLK_GPLL_RIGHT,
@@ -353,6 +359,13 @@ begin
       LVL1_TRG_INFORMATION_OUT => trg_information_i,
       LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
 
+      --Information about trigger handler errors
+      TRG_MULTIPLE_TRG_OUT         => trg_multiple_trg_i,
+      TRG_TIMEOUT_DETECTED_OUT     => trg_timeout_detected_i,
+      TRG_SPURIOUS_TRG_OUT         => trg_spurious_trg_i,
+      TRG_MISSING_TMG_TRG_OUT      => trg_missing_tmg_trg_i,
+      TRG_SPIKE_DETECTED_OUT       => trg_spike_detected_i,
+      
       --Response from FEE
       FEE_TRG_RELEASE_IN(0)       => fee_trg_release_i,
       FEE_TRG_STATUSBITS_IN       => fee_trg_statusbits_i,
diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf
index 073eb80..f918879 100644
--- a/base/trb3_periph_ada.lpf
+++ b/base/trb3_periph_ada.lpf
@@ -105,7 +105,7 @@ LOCATE COMP  "CLK_GPLL_RIGHT"       SITE "W1";
 LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
 
 DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25 ;
 
 
 #################################################################
@@ -115,8 +115,8 @@ IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 #Trigger from fan-out
 LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
 LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
-IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; 
-IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25; 
+IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25;
 
 
 
diff --git a/base/trb3_periph_constraints.lpf b/base/trb3_periph_constraints.lpf
index aa9e43b..9441786 100644
--- a/base/trb3_periph_constraints.lpf
+++ b/base/trb3_periph_constraints.lpf
@@ -7,11 +7,11 @@ BLOCK RD_DURING_WR_PATHS ;
 #################################################################
 
   SYSCONFIG MCCLK_FREQ = 2.5;
+
   FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
   FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  100 MHz;
-
+  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
   
 #################################################################
 # Reset Nets
-- 
2.43.0