From d80c1b5b8450e20e0c42e62cc2d62ce82bed32fa Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 14 Dec 2015 13:50:09 +0100 Subject: [PATCH] some fixes to new 32PinAddOn design - slow control fine. --- 32PinAddOn/compile_constraints_frankfurt.pl | 8 +++++--- 32PinAddOn/compile_periph_frankfurt.pl | 10 ++++++---- 32PinAddOn/trb3_periph_32PinAddOn.prj | 2 +- base/code/trb3_tools.vhd | 14 ++++++++++---- 4 files changed, 22 insertions(+), 12 deletions(-) diff --git a/32PinAddOn/compile_constraints_frankfurt.pl b/32PinAddOn/compile_constraints_frankfurt.pl index 3c6e4d9..de79f05 100755 --- a/32PinAddOn/compile_constraints_frankfurt.pl +++ b/32PinAddOn/compile_constraints_frankfurt.pl @@ -7,7 +7,9 @@ my $TOPNAME = "trb3_periph_32PinAddOn"; #Name of top-level #create full lpf file -system("cp ../base/trb3_periph_32PinAddOn.lpf workdir/$TOPNAME.lpf"); -system("cat currentRelease/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf"); -system("cat currentRelease/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); +system("cp ../base/$TOPNAME.lpf workdir/diamond/$TOPNAME.lpf"); +system("cat tdc_release/trbnet_constraints.lpf >> workdir/diamond/$TOPNAME.lpf"); +system("cat tdc_release/tdc_constraints_64.lpf >> workdir/diamond/$TOPNAME.lpf"); +system("cat tdc_release/unimportant_lines_constraints.lpf >> workdir/diamond/$TOPNAME.lpf"); +system("cat unimportant_lines_constraints.lpf >> workdir/diamond/$TOPNAME.lpf"); diff --git a/32PinAddOn/compile_periph_frankfurt.pl b/32PinAddOn/compile_periph_frankfurt.pl index 315c8d2..1929e70 100755 --- a/32PinAddOn/compile_periph_frankfurt.pl +++ b/32PinAddOn/compile_periph_frankfurt.pl @@ -31,12 +31,14 @@ my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; my $PACKAGE="FPBGA672"; my $SPEEDGRADE="8"; - +my $WORKDIR = "workdir"; #create full lpf file -system("cp ../base/trb3_periph_32PinAddOn.lpf workdir/$TOPNAME.lpf"); -system("cat currentRelease/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf"); -system("cat currentRelease/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); +system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); +system("cat tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat tdc_release/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); #set -e diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj index c7ec0a7..2692802 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.prj +++ b/32PinAddOn/trb3_periph_32PinAddOn.prj @@ -163,7 +163,7 @@ add_file -vhdl -lib work "tdc_release/bit_sync.vhd" add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" add_file -vhdl -lib work "tdc_release/Channel_200.vhd" add_file -vhdl -lib work "tdc_release/Channel.vhd" -add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" add_file -vhdl -lib work "tdc_release/hit_mux.vhd" add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" diff --git a/base/code/trb3_tools.vhd b/base/code/trb3_tools.vhd index 84f9375..b7eb11b 100644 --- a/base/code/trb3_tools.vhd +++ b/base/code/trb3_tools.vhd @@ -84,8 +84,8 @@ begin THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( PORT_NUMBER => 7, - PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 3 => x"0500", 4 => x"0600", 5 => x"0180", 6 => x"0f00", 7 => x"0f80", others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 5, 3 => 1, 4 => 2, 5 => 4, 6 => 7, 7 => 7, others => 0), + PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0500", 3 => x"0600", 4 => x"0180", 5 => x"0f00", 6 => x"0f80", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 1, 3 => 2, 4 => 4, 5 => 7, 6 => 7, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -232,9 +232,11 @@ end generate; SPI_MOSI_OUT <= (others => spi_sdo); SPI_CLR_OUT <= spi_clr; spi_sdi <= or_all(SPI_MISO_IN and not spi_cs); - + busspi_tx.unknown <= '0'; + end generate; + gen_noSPI_LOGIC : if INCLUDE_SPI = 0 generate + busspi_tx.unknown <= busspi_rx.read or busspi_rx.write; end generate; - busspi_tx.unknown <= '0'; --------------------------------------------------------------------------- -- UART @@ -253,6 +255,9 @@ end generate; BUS_TX => busuart_tx ); end generate; + gen_noUART_LOGIC : if INCLUDE_UART = 0 generate + busuart_tx.unknown <= busuart_rx.read or busuart_rx.write; + end generate; --------------------------------------------------------------------------- -- Debug Connection @@ -282,6 +287,7 @@ gen_nodebug : if INCLUDE_DEBUG_INTERFACE = 0 generate bus_debug_rx_out.addr <= (others => '0'); bus_debug_rx_out.data <= (others => '0'); debug_tx <= 'Z'; + debug_active <= '0'; end generate; --------------------------------------------------------------------------- -- 2.43.0