From d8306cd951a5696b88790bca16f1de803eeafe61 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 16 Sep 2011 18:14:46 +0000 Subject: [PATCH] First TrbNet implementation finished, Jan --- README | 12 +- base/trb3_central.lpf | 67 ++--- base/trb3_central.prj | 2 + base/trb3_central.vhd | 60 ++--- base/trb3_central_constraints.lpf | 8 +- base/trb3_periph.lpf | 10 +- base/trb3_periph.prj | 82 ++++++ base/trb3_periph.vhd | 408 +++++++++++++++++++++++++++-- base/trb3_periph_constraints.lpf | 32 +++ fpgatest/projects/trb3_central.ldf | 237 +++++++++++------ 10 files changed, 740 insertions(+), 178 deletions(-) create mode 100644 base/trb3_periph_constraints.lpf diff --git a/README b/README index 7a21b6c..23c0d96 100644 --- a/README +++ b/README @@ -91,12 +91,12 @@ The upper 16 bit of the REGIO_HARDWARE_VERSION generic of the TrbNet endpoint ha ==================== REGIO_INIT_ADDRESS gives the default network address -- 0xFF30 for the central FPGA -- 0xFF35 for peripheral FPGAs -- 0xFF31 for FPGA 1 only -- 0xFF32 for FPGA 2 only -- 0xFF33 for FPGA 3 only -- 0xFF34 for FPGA 4 only +- 0xF300 for the central FPGA +- 0xF305 for peripheral FPGAs +- 0xF301 for FPGA 1 only +- 0xF302 for FPGA 2 only +- 0xF303 for FPGA 3 only +- 0xF304 for FPGA 4 only BROADCAST_SPECIAL_ADDR has to be set to address all FPGA of a given type within a setup: - 0x40 for the central FPGA diff --git a/base/trb3_central.lpf b/base/trb3_central.lpf index c0f56a6..2e34a50 100644 --- a/base/trb3_central.lpf +++ b/base/trb3_central.lpf @@ -453,40 +453,41 @@ IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; ################################################################# -# Test Connector +# Test Connector (Order corrected to match pin-out of connector!) ################################################################# -LOCATE COMP "TEST_LINE_0" SITE "G4"; -LOCATE COMP "TEST_LINE_1" SITE "G5"; -LOCATE COMP "TEST_LINE_2" SITE "H5"; -LOCATE COMP "TEST_LINE_3" SITE "H4"; -LOCATE COMP "TEST_LINE_4" SITE "F2"; -LOCATE COMP "TEST_LINE_5" SITE "F1"; -LOCATE COMP "TEST_LINE_6" SITE "F3"; -LOCATE COMP "TEST_LINE_7" SITE "E3"; -LOCATE COMP "TEST_LINE_8" SITE "G2"; -LOCATE COMP "TEST_LINE_9" SITE "G1"; -LOCATE COMP "TEST_LINE_10" SITE "G3"; -LOCATE COMP "TEST_LINE_11" SITE "H3"; -LOCATE COMP "TEST_LINE_12" SITE "H1"; -LOCATE COMP "TEST_LINE_13" SITE "J1"; -LOCATE COMP "TEST_LINE_14" SITE "J3"; -LOCATE COMP "TEST_LINE_15" SITE "H2"; -LOCATE COMP "TEST_LINE_16" SITE "K4"; -LOCATE COMP "TEST_LINE_17" SITE "K3"; -LOCATE COMP "TEST_LINE_18" SITE "K7"; -LOCATE COMP "TEST_LINE_19" SITE "J6"; -LOCATE COMP "TEST_LINE_20" SITE "K2"; -LOCATE COMP "TEST_LINE_21" SITE "K1"; -LOCATE COMP "TEST_LINE_22" SITE "L10"; -LOCATE COMP "TEST_LINE_23" SITE "L9"; -LOCATE COMP "TEST_LINE_24" SITE "L2"; -LOCATE COMP "TEST_LINE_25" SITE "L1"; -LOCATE COMP "TEST_LINE_26" SITE "M8"; -LOCATE COMP "TEST_LINE_27" SITE "L7"; -LOCATE COMP "TEST_LINE_28" SITE "L5"; -LOCATE COMP "TEST_LINE_29" SITE "L4"; -LOCATE COMP "TEST_LINE_30" SITE "K6"; -LOCATE COMP "TEST_LINE_31" SITE "K5"; +LOCATE COMP "TEST_LINE_4" SITE "G4"; # "TEST_LINE_0" +LOCATE COMP "TEST_LINE_5" SITE "G5"; # "TEST_LINE_1" +LOCATE COMP "TEST_LINE_2" SITE "H5"; # "TEST_LINE_2" +LOCATE COMP "TEST_LINE_3" SITE "H4"; # "TEST_LINE_3" +LOCATE COMP "TEST_LINE_10" SITE "F2"; # "TEST_LINE_4" +LOCATE COMP "TEST_LINE_11" SITE "F1"; # "TEST_LINE_5" +LOCATE COMP "TEST_LINE_6" SITE "F3"; # "TEST_LINE_6" +LOCATE COMP "TEST_LINE_7" SITE "E3"; # "TEST_LINE_7" +LOCATE COMP "TEST_LINE_12" SITE "G2"; # "TEST_LINE_8" +LOCATE COMP "TEST_LINE_13" SITE "G1"; # "TEST_LINE_9" +LOCATE COMP "TEST_LINE_8" SITE "G3"; # "TEST_LINE_10" +LOCATE COMP "TEST_LINE_9" SITE "H3"; # "TEST_LINE_11" +LOCATE COMP "TEST_LINE_14" SITE "H1"; # "TEST_LINE_12" +LOCATE COMP "TEST_LINE_15" SITE "J1"; # "TEST_LINE_13" +LOCATE COMP "TEST_LINE_0" SITE "J3"; # "TEST_LINE_14" +LOCATE COMP "TEST_LINE_1" SITE "H2"; # "TEST_LINE_15" + +LOCATE COMP "TEST_LINE_20" SITE "K4"; # "TEST_LINE_16" +LOCATE COMP "TEST_LINE_21" SITE "K3"; # "TEST_LINE_17" +LOCATE COMP "TEST_LINE_26" SITE "K7"; # "TEST_LINE_18" +LOCATE COMP "TEST_LINE_27" SITE "J6"; # "TEST_LINE_19" +LOCATE COMP "TEST_LINE_16" SITE "K2"; # "TEST_LINE_20" +LOCATE COMP "TEST_LINE_17" SITE "K1"; # "TEST_LINE_21" +LOCATE COMP "TEST_LINE_30" SITE "L10"; # "TEST_LINE_22" +LOCATE COMP "TEST_LINE_31" SITE "L9"; # "TEST_LINE_23" +LOCATE COMP "TEST_LINE_18" SITE "L2"; # "TEST_LINE_24" +LOCATE COMP "TEST_LINE_19" SITE "L1"; # "TEST_LINE_25" +LOCATE COMP "TEST_LINE_28" SITE "M8"; # "TEST_LINE_26" +LOCATE COMP "TEST_LINE_29" SITE "L7"; # "TEST_LINE_27" +LOCATE COMP "TEST_LINE_22" SITE "L5"; # "TEST_LINE_28" +LOCATE COMP "TEST_LINE_23" SITE "L4"; # "TEST_LINE_29" +LOCATE COMP "TEST_LINE_24" SITE "K6"; # "TEST_LINE_30" +LOCATE COMP "TEST_LINE_25" SITE "K5"; # "TEST_LINE_31" DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; diff --git a/base/trb3_central.prj b/base/trb3_central.prj index a2d34d0..61c4b04 100644 --- a/base/trb3_central.prj +++ b/base/trb3_central.prj @@ -99,6 +99,8 @@ add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" + add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" diff --git a/base/trb3_central.vhd b/base/trb3_central.vhd index b119be9..6359c1d 100644 --- a/base/trb3_central.vhd +++ b/base/trb3_central.vhd @@ -194,8 +194,6 @@ architecture trb3_central_arch of trb3_central is signal spi_bram_rd_d : std_logic_vector(7 downto 0); signal spi_bram_we : std_logic; - signal delayed_restart_fpga : std_logic; - signal restart_fpga_counter : unsigned(11 downto 0); begin @@ -316,9 +314,9 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard SD_LOS_IN(2) => FPGA3_COMM(2), SD_LOS_IN(3) => FPGA4_COMM(2), SD_TXDIS_OUT(0) => FPGA1_COMM(0), - SD_TXDIS_OUT(1) => FPGA1_COMM(1), - SD_TXDIS_OUT(2) => FPGA1_COMM(2), - SD_TXDIS_OUT(3) => FPGA1_COMM(3), + SD_TXDIS_OUT(1) => FPGA2_COMM(0), + SD_TXDIS_OUT(2) => FPGA3_COMM(0), + SD_TXDIS_OUT(3) => FPGA4_COMM(0), -- Status and control port STAT_OP => med_stat_op(63 downto 0), CTRL_OP => med_ctrl_op(63 downto 0), @@ -347,7 +345,7 @@ THE_HUB : trb_net16_hub_base HARDWARE_VERSION => x"90000000", INIT_ENDPOINT_ID => x"0005", INIT_ADDRESS => x"F305", - BROADCAST_SPECIAL_ADDR => x"15" + BROADCAST_SPECIAL_ADDR => x"40" ) port map ( CLK => clk_100_i, @@ -496,27 +494,15 @@ THE_SPI_MEMORY: spi_databus_memory --------------------------------------------------------------------------- -- Reboot FPGA --------------------------------------------------------------------------- - PROC_REBOOT : process - begin - wait until rising_edge(clk_100_i); - if reset_i = '1' then - PROGRAMN <= '1'; - delayed_restart_fpga <= '0'; - restart_fpga_counter <= x"FFF"; - else - PROGRAMN <= not delayed_restart_fpga; - delayed_restart_fpga <= '0'; - if common_ctrl_regs(15) = '1' then - restart_fpga_counter <= x"000"; - elsif restart_fpga_counter /= x"FFF" then - restart_fpga_counter <= restart_fpga_counter + 1; - if restart_fpga_counter >= x"F00" then - delayed_restart_fpga <= '1'; - end if; - end if; - end if; - end process; +THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_regs(15), + PROGRAMN => PROGRAMN + ); + --------------------------------------------------------------------------- -- Clock and Trigger Configuration --------------------------------------------------------------------------- @@ -530,10 +516,10 @@ THE_SPI_MEMORY: spi_databus_memory --------------------------------------------------------------------------- -- FPGA communication --------------------------------------------------------------------------- - FPGA1_COMM <= (others => 'Z'); - FPGA2_COMM <= (others => 'Z'); - FPGA3_COMM <= (others => 'Z'); - FPGA4_COMM <= (others => 'Z'); +-- FPGA1_COMM <= (others => 'Z'); +-- FPGA2_COMM <= (others => 'Z'); +-- FPGA3_COMM <= (others => 'Z'); +-- FPGA4_COMM <= (others => 'Z'); FPGA1_TTL <= (others => 'Z'); FPGA2_TTL <= (others => 'Z'); @@ -561,18 +547,24 @@ THE_SPI_MEMORY: spi_databus_memory --------------------------------------------------------------------------- LED_CLOCK_GREEN <= '0'; LED_CLOCK_RED <= '1'; - LED_GREEN <= '0'; - LED_ORANGE <= '1'; + LED_GREEN <= not med_stat_op(9); + LED_YELLOW <= not med_stat_op(10); + LED_ORANGE <= not med_stat_op(11); LED_RED <= '1'; LED_TRIGGER_GREEN <= not med_stat_op(4*16+9); LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10)); - LED_YELLOW <= '1'; --------------------------------------------------------------------------- -- Test Connector --------------------------------------------------------------------------- - TEST_LINE <= (others => '0'); + + TEST_LINE(7 downto 0) <= med_data_in(7 downto 0); + TEST_LINE(8) <= med_dataready_in(0); + TEST_LINE(9) <= med_dataready_out(0); + + + TEST_LINE(31 downto 10) <= (others => '0'); --------------------------------------------------------------------------- diff --git a/base/trb3_central_constraints.lpf b/base/trb3_central_constraints.lpf index 32f0bee..06e5adb 100644 --- a/base/trb3_central_constraints.lpf +++ b/base/trb3_central_constraints.lpf @@ -27,9 +27,9 @@ GSR_NET NET "GSR_N"; LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_MEDIA_ONBOARD/THE_SERDES/PCSD_INST" SITE "PCSC" ; -#REGION "MEDIA_UPLINK" CLKREG "CLKREG_R6C4" 1 1; -REGION "MEDIA_UPLINK" "R88C92" 18 27; + +REGION "MEDIA_UPLINK" "R98C95" 17 27; LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; -REGION "MEDIA_ONBOARD" "R88C122" 40 27; -LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ; +REGION "MEDIA_ONBOARD" "R90C122" 25 40; +LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ; diff --git a/base/trb3_periph.lpf b/base/trb3_periph.lpf index 0bd7816..c4971cb 100644 --- a/base/trb3_periph.lpf +++ b/base/trb3_periph.lpf @@ -56,7 +56,7 @@ LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; LOCATE COMP "FPGA5_COMM_10" SITE "V10"; LOCATE COMP "FPGA5_COMM_11" SITE "W10"; DEFINE PORT GROUP "FPGA_group" "FPGA*" ; -IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8 ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; LOCATE COMP "TEST_LINE_0" SITE "A5"; LOCATE COMP "TEST_LINE_1" SITE "A6"; @@ -295,7 +295,7 @@ LOCATE COMP "FLASH_DIN" SITE "E12"; LOCATE COMP "FLASH_DOUT" SITE "A12"; DEFINE PORT GROUP "FLASH_group" "FLASH*" ; -IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; LOCATE COMP "PROGRAMN" SITE "B11"; IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; @@ -305,13 +305,13 @@ IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; # Misc ################################################################# LOCATE COMP "TEMPSENS" SITE "A13"; -IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; #coding of FPGA number LOCATE COMP "CODE_LINE_1" SITE "AA20"; LOCATE COMP "CODE_LINE_0" SITE "Y21"; -IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; #terminated differential pair to pads LOCATE COMP "SUPPL" SITE "C14"; diff --git a/base/trb3_periph.prj b/base/trb3_periph.prj index 2a86381..f8865b1 100644 --- a/base/trb3_periph.prj +++ b/base/trb3_periph.prj @@ -56,6 +56,88 @@ add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" add_file -vhdl -lib "work" "../base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +# add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_8bit_16bit_bram_dualport.vhd" +# add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_8b_16b_dualport.vhd" +# add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16b_16b_dualport.vhd" +# add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" + +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "./trb3_periph.vhd" diff --git a/base/trb3_periph.vhd b/base/trb3_periph.vhd index 8f140da..a002c89 100644 --- a/base/trb3_periph.vhd +++ b/base/trb3_periph.vhd @@ -92,39 +92,296 @@ entity trb3_periph is attribute syn_useioff of DQLR : signal is true; attribute syn_useioff of DQUR : signal is true; attribute syn_useioff of SPARE_LINE : signal is true; - attribute syn_useioff of FPGA5_COMM : signal is true; + end entity; architecture trb3_periph_arch of trb3_periph is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 2; + constant REGIO_NUM_CTRL_REGS : integer := 2; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - --TDC clock is separate signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal my_address : std_logic_vector (15 downto 0); + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; --FPGA Test signal time_counter : unsigned(31 downto 0); begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + +GSR_N <= pll_lock; + +THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + --------------------------------------------------------------------------- -- Clock Handling --------------------------------------------------------------------------- - THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => CLK_GPLL_LEFT, - CLKOP => clk_100_i, - CLKOK => clk_200_i, - LOCK => pll_lock - ); +THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); --------------------------------------------------------------------------- --- FPGA communication +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- +THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES --run on 200 MHz clock + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + --------------------------------------------------------------------------- - FPGA5_COMM <= (others => '0'); +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,--4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,--3, --8 cotrol reg + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + REGIO_HARDWARE_VERSION => x"91000001", + REGIO_INIT_ADDRESS => x"f300", + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => 100, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024 + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2)=> (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT=> open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); --------------------------------------------------------------------------- -- AddOn @@ -134,28 +391,139 @@ begin DQLR <= (others => '0'); DQUR <= (others => '0'); +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- +THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 2, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + + STAT_DEBUG => open + ); --------------------------------------------------------------------------- --- Flash ROM +-- SPI / Flash --------------------------------------------------------------------------- - FLASH_CLK <= '0'; - FLASH_CS <= '0'; - FLASH_CIN <= '0'; - PROGRAMN <= '1'; + +THE_SPI_MASTER: spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_CIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + +-- data memory for SPI accesses +THE_SPI_MEMORY: spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- +THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_GREEN <= not time_counter(24); - LED_ORANGE <= not time_counter(25); + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); LED_RED <= not time_counter(26); - LED_YELLOW <= not time_counter(27); + LED_YELLOW <= not med_stat_op(11); --------------------------------------------------------------------------- -- Test Connector --------------------------------------------------------------------------- - TEST_LINE <= (others => '0'); + TEST_LINE( 7 downto 0) <= med_data_in(7 downto 0); + TEST_LINE( 8) <= med_dataready_in; + TEST_LINE( 9) <= med_dataready_out; + TEST_LINE(10) <= stat_reg_strobe(0); + TEST_LINE(15 downto 11) <= (others => '0'); --------------------------------------------------------------------------- diff --git a/base/trb3_periph_constraints.lpf b/base/trb3_periph_constraints.lpf new file mode 100644 index 0000000..0d6c128 --- /dev/null +++ b/base/trb3_periph_constraints.lpf @@ -0,0 +1,32 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + + SYSCONFIG MCCLK_FREQ = 20; + + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; + FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; + + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + + + +REGION "MEDIA_UPLINK" "R98C95" 17 27; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + diff --git a/fpgatest/projects/trb3_central.ldf b/fpgatest/projects/trb3_central.ldf index c6c7058..93342ea 100644 --- a/fpgatest/projects/trb3_central.ldf +++ b/fpgatest/projects/trb3_central.ldf @@ -1,90 +1,155 @@ - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + - - + - + -- 2.43.0