From d8be38a1a2c82948dd4a1daa838219f39ab596f1 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Wed, 24 Sep 2014 23:13:44 +0200 Subject: [PATCH] CBM: Timing issues in sync module due to meta-stab seem to be resolved + Improved function of sync module + Typo in port of pos_edge_sync_strech corrected --- cbmnet/code/cbmnet_interface_pkg.vhd | 27 ++- cbmnet/code/cbmnet_sync_module.vhd | 259 ++++++++++++++++++--------- cbmnet/code/pos_edge_strech_sync.vhd | 32 +++- cbmnet/trb3_periph_cbmnet.lpf | 241 +++++-------------------- cbmnet/trb3_periph_cbmnet.vhd | 238 ++++++++++++++---------- cts/trb3_central.vhd | 16 +- cts/trb3_central_syn.fdc | 1 - 7 files changed, 419 insertions(+), 395 deletions(-) diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd index 669f149..84103e6 100644 --- a/cbmnet/code/cbmnet_interface_pkg.vhd +++ b/cbmnet/code/cbmnet_interface_pkg.vhd @@ -529,13 +529,25 @@ package cbmnet_interface_pkg is LENGTH : positive := 2 ); port ( - IN_CLK_IN : std_logic; - DATA_IN : std_logic; - OUT_CLK_IN : std_logic; - DATA_OUT : std_logic + IN_CLK_IN : in std_logic; + DATA_IN : in std_logic; + OUT_CLK_IN : in std_logic; + DATA_OUT : out std_logic ); end component; + component gray_code_sync is + generic ( + WIDTH : positive := 32 + ); + port ( + IN_CLK_IN : in std_logic; + DATA_IN : in std_logic_vector(WIDTH-1 downto 0); + OUT_CLK_IN : in std_logic; + DATA_OUT : out std_logic_vector(WIDTH-1 downto 0) + ); + end component; + component cbmnet_sync_module is port( -- TRB @@ -545,7 +557,8 @@ package cbmnet_interface_pkg is --data output for read-out TRB_TRIGGER_IN : in std_logic; - TRB_RDO_VALID_IN : in std_logic; + TRB_RDO_VALID_DATA_TRG_IN : in std_logic; + TRB_RDO_VALID_NO_TIMING_IN : in std_logic; TRB_RDO_DATA_OUT : out std_logic_vector(31 downto 0); TRB_RDO_WRITE_OUT : out std_logic; TRB_RDO_STATUSBIT_OUT: out std_logic_vector(31 downto 0); @@ -563,8 +576,12 @@ package cbmnet_interface_pkg is -- CBMNET CBM_CLK_IN : in std_logic; + CBM_CLK_250_IN : in std_logic; CBM_RESET_IN : in std_logic; CBM_PHY_BARREL_SHIFTER_POS_IN : in std_logic_vector(3 downto 0); + CBM_LINK_ACTIVE_IN : in std_logic; + + CBM_TIMING_TRIGGER_OUT : out std_logic; -- DLM port CBM_DLM_REC_IN : in std_logic_vector(3 downto 0); diff --git a/cbmnet/code/cbmnet_sync_module.vhd b/cbmnet/code/cbmnet_sync_module.vhd index ddf5853..cc95831 100644 --- a/cbmnet/code/cbmnet_sync_module.vhd +++ b/cbmnet/code/cbmnet_sync_module.vhd @@ -12,7 +12,8 @@ entity cbmnet_sync_module is --data output for read-out TRB_TRIGGER_IN : in std_logic; - TRB_RDO_VALID_IN : in std_logic; + TRB_RDO_VALID_DATA_TRG_IN : in std_logic; + TRB_RDO_VALID_NO_TIMING_IN : in std_logic; TRB_RDO_DATA_OUT : out std_logic_vector(31 downto 0); TRB_RDO_WRITE_OUT : out std_logic; TRB_RDO_STATUSBIT_OUT: out std_logic_vector(31 downto 0); @@ -30,8 +31,12 @@ entity cbmnet_sync_module is -- CBMNET CBM_CLK_IN : in std_logic; + CBM_CLK_250_IN : in std_logic; + CBM_LINK_ACTIVE_IN : in std_logic; + CBM_RESET_IN : in std_logic; CBM_PHY_BARREL_SHIFTER_POS_IN : in std_logic_vector(3 downto 0); + CBM_TIMING_TRIGGER_OUT : out std_logic; -- DLM port CBM_DLM_REC_IN : in std_logic_vector(3 downto 0); @@ -52,13 +57,13 @@ end entity; architecture cbmnet_sync_module_arch of cbmnet_sync_module is -- DETECT DLMs signal trb_dlm_sense_mask_i : std_logic_vector(15 downto 0); - signal cbm_crs_trb_dlm_sense_mask_i : std_logic_vector(15 downto 0); + signal cbm_from_trb_dlm_sense_mask_i : std_logic_vector(15 downto 0); signal cbm_dlm_sensed_i : std_logic; - signal trb_crs_cbm_dlm_sensed_i : std_logic; + signal trb_from_cbm_dlm_sensed_i : std_logic; -- EPOCH - signal cbm_crs_trb_epoch_update_scheme_i : std_logic_vector(1 downto 0); + signal cbm_from_trb_epoch_update_scheme_i : std_logic_vector(1 downto 0); signal cbm_current_epoch_i : std_logic_vector(31 downto 0); signal cbm_current_epoch_updated_i : std_logic; @@ -70,17 +75,17 @@ architecture cbmnet_sync_module_arch of cbmnet_sync_module is signal cbm_next_epoch_updated_i : std_logic; - signal cbm_crs_trb_next_epoch_i : std_logic_vector(31 downto 0); - signal cbm_crs_trb_next_epoch_updated_i : std_logic; - signal trb_crs_cbm_current_epoch_i : std_logic_vector(31 downto 0); - signal trb_crs_cbm_current_epoch_updated_i : std_logic; + signal cbm_from_trb_next_epoch_i : std_logic_vector(31 downto 0); + signal cbm_from_trb_next_epoch_updated_i : std_logic; + signal trb_from_cbm_current_epoch_i : std_logic_vector(31 downto 0); + signal trb_from_cbm_current_epoch_updated_i : std_logic; -- PULSER signal trb_pulser_threshold_i : std_logic_vector(31 downto 0); - signal cbm_crs_trb_pulser_threshold_i : unsigned(31 downto 0); - signal cbm_pulser_i : unsigned(31 downto 0); + signal cbm_from_trb_pulser_threshold_i : unsigned(31 downto 0); + signal cbm_pulser_period_counter_i : unsigned(31 downto 0); signal cbm_pulse_i : std_logic; - signal trb_crs_cbm_pulse_i : std_logic; + signal trb_from_cbm_pulse_i : std_logic; -- TIMESTAMPS signal trb_timestamp_i : unsigned(31 downto 0); @@ -93,16 +98,15 @@ architecture cbmnet_sync_module_arch of cbmnet_sync_module is signal cbm_timestamp_last_pulse_i : unsigned(31 downto 0); signal cbm_reset_counter_i : unsigned(15 downto 0); signal cbm_dlm_counter_i : unsigned(31 downto 0); - signal cbm_pulser_counter_i : unsigned(31 downto 0); - signal cbm_epoch_i : std_logic_vector(31 downto 0); - + signal cbm_pulse_counter_i : unsigned(31 downto 0); + -- same signals as above, but in trbnet clock domain - signal trb_crs_cbm_timestamp_i : unsigned(31 downto 0); - signal trb_crs_cbm_timestamp_last_dlm_i : unsigned(31 downto 0); - signal trb_crs_cbm_timestamp_last_pulse_i : unsigned(31 downto 0); - signal trb_crs_cbm_reset_counter_i : unsigned(15 downto 0); - signal trb_crs_cbm_dlm_counter_i : unsigned(31 downto 0); - signal trb_crs_cbm_pulser_counter_i : unsigned(31 downto 0); + signal trb_from_cbm_timestamp_i : unsigned(31 downto 0); + signal trb_from_cbm_timestamp_last_dlm_i : unsigned(31 downto 0); + signal trb_from_cbm_timestamp_last_pulse_i : unsigned(31 downto 0); + signal trb_from_cbm_reset_counter_i : unsigned(15 downto 0); + signal trb_from_cbm_dlm_counter_i : unsigned(31 downto 0); + signal trb_from_cbm_pulse_counter_i : unsigned(31 downto 0); -- CBMNET slow control @@ -119,25 +123,44 @@ architecture cbmnet_sync_module_arch of cbmnet_sync_module is signal trb_epoch_update_scheme_i : std_logic_vector(1 downto 0); -- TrbNet read-out + constant TRB_RDO_HDR_EXT_MARKER_C : integer := 27; + constant TRB_RDO_HDR_LINK_ACTIVE_C : integer := 26; + type TRB_RDO_BUFFER_T is array (0 to 10) of std_logic_vector(31 downto 0); signal trb_rdo_buffer_i : TRB_RDO_BUFFER_T; type TRB_RDO_FSM_T is (WAIT_FOR_TRIGGER, WAIT_FOR_VALID, COPY_DATA, FINISH); signal trb_rdo_fsm_i : TRB_RDO_FSM_T; signal trb_rdo_fsm_state_i : std_logic_vector(3 downto 0); - signal trb_rdo_counter_i : integer range 0 to 16; + signal trb_rdo_counter_i : integer range 0 to 15; + signal trb_rdo_finished_i : std_logic; + + type CBM_TRB_RDO_FSM_T is (IDLE, WAIT_FOR_RELEASE, WAIT_BEFORE_IDLE); + signal cbm_trb_rdo_fsm_i : CBM_TRB_RDO_FSM_T; + + signal cbm_rdo_registered_i : std_logic; + signal trb_from_cbm_rdo_registered_i : std_logic; + + signal cbm_from_trb_trigger_in : std_logic; + signal cbm_from_trb_trigger_buf_in : std_logic; + signal cbm_from_trb_rdo_valid_no_timing_in : std_logic; + signal cbm_from_trb_rdo_finished_i : std_logic; + signal cbm_from_trb_reset_in : std_logic; begin -- TRBNet read-out TRBNET_READOUT_PROC: process is variable header_v : std_logic_vector(31 downto 0); + + variable valid_trg_v : std_logic; + begin wait until rising_edge(TRB_CLK_IN); header_v := (others => '0'); -- prevent storage TRB_RDO_WRITE_OUT <= '0'; TRB_RDO_STATUSBIT_OUT <= (others => '0'); - TRB_RDO_FINISHED_OUT <= '0'; + trb_rdo_finished_i <= '0'; trb_rdo_counter_i <= 0; if TRB_RESET_IN='1' then @@ -146,57 +169,113 @@ begin case (trb_rdo_fsm_i) is when WAIT_FOR_TRIGGER => trb_rdo_fsm_state_i <= x"0"; - if TRB_TRIGGER_IN = '1' then + valid_trg_v := '0'; + + if TRB_TRIGGER_IN = '1' or TRB_RDO_VALID_NO_TIMING_IN = '1' then -- store data - header_v(31 downto 28) := x"1"; -- version + header_v(31 downto 28) := "0001"; -- version header_v(23 downto 8) := trb_pulser_threshold_i(15 downto 0); header_v( 7 downto 4) := CBM_PHY_BARREL_SHIFTER_POS_IN; - header_v( 3 downto 0) := trb_crs_cbm_current_epoch_updated_i & "0" & trb_epoch_update_scheme_i; + header_v( 3 downto 0) := trb_from_cbm_current_epoch_updated_i & "0" & trb_epoch_update_scheme_i; + + header_v(TRB_RDO_HDR_LINK_ACTIVE_C) := CBM_LINK_ACTIVE_IN; + header_v(TRB_RDO_HDR_EXT_MARKER_C) := CBM_LINK_ACTIVE_IN and not TRB_TRIGGER_IN; + -- signals commented out are registered in the cbm clock domain in the next process trb_rdo_buffer_i( 0) <= header_v; - trb_rdo_buffer_i( 1) <= trb_crs_cbm_current_epoch_i; - trb_rdo_buffer_i( 2) <= trb_crs_cbm_timestamp_i; - trb_rdo_buffer_i( 3) <= trb_crs_cbm_timestamp_last_dlm_i; - trb_rdo_buffer_i( 4) <= trb_crs_cbm_timestamp_last_pulse_i; - trb_rdo_buffer_i( 5) <= trb_timestamp_i; - trb_rdo_buffer_i( 6) <= trb_timestamp_last_dlm_i; - trb_rdo_buffer_i( 7) <= trb_timestamp_last_pulse_i; - trb_rdo_buffer_i( 8) <= trb_crs_cbm_dlm_counter_i; - trb_rdo_buffer_i( 9) <= trb_crs_cbm_pulser_counter_i; - trb_rdo_buffer_i(10) <= STD_LOGIC_VECTOR(trb_reset_counter_i) & STD_LOGIC_VECTOR(trb_crs_cbm_reset_counter_i); + trb_rdo_buffer_i( 1) <= trb_timestamp_i; + -- trb_rdo_buffer_i( 2) <= cbm_timestamp_i; + trb_rdo_buffer_i( 3) <= trb_timestamp_last_pulse_i; + -- trb_rdo_buffer_i( 4) <= cbm_timestamp_last_pulse_i; + -- trb_rdo_buffer_i( 5) <= cbm_current_epoch_i; + -- trb_rdo_buffer_i( 6) <= cbm_timestamp_last_dlm_i; + trb_rdo_buffer_i( 7) <= trb_timestamp_last_dlm_i; + -- trb_rdo_buffer_i( 8) <= cbm_dlm_counter_i; + -- trb_rdo_buffer_i( 9) <= cbm_pulse_counter_i; + trb_rdo_buffer_i(10)(31 downto 16) <= trb_reset_counter_i; + -- trb_rdo_buffer_i(10)(15 downto 0) <= cbm_reset_counter_i; - -- fsm trb_rdo_fsm_i <= WAIT_FOR_VALID; - elsif TRB_RDO_VALID_IN = '1' then - trb_rdo_fsm_i <= FINISH; - end if; when WAIT_FOR_VALID => + valid_trg_v := valid_trg_v or TRB_RDO_VALID_DATA_TRG_IN; + trb_rdo_fsm_state_i <= x"1"; - if TRB_RDO_VALID_IN = '1' then + if (trb_rdo_buffer_i(0)(TRB_RDO_HDR_LINK_ACTIVE_C)='0' or trb_from_cbm_rdo_registered_i = '1') and + valid_trg_v = '1' then trb_rdo_fsm_i <= COPY_DATA; end if; - + + if CBM_LINK_ACTIVE_IN = '0' then + trb_rdo_buffer_i(0)(TRB_RDO_HDR_EXT_MARKER_C) <= '0'; + trb_rdo_buffer_i(0)(TRB_RDO_HDR_LINK_ACTIVE_C) <= '0'; + end if; + when COPY_DATA => trb_rdo_fsm_state_i <= x"2"; TRB_RDO_DATA_OUT <= trb_rdo_buffer_i(trb_rdo_counter_i); TRB_RDO_WRITE_OUT <= '1'; - if trb_rdo_counter_i = TRB_RDO_DATA_OUT'high then + if (trb_rdo_buffer_i(0)(TRB_RDO_HDR_LINK_ACTIVE_C) = '0') or + (trb_rdo_buffer_i(0)(TRB_RDO_HDR_EXT_MARKER_C) = '1' and trb_rdo_counter_i = 10) or + (trb_rdo_buffer_i(0)(TRB_RDO_HDR_EXT_MARKER_C) = '0' and trb_rdo_counter_i = 4) + then trb_rdo_fsm_i <= FINISH; end if; + trb_rdo_counter_i <= trb_rdo_counter_i + 1; when FINISH => trb_rdo_fsm_state_i <= x"3"; - TRB_RDO_FINISHED_OUT <= '1'; + trb_rdo_finished_i <= '1'; trb_rdo_fsm_i <= WAIT_FOR_TRIGGER; - end case; end if; end process; + TRB_RDO_FINISHED_OUT <= trb_rdo_finished_i; + + CBM_TRBNET_READOUT_PROC: process is + variable block_v : std_logic := '0'; + begin + wait until rising_edge(CBM_CLK_IN); + + + if CBM_RESET_IN='1' or cbm_from_trb_reset_in ='1' then + cbm_trb_rdo_fsm_i <= IDLE; + end if; + + cbm_rdo_registered_i <= '0'; + + case (cbm_trb_rdo_fsm_i) is + when IDLE => + if cbm_from_trb_trigger_buf_in = '1' then + CBM_TIMING_TRIGGER_OUT <= '1'; + end if; + + if cbm_from_trb_trigger_in = '1' or cbm_from_trb_rdo_valid_no_timing_in = '1' then + trb_rdo_buffer_i( 2) <= cbm_timestamp_i; + trb_rdo_buffer_i( 4) <= cbm_timestamp_last_pulse_i; + trb_rdo_buffer_i( 5) <= cbm_current_epoch_i; + trb_rdo_buffer_i( 6) <= cbm_timestamp_last_dlm_i; + trb_rdo_buffer_i( 8) <= cbm_dlm_counter_i; + trb_rdo_buffer_i( 9) <= cbm_pulse_counter_i; + trb_rdo_buffer_i(10)(15 downto 0) <= cbm_reset_counter_i; + + cbm_trb_rdo_fsm_i <= WAIT_FOR_RELEASE; + end if; + + when WAIT_FOR_RELEASE => + cbm_rdo_registered_i <= '1'; + if cbm_from_trb_rdo_finished_i = '1' then + cbm_trb_rdo_fsm_i <= WAIT_BEFORE_IDLE; + end if; + + when WAIT_BEFORE_IDLE => + cbm_trb_rdo_fsm_i <= IDLE; + end case; + end process; -- TRBNet slow control trb_regio_addr_i <= to_integer(UNSIGNED(TRB_REGIO_ADDR_IN(3 downto 0))); @@ -210,7 +289,7 @@ begin TRB_REGIO_UNKNOWN_ADDR_OUT <= '0'; TRB_REGIO_DATA_OUT <= (others => '0'); - if trb_crs_cbm_dlm_sensed_i = '1' then + if trb_from_cbm_dlm_sensed_i = '1' then trb_next_epoch_updated_i <= '0'; end if; @@ -227,7 +306,8 @@ begin when 0 => TRB_REGIO_DATA_OUT(31 downto 16) <= trb_dlm_sense_mask_i; TRB_REGIO_DATA_OUT(11 downto 8) <= trb_rdo_fsm_state_i; - TRB_REGIO_DATA_OUT(4) <= trb_crs_cbm_current_epoch_updated_i; + TRB_REGIO_DATA_OUT(5) <= CBM_LINK_ACTIVE_IN; + TRB_REGIO_DATA_OUT(4) <= trb_from_cbm_current_epoch_updated_i; TRB_REGIO_DATA_OUT( 3 downto 0) <= "00" & trb_epoch_update_scheme_i; when 1 => @@ -237,16 +317,16 @@ begin TRB_REGIO_DATA_OUT <= trb_next_epoch_i; when trb_sync_lowest_address_c => - TRB_REGIO_DATA_OUT <= trb_crs_cbm_current_epoch_i; - trb_sync_buffer_i(trb_sync_lowest_address_c+1) <= trb_crs_cbm_timestamp_i; - trb_sync_buffer_i(trb_sync_lowest_address_c+2) <= trb_crs_cbm_timestamp_last_dlm_i; - trb_sync_buffer_i(trb_sync_lowest_address_c+3) <= trb_crs_cbm_timestamp_last_pulse_i; + TRB_REGIO_DATA_OUT <= trb_from_cbm_current_epoch_i; + trb_sync_buffer_i(trb_sync_lowest_address_c+1) <= trb_from_cbm_timestamp_i; + trb_sync_buffer_i(trb_sync_lowest_address_c+2) <= trb_from_cbm_timestamp_last_dlm_i; + trb_sync_buffer_i(trb_sync_lowest_address_c+3) <= trb_from_cbm_timestamp_last_pulse_i; trb_sync_buffer_i(trb_sync_lowest_address_c+4) <= trb_timestamp_i; trb_sync_buffer_i(trb_sync_lowest_address_c+5) <= trb_timestamp_last_dlm_i; trb_sync_buffer_i(trb_sync_lowest_address_c+6) <= trb_timestamp_last_pulse_i; - trb_sync_buffer_i(trb_sync_lowest_address_c+7) <= trb_crs_cbm_dlm_counter_i; - trb_sync_buffer_i(trb_sync_lowest_address_c+8) <= trb_crs_cbm_pulser_counter_i; - trb_sync_buffer_i(trb_sync_lowest_address_c+9) <= STD_LOGIC_VECTOR(trb_reset_counter_i) & STD_LOGIC_VECTOR(trb_crs_cbm_reset_counter_i); + trb_sync_buffer_i(trb_sync_lowest_address_c+7) <= trb_from_cbm_dlm_counter_i; + trb_sync_buffer_i(trb_sync_lowest_address_c+8) <= trb_from_cbm_pulse_counter_i; + trb_sync_buffer_i(trb_sync_lowest_address_c+9) <= STD_LOGIC_VECTOR(trb_reset_counter_i) & STD_LOGIC_VECTOR(trb_from_cbm_reset_counter_i); when trb_sync_lowest_address_c + 1 to trb_sync_lowest_address_c + trb_sync_buffer_i'high => TRB_REGIO_DATA_OUT <= trb_sync_buffer_i(trb_regio_addr_i); @@ -317,7 +397,7 @@ begin wait until rising_edge(CBM_CLK_IN); dlm_v := to_integer(UNSIGNED(CBM_DLM_REC_IN)); - sensed_v := cbm_crs_trb_dlm_sense_mask_i(dlm_v) and CBM_DLM_REC_VALID_IN; + sensed_v := cbm_from_trb_dlm_sense_mask_i(dlm_v) and CBM_DLM_REC_VALID_IN; cbm_dlm_sensed_i <= sensed_v; if CBM_RESET_IN='1' then @@ -338,10 +418,10 @@ begin cbm_current_epoch_i <= (others => '0'); elsif cbm_dlm_sensed_i = '1' then - case cbm_crs_trb_epoch_update_scheme_i is + case cbm_from_trb_epoch_update_scheme_i is when "01" => -- TRB defined - cbm_current_epoch_i <= cbm_crs_trb_next_epoch_i; - cbm_current_epoch_updated_i <= cbm_crs_trb_next_epoch_updated_i; + cbm_current_epoch_i <= cbm_from_trb_next_epoch_i; + cbm_current_epoch_updated_i <= cbm_from_trb_next_epoch_updated_i; when "10" => -- CBM defined cbm_current_epoch_i <= cbm_next_epoch_i; @@ -379,28 +459,28 @@ begin begin wait until rising_edge(CBM_CLK_IN); - cbm_crs_trb_pulser_threshold_i <= trb_pulser_threshold_i; + cbm_from_trb_pulser_threshold_i <= trb_pulser_threshold_i; cbm_pulse_i <= '0'; if CBM_RESET_IN='1' then - cbm_pulser_counter_i <= 0; + cbm_pulse_counter_i <= 0; end if; - if CBM_RESET_IN='1' or cbm_crs_trb_pulser_threshold_i=x"00000000" then - cbm_pulser_i <= 0; + if CBM_RESET_IN='1' or cbm_from_trb_pulser_threshold_i=x"00000000" then + cbm_pulser_period_counter_i <= 0; - elsif cbm_pulser_i = cbm_crs_trb_pulser_threshold_i then - cbm_pulser_i <= 0; - cbm_pulser_counter_i <= cbm_pulser_counter_i + 1; + elsif cbm_pulser_period_counter_i = cbm_from_trb_pulser_threshold_i then + cbm_pulser_period_counter_i <= 0; + cbm_pulse_counter_i <= cbm_pulse_counter_i + 1; cbm_timestamp_last_pulse_i <= cbm_timestamp_i; cbm_pulse_i <= '1'; - elsif cbm_pulser_i > cbm_crs_trb_pulser_threshold_i then - cbm_pulser_i <= 0; + elsif cbm_pulser_period_counter_i > cbm_from_trb_pulser_threshold_i then + cbm_pulser_period_counter_i <= 0; else - cbm_pulser_i <= cbm_pulser_i + 1; + cbm_pulser_period_counter_i <= cbm_pulser_period_counter_i + 1; end if; end process; @@ -416,11 +496,11 @@ begin trb_reset_counter_i <= trb_reset_counter_i + 1; end if; else - if trb_crs_cbm_dlm_sensed_i = '1' then + if trb_from_cbm_dlm_sensed_i = '1' then trb_timestamp_last_dlm_i <= trb_timestamp_i; end if; - if trb_crs_cbm_pulse_i = '1' then + if trb_from_cbm_pulse_i = '1' then trb_timestamp_last_pulse_i <= trb_timestamp_i; end if; @@ -432,31 +512,40 @@ begin -- Clock Domain Crossing CBM -> TRB THE_PULSE_SYNC: pos_edge_strech_sync port map ( IN_CLK_IN => CBM_CLK_IN, OUT_CLK_IN => TRB_CLK_IN, - DATA_IN => cbm_pulse_i, - DATA_OUT => trb_crs_cbm_pulse_i + DATA_IN => cbm_pulse_i, + DATA_OUT => trb_from_cbm_pulse_i ); THE_DLM_SENSE_SYNC: pos_edge_strech_sync port map ( IN_CLK_IN => CBM_CLK_IN, OUT_CLK_IN => TRB_CLK_IN, - DATA_IN => cbm_dlm_sensed_i, - DATA_OUT => trb_crs_cbm_dlm_sensed_i + DATA_IN => cbm_dlm_sensed_i, + DATA_OUT => trb_from_cbm_dlm_sensed_i ); + + TRB_TRIGGER_OUT <= trb_from_cbm_dlm_sensed_i; - trb_crs_cbm_timestamp_i <= cbm_timestamp_i when rising_edge(TRB_CLK_IN); - trb_crs_cbm_timestamp_last_dlm_i <= cbm_timestamp_last_dlm_i when rising_edge(TRB_CLK_IN); - trb_crs_cbm_reset_counter_i <= cbm_reset_counter_i when rising_edge(TRB_CLK_IN); - trb_crs_cbm_dlm_counter_i <= cbm_dlm_counter_i when rising_edge(TRB_CLK_IN); - trb_crs_cbm_pulser_counter_i <= cbm_pulser_counter_i when rising_edge(TRB_CLK_IN); - trb_crs_cbm_timestamp_last_pulse_i <= cbm_timestamp_last_pulse_i when rising_edge(TRB_CLK_IN); + trb_from_cbm_timestamp_i <= cbm_timestamp_i when rising_edge(TRB_CLK_IN); + trb_from_cbm_timestamp_last_dlm_i <= cbm_timestamp_last_dlm_i when rising_edge(TRB_CLK_IN); + trb_from_cbm_reset_counter_i <= cbm_reset_counter_i when rising_edge(TRB_CLK_IN); + trb_from_cbm_dlm_counter_i <= cbm_dlm_counter_i when rising_edge(TRB_CLK_IN); + trb_from_cbm_pulse_counter_i <= cbm_pulse_counter_i when rising_edge(TRB_CLK_IN); + trb_from_cbm_timestamp_last_pulse_i <= cbm_timestamp_last_pulse_i when rising_edge(TRB_CLK_IN); - trb_crs_cbm_current_epoch_i <= cbm_current_epoch_i when rising_edge(TRB_CLK_IN); - trb_crs_cbm_current_epoch_updated_i <= cbm_current_epoch_updated_i when rising_edge(TRB_CLK_IN); + trb_from_cbm_rdo_registered_i <= cbm_rdo_registered_i when rising_edge(TRB_CLK_IN); + + trb_from_cbm_current_epoch_i <= cbm_current_epoch_i when rising_edge(TRB_CLK_IN); + trb_from_cbm_current_epoch_updated_i <= cbm_current_epoch_updated_i when rising_edge(TRB_CLK_IN); -- Clock Domain Crossing TRB -> CBM - cbm_crs_trb_epoch_update_scheme_i <= trb_epoch_update_scheme_i when rising_edge(CBM_CLK_IN); - cbm_crs_trb_next_epoch_i <= trb_next_epoch_i when rising_edge(CBM_CLK_IN); - cbm_crs_trb_next_epoch_updated_i <= trb_next_epoch_updated_i when rising_edge(CBM_CLK_IN); - cbm_crs_trb_dlm_sense_mask_i <= trb_dlm_sense_mask_i when rising_edge(CBM_CLK_IN); + cbm_from_trb_epoch_update_scheme_i <= trb_epoch_update_scheme_i when rising_edge(CBM_CLK_IN); + cbm_from_trb_next_epoch_i <= trb_next_epoch_i when rising_edge(CBM_CLK_IN); + cbm_from_trb_next_epoch_updated_i <= trb_next_epoch_updated_i when rising_edge(CBM_CLK_IN); + cbm_from_trb_dlm_sense_mask_i <= trb_dlm_sense_mask_i when rising_edge(CBM_CLK_IN); + cbm_from_trb_trigger_buf_in <= TRB_TRIGGER_IN when rising_edge(CBM_CLK_IN); + cbm_from_trb_trigger_in <= cbm_from_trb_trigger_buf_in when rising_edge(CBM_CLK_IN); + cbm_from_trb_rdo_valid_no_timing_in <= TRB_RDO_VALID_NO_TIMING_IN when rising_edge(CBM_CLK_IN); + cbm_from_trb_rdo_finished_i <= trb_rdo_finished_i when rising_edge(CBM_CLK_IN); + cbm_from_trb_reset_in <= TRB_RESET_IN when rising_edge(CBM_CLK_IN); end architecture; \ No newline at end of file diff --git a/cbmnet/code/pos_edge_strech_sync.vhd b/cbmnet/code/pos_edge_strech_sync.vhd index b8f1321..2556e9f 100644 --- a/cbmnet/code/pos_edge_strech_sync.vhd +++ b/cbmnet/code/pos_edge_strech_sync.vhd @@ -8,20 +8,34 @@ entity pos_edge_strech_sync is LENGTH : positive := 2 ); port ( - IN_CLK_IN : std_logic; - DATA_IN : std_logic; - OUT_CLK_IN : std_logic; - DATA_OUT : std_logic + IN_CLK_IN : in std_logic; + DATA_IN : in std_logic; + OUT_CLK_IN : in std_logic; + DATA_OUT : out std_logic ); end entity; architecture RTL of pos_edge_strech_sync is - signal in_buffer_i : std_logic_vector(LENGTH - 1 downto 0); + signal in_buffer_i : std_logic_vector(LENGTH - 1 downto 0) := (others => '0'); signal in_buffer_aggr_i : std_logic; - signal out_buffer_i : std_logic; + signal out_buffer_i : std_logic := '0'; begin - in_buffer_i <= in_buffer_i(LENGTH-2 downto 0) & DATA_IN when rising_edge(OUT_CLK_IN); - in_buffer_aggr_i <= OR_ALL(in_buffer_i); + IN_PROC: process is + begin + wait until rising_edge(IN_CLK_IN); + in_buffer_i <= in_buffer_i(LENGTH-2 downto 0) & DATA_IN; + end process; - out_buffer_i <= not out_buffer_i and in_buffer_aggr_i when rising_edge(OUT_CLK_IN); + OUT_PROC: process is + begin + wait until rising_edge(OUT_CLK_IN); + + in_buffer_aggr_i <= OR_ALL(in_buffer_i); + + out_buffer_i <= '0'; + if out_buffer_i = '0' and in_buffer_aggr_i = '1' then + out_buffer_i <= '1'; + end if; + end process; + DATA_OUT <= out_buffer_i; end architecture; \ No newline at end of file diff --git a/cbmnet/trb3_periph_cbmnet.lpf b/cbmnet/trb3_periph_cbmnet.lpf index 785ea82..a4f272d 100644 --- a/cbmnet/trb3_periph_cbmnet.lpf +++ b/cbmnet/trb3_periph_cbmnet.lpf @@ -1,184 +1,3 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; -################################################################# -# Basic Settings -################################################################# -# SYSCONFIG MCCLK_FREQ = 2.5; -FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ; -FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ; -FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ; -FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ; -################################################################# -# Clock I/O -################################################################# -LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; -LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; -LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18" ; -LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10" ; -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ; -LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; -DEFINE PORT GROUP "CLK_group" "CLK*" ; -IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; -################################################################# -# Trigger I/O -################################################################# -#Trigger from fan-out -LOCATE COMP "TRIGGER_LEFT" SITE "V3" ; -LOCATE COMP "TRIGGER_RIGHT" SITE "N24" ; -IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; -IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; -################################################################# -# To central FPGA -################################################################# -LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ; -LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ; -LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ; -LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ; -LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ; -LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ; -LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ; -LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ; -LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ; -LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ; -LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ; -LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ; -DEFINE PORT GROUP "FPGA_group" "FPGA*" ; -IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -LOCATE COMP "TEST_LINE[0]" SITE "A5" ; -LOCATE COMP "TEST_LINE[1]" SITE "A6" ; -LOCATE COMP "TEST_LINE[2]" SITE "G8" ; -LOCATE COMP "TEST_LINE[3]" SITE "F9" ; -LOCATE COMP "TEST_LINE[4]" SITE "D9" ; -LOCATE COMP "TEST_LINE[5]" SITE "D10" ; -LOCATE COMP "TEST_LINE[6]" SITE "F10" ; -LOCATE COMP "TEST_LINE[7]" SITE "E10" ; -LOCATE COMP "TEST_LINE[8]" SITE "A8" ; -LOCATE COMP "TEST_LINE[9]" SITE "B8" ; -LOCATE COMP "TEST_LINE[10]" SITE "G10" ; -LOCATE COMP "TEST_LINE[11]" SITE "G9" ; -LOCATE COMP "TEST_LINE[12]" SITE "C9" ; -LOCATE COMP "TEST_LINE[13]" SITE "C10" ; -LOCATE COMP "TEST_LINE[14]" SITE "H10" ; -LOCATE COMP "TEST_LINE[15]" SITE "H11" ; -DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN SLEWRATE=FAST DRIVE=20 ; -################################################################# -# Connection to AddOn -################################################################# -LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 -LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 -LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 -LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 -LOCATE COMP "SFP_MOD1[1]" SITE "R1" ;#DQLL0_4 #9 -LOCATE COMP "SFP_MOD2[1]" SITE "R2" ;#DQLL0_5 #11 -LOCATE COMP "SFP_RATESEL[1]" SITE "N3" ;#DQSLL0_T #13 -LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 -LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 -LOCATE COMP "SFP_TXFAULT[1]" SITE "P6" ;#DQLL0_7 #19 -LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 -LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 -LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 -LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 -LOCATE COMP "SFP_MOD1[2]" SITE "AB1" ;#DQLL2_2 #29 -LOCATE COMP "SFP_MOD2[2]" SITE "AC1" ;#DQLL2_3 #31 -LOCATE COMP "SFP_RATESEL[2]" SITE "AA1" ;#DQLL2_4 #33 -LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 -LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 -LOCATE COMP "SFP_TXFAULT[2]" SITE "W6" ;#DQLL2_C #39 #should be DQSLL2 -LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 -LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 -LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 -LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 -LOCATE COMP "SFP_MOD1[3]" SITE "AB3" ;#DQLL3_4 #10 -LOCATE COMP "SFP_MOD2[3]" SITE "AB4" ;#DQLL3_5 #12 -LOCATE COMP "SFP_RATESEL[3]" SITE "Y6" ;#DQLL3_T #14 #should be DQSLL3 -LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 -LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 -LOCATE COMP "SFP_TXFAULT[3]" SITE "AA4" ;#DQLL3_7 #20 -LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 -LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 -LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 -LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 -LOCATE COMP "SFP_MOD1[4]" SITE "T1" ;#DQLL1_2 #30 -LOCATE COMP "SFP_MOD2[4]" SITE "U1" ;#DQLL1_3 #32 -LOCATE COMP "SFP_RATESEL[4]" SITE "P4" ;#DQLL1_4 #34 -LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 -LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 -LOCATE COMP "SFP_TXFAULT[4]" SITE "R4" ;#DQSLL1_C #40 -LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 -LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 -LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 -LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 -LOCATE COMP "SFP_MOD1[5]" SITE "AA26" ;#DQLR1_4 #177 -LOCATE COMP "SFP_MOD2[5]" SITE "AB26" ;#DQLR1_5 #179 -LOCATE COMP "SFP_RATESEL[5]" SITE "W21" ;#DQSLR1_T #181 -LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 -LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 -LOCATE COMP "SFP_TXFAULT[5]" SITE "AA23" ;#DQLR1_7 #187 -LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 -LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 -LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 -LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 -LOCATE COMP "SFP_MOD1[6]" SITE "T26" ;#DQLR2_4 #178 -LOCATE COMP "SFP_MOD2[6]" SITE "U26" ;#DQLR2_5 #180 -LOCATE COMP "SFP_RATESEL[6]" SITE "V21" ;#DQSLR2_T #182 -LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 -LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 -LOCATE COMP "SFP_TXFAULT[6]" SITE "V24" ;#DQLR2_7 #188 -DEFINE PORT GROUP "SFP_group" "SFP*" ; -IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -################################################################# -# Additional Lines to AddOn -################################################################# -#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 -#all lines are input only -#line 4/5 go to PLL input -LOCATE COMP "SPARE_LINE_0" SITE "M25" ;#194 -LOCATE COMP "SPARE_LINE_1" SITE "M26" ;#196 -LOCATE COMP "SPARE_LINE_2" SITE "W4" ;#198 -LOCATE COMP "SPARE_LINE_3" SITE "W5" ;#200 -LOCATE COMP "SPARE_LINE_4" SITE "M3" ;#DQUL3_8_OUTOFLANE_FPGA__3 #69 -LOCATE COMP "SPARE_LINE_5" SITE "M2" ;#DQUL3_9_OUTOFLANE_FPGA__3 #71 -################################################################# -# Flash ROM and Reboot -################################################################# -LOCATE COMP "FLASH_CLK" SITE "B12" ; -LOCATE COMP "FLASH_CS" SITE "E11" ; -LOCATE COMP "FLASH_DIN" SITE "E12" ; -LOCATE COMP "FLASH_DOUT" SITE "A12" ; -DEFINE PORT GROUP "FLASH_group" "FLASH*" ; -IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; -LOCATE COMP "PROGRAMN" SITE "B11" ; -IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -################################################################# -# Misc -################################################################# -LOCATE COMP "TEMPSENS" SITE "A13" ; -IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -#coding of FPGA number -LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; -LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; -IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -#terminated differential pair to pads -LOCATE COMP "SUPPL" SITE "C14" ; -IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; -################################################################# -# LED -################################################################# -LOCATE COMP "LED_GREEN" SITE "F12" ; -LOCATE COMP "LED_ORANGE" SITE "G13" ; -LOCATE COMP "LED_RED" SITE "A15" ; -LOCATE COMP "LED_YELLOW" SITE "A16" ; -DEFINE PORT GROUP "LED_group" "LED*" ; -IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; -# BLOCK RESETPATHS ; -# BLOCK ASYNCPATHS ; -# BLOCK RD_DURING_WR_PATHS ; -################################################################# -# Basic Settings -################################################################# SYSCONFIG MCCLK_FREQ=20 ; # FREQUENCY NET "THE_CBM_PHY/CLK_TX_FULL_I" 250 MHz; #FREQUENCY NET "THE_CBM_PHY/RCLK_250_I" 250.000000 MHz ; @@ -200,28 +19,56 @@ REGION "MEDIA_UPLINK" "R102C95D" 13 25 DEVSIZE; LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; LOCATE COMP "THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSB" ; #LOCATE COMP "THE_CBM_PHY/GEN_EASY_SERDES/THE_EASY_SERDES/PCSD_INST" SITE "PCSB" ; -#REGION "CBM_PHY" "R102C49D" 13 25; -#LOCATE UGROUP "THE_CBM_PHY/cbmnet_phy_group" REGION "CBM_PHY"; -#REGION "CBM_PHY_RX_GEAR" "R102C50D" 13 15 DEVSIZE; -#LOCATE UGROUP "THE_CBM_PHY/THE_RX_GEAR/cbmnet_phy_rx_gear" REGION "CBM_PHY_RX_GEAR" ; -#REGION "CBM_PHY_TX_GEAR" "R102C50D" 13 15 DEVSIZE; -#LOCATE UGROUP "THE_CBM_PHY/THE_TX_GEAR/cbmnet_phy_tx_gear" REGION "CBM_PHY_TX_GEAR" ; + +REGION "CBM_PHY" "R102C49D" 13 30; +LOCATE UGROUP "THE_CBM_PHY/cbmnet_phy_group" REGION "CBM_PHY"; + + ################################################################# # Relax some of the timing constraints ################################################################# -FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ; -FREQUENCY NET "clk_200_i" 200.000000 MHz ; -FREQUENCY NET "clk_100_i_c" 100.000000 MHz ; -FREQUENCY NET "CLK_RX_FULL_OUT" 250.000000 MHz ; -FREQUENCY NET "THE_CBM_PHY/clk_tx_full_i" 250.000000 MHz ; -FREQUENCY NET "THE_MEDIA_UPLINK/un1_THE_MEDIA_UPLINK_2_c" 100.000000 MHz ; -FREQUENCY NET "THE_CBM_PHY/THE_RX_GEAR/clk_125_i_i" 125.000000 MHz ; -FREQUENCY NET "rclk_125_i" 125.000000 MHz ; +FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ; +FREQUENCY PORT "CLK_GPLL_LEFT" 125.0 MHz; +FREQUENCY NET "THE_MAIN_PLL/clk_200_i" 200.0 MHz; +FREQUENCY NET "THE_MAIN_PLL/clk_100_i_c" 100.0 MHz; +FREQUENCY NET "THE_CBM_PHY/THE_RX_GEAR/rclk_125_i_c" 125.0 MHz; +FREQUENCY NET "THE_CBM_PHY/CLK_RX_FULL_OUT" 250.0 MHz; +FREQUENCY NET "THE_CBM_PHY/clk_tx_full_i" 250.0 MHz; +FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/un1_THE_MEDIA_UPLINK_1_c" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/refclkdiv2_rx_ch1" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/refclkdiv2_tx_ch" 100.0 MHz; +FREQUENCY PORT "TRIGGER_LEFT" 125.0 MHz; DEFINE BUS "rx_data" NET "THE_CBM_PHY/rx_data_from_serdes_i[0]" NET "THE_CBM_PHY/rx_data_from_serdes_i[1]" NET "THE_CBM_PHY/rx_data_from_serdes_i[2]" NET "THE_CBM_PHY/rx_data_from_serdes_i[3]" NET "THE_CBM_PHY/rx_data_from_serdes_i[4]" NET "THE_CBM_PHY/rx_data_from_serdes_i[5]" NET "THE_CBM_PHY/rx_data_from_serdes_i[6]" NET "THE_CBM_PHY/rx_data_from_serdes_i[7]" NET "THE_CBM_PHY/rx_data_from_serdes_i[8]"; DEFINE BUS "tx_data" NET "THE_CBM_PHY/tx_data_to_serdes_i[0]" NET "THE_CBM_PHY/tx_data_to_serdes_i[1]" NET "THE_CBM_PHY/tx_data_to_serdes_i[2]" NET "THE_CBM_PHY/tx_data_to_serdes_i[3]" NET "THE_CBM_PHY/tx_data_to_serdes_i[4]" NET "THE_CBM_PHY/tx_data_to_serdes_i[5]" NET "THE_CBM_PHY/tx_data_to_serdes_i[6]" NET "THE_CBM_PHY/tx_data_to_serdes_i[7]" NET "THE_CBM_PHY/tx_data_to_serdes_i[8]"; -PRIORITIZE BUS "rx_data" 51; -PRIORITIZE BUS "tx_data" 50; \ No newline at end of file +PRIORITIZE BUS "rx_data" 100; +PRIORITIZE BUS "tx_data" 100; + +#MULTICYCLE TO CELL "THE_CBM_PHY/THE_TX_GEAR/data_in_buf250_0_i*" 2 X; +#MULTICYCLE TO CELL "THE_CBM_PHY/THE_RX_GEAR/delay_clock_buf_i" 2 X; +#MULTICYCLE TO CELL "THE_CBM_PHY/THE_RX_GEAR/data_out_buf125_i*" 2 X; + + +#PROHIBIT PRIMARY NET "THE_CBM_PHY/un1_THE_CBM_PHY" ; +#PROHIBIT SECONDARY NET "THE_CBM_PHY/un1_THE_CBM_PHY" ; +#PROHIBIT PRIMARY NET "THE_CBM_PHY/clk_tx_full_i" ; +#PROHIBIT SECONDARY NET "THE_CBM_PHY/clk_tx_full_i" ; + +UGROUP "CBM_PHY_UGROUP" BBOX 13 26 + BLKNAME THE_CBM_PHY + BLKNAME THE_CBM_PHY/THE_RX_GEAR + BLKNAME THE_CBM_PHY/THE_TX_GEAR; +LOCATE UGROUP "CBM_PHY_UGROUP" SITE "R105C110D" ; + +UGROUP "CBMNET_group" BBOX 36 50 +# BLKNAME THE_CBMNET_READOUT + BLKNAME THE_CBM_ENDPOINT + BLKNAME THE_DLM_REFLECT + BLKNAME THE_SYNC_MODULE; +LOCATE UGROUP "CBMNET_group" SITE "R80C85D" ; + + +BLOCK PATH TO CELL "phy_debug_i_buf*" ; \ No newline at end of file diff --git a/cbmnet/trb3_periph_cbmnet.vhd b/cbmnet/trb3_periph_cbmnet.vhd index 06739bd..f684680 100755 --- a/cbmnet/trb3_periph_cbmnet.vhd +++ b/cbmnet/trb3_periph_cbmnet.vhd @@ -136,6 +136,8 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal rclk_125_i : std_logic; -- recovered clock + signal rclk_250_i : std_logic; -- recovered clock + signal rreset_i : std_logic; -- reset for recovered clock ~ 1us after clock becomes stable @@ -228,6 +230,19 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal debug_addr : std_logic_vector(5 downto 0); signal debug_data_out : std_logic_vector(31 downto 0); signal debug_ack : std_logic; + + signal sync_regio_read_en : std_logic; + signal sync_regio_write_en : std_logic; + signal sync_regio_status_data : std_logic_vector(31 downto 0); + signal sync_regio_addr : std_logic_vector(3 downto 0); + signal sync_regio_config_data : std_logic_vector(31 downto 0); + signal sync_regio_read_ack : std_logic; + signal sync_regio_write_ack : std_logic; + signal sync_regio_unknown : std_logic; + + signal trb_trigger : std_logic; + signal sync_dlm_sense : std_logic; + signal sync_pulser : std_logic; signal spi_bram_addr : std_logic_vector(7 downto 0); @@ -435,10 +450,48 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal event_gap_cnt_i : unsigned(31 downto 0); - type TRB_FSM_T is (IDLE, START_READOUT, START_READOUT_WAIT, FEE_BUSY, SEND_EINF_H, SEND_EINF_L, SEND_LENGTH, SEND_SOURCE, SEND_SOURCE_WAIT, SEND_PAYLOAD_H, SEND_PAYLOAD_L, SEND_PAYLOAD_RT_H, SEND_PAYLOAD_RT_L, COMPL_WAIT, COMPL_NOT_BUSY_WAIT, EVT_WAIT); + type TRB_FSM_T is (IDLE, START_READOUT, START_READOUT_WAIT, FEE_BUSY, SEND_EINF_H, SEND_EINF_L, SEND_LENGTH, SEND_SOURCE, SEND_SOURCE_WAIT, + SEND_PAYLOAD_SSEHDR_H, SEND_PAYLOAD_SSEHDR_L, + SEND_PAYLOAD_RT_H, SEND_PAYLOAD_RT_L, + SEND_PAYLOAD_H, SEND_PAYLOAD_L, + COMPL_WAIT, COMPL_NOT_BUSY_WAIT, EVT_WAIT); signal trb_fsm_i : TRB_FSM_T; + + signal rdo_send_length_min_i : unsigned(31 downto 0); + signal rdo_send_length_max_i : unsigned(31 downto 0); + signal rdo_send_length_inc_i : unsigned(31 downto 0); + signal rdo_send_length_cur_i : unsigned(31 downto 0); + + type RDO_FSM_STATES_T is (UPDATE_LENGTH, WAIT_FOR_TRIGGER, SEND_RT_100, SEND_RT_125, SEND_TESTPATTERN, COMPLETE); + signal rdo_fsm_i : RDO_FSM_STATES_T; + + signal do_reboot_i : std_logic; + + signal cbm_do_reboot_i : std_logic; + signal trb_crs_cbm_do_reboot_i : std_logic; begin +-- RDO_PROC: process is +-- begin +-- wait until rising_edge(clk_100_i); +-- +-- if reset_i='1' then +-- rdo_fsm_i <= WAIT_FOR_TRIGGER; +-- rdo_send_length_cur_i <= rdo_send_length_min_i; +-- +-- else +-- case(rdo_fsm_i) is +-- case UPDATE_LENGTH => +-- case WAIT_FOR_TRIGGER => +-- case SEND_RT_100 => +-- case SEND_RT_125 => +-- case SEND_TESTPATTERN => +-- case COMPLETE => +-- end case; +-- end if; +-- end process; + + clk_125_i <= CLK_GPLL_LEFT; assert(INCLUDE_TRBNET = c_YES); @@ -463,7 +516,7 @@ begin PHY_RXDATA_K_OUT => cbm_data_from_link(17 downto 16), CLK_RX_HALF_OUT => rclk_125_i, - CLK_RX_FULL_OUT => open, + CLK_RX_FULL_OUT => rclk_250_i, CLK_RX_RESET_OUT => rreset_i, LINK_ACTIVE_OUT => open, @@ -489,25 +542,62 @@ begin DEBUG_OUT => phy_debug_i ); --- TEST_LINE(7 downto 0) <= cbm_data2send_stop & cbm_data2send_start & cbm_data2send_end & cbm_dlm_rec_va & cbm_dlm_rec_type; --- TEST_LINE(15 downto 8) <= phy_stat_debug(7 downto 0); - - PROC_TESTLINE: process is - variable pattern_v : std_logic_vector(15 downto 0) := x"0001"; - begin - wait until rising_edge(rclk_125_i); + TEST_LINE(2 downto 0) <= sync_pulser & sync_dlm_sense & trb_trigger; + + + THE_SYNC_MODULE: cbmnet_sync_module port map ( + -- TRB + TRB_CLK_IN => clk_100_i, -- in std_logic; + TRB_RESET_IN => reset_i, -- in std_logic; + TRB_TRIGGER_OUT => trb_trigger, -- out std_logic; + + --data output for read-out + TRB_TRIGGER_IN => timing_trg_received_i, -- in std_logic; - pattern_v := pattern_v(14 downto 0) & pattern_v(15); + TRB_RDO_VALID_DATA_TRG_IN => trg_data_valid_i, + TRB_RDO_VALID_NO_TIMING_IN => trg_notiming_valid_i, - if send_enabled_i = '0' then - TEST_LINE <= pattern_v; - else - pattern_v := x"0001"; - TEST_LINE(15 downto 11) <= cbm_data2send_stop & cbm_data2send_start & cbm_data2send_end & cbm_data2send(15 downto 14); - TEST_LINE(10 downto 0) <= cbm_data2send(10 downto 0); - end if; - end process; - + TRB_RDO_DATA_OUT => fee_data_i, -- out std_logic_vector(31 downto 0); + TRB_RDO_WRITE_OUT => fee_data_write_i, -- out std_logic; + TRB_RDO_STATUSBIT_OUT => fee_trg_statusbits_i, -- out std_logic_vector(31 downto 0); + TRB_RDO_FINISHED_OUT => fee_data_finished_i, -- out std_logic; + + -- reg io + TRB_REGIO_ADDR_IN(15 downto 4) => x"000", + TRB_REGIO_ADDR_IN(3 downto 0) => sync_regio_addr, -- in std_logic_vector(15 downto 0); + TRB_REGIO_DATA_IN => sync_regio_config_data, -- in std_logic_vector(31 downto 0); + TRB_REGIO_READ_ENABLE_IN => sync_regio_read_en, -- in std_logic; + TRB_REGIO_WRITE_ENABLE_IN => sync_regio_write_en, -- in std_logic; + TRB_REGIO_DATA_OUT => sync_regio_status_data, -- out std_logic_vector(31 downto 0); + TRB_REGIO_DATAREADY_OUT => sync_regio_read_ack, -- out std_logic; + TRB_REGIO_WRITE_ACK_OUT => sync_regio_write_ack, -- out std_logic; + TRB_REGIO_UNKNOWN_ADDR_OUT => sync_regio_unknown, -- out std_logic; + + -- CBMNET + CBM_CLK_IN => rclk_125_i, -- in std_logic; + CBM_CLK_250_IN => rclk_250_i, + CBM_LINK_ACTIVE_IN => cbm_link_active, + CBM_RESET_IN => rreset_i, -- in std_logic; + CBM_PHY_BARREL_SHIFTER_POS_IN => x"0", -- in std_logic_vector(3 downto 0); + + CBM_TIMING_TRIGGER_OUT => open, + + -- DLM port + CBM_DLM_REC_IN => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0); + CBM_DLM_REC_VALID_IN => cbm_dlm_rec_va, -- in std_logic; + CBM_DLM_SENSE_OUT => sync_dlm_sense, -- out std_logic; + CBM_PULSER_OUT => sync_pulser, -- out std_logic; -- connect to TDC + + -- Ctrl port + CBM_CTRL_DATA_IN => cbm_ctrl_rec, -- in std_logic_vector(15 downto 0); + CBM_CTRL_DATA_START_IN => cbm_ctrl_rec_start, -- in std_logic; + CBM_CTRL_DATA_END_IN => cbm_ctrl_rec_end, -- in std_logic; + CBM_CTRL_DATA_STOP_OUT => cbm_ctrl_rec_stop, -- out std_logic; + + DEBUG_OUT => open -- out std_logic_vector(31 downto 0) + ); + + fee_trg_release_i <= fee_data_finished_i; SFP_RATESEL <= (others => '0'); @@ -776,8 +866,21 @@ begin trb_fsm_i <= SEND_SOURCE_WAIT; when SEND_SOURCE_WAIT => - trb_fsm_i <= SEND_PAYLOAD_H; + trb_fsm_i <= SEND_PAYLOAD_SSEHDR_H; + when SEND_PAYLOAD_SSEHDR_H => + HUB_FEE_DATA <= std_logic_vector(send_counter_i - 1); + HUB_FEE_DATAREADY <= '1'; + trb_fsm_i <= SEND_PAYLOAD_SSEHDR_L; + + when SEND_PAYLOAD_SSEHDR_L => + HUB_FEE_DATA <= x"4444"; + HUB_FEE_DATAREADY <= '1'; + trb_fsm_i <= SEND_PAYLOAD_H; + send_counter_i <= send_counter_i - 1; + + trb_fsm_i <= SEND_PAYLOAD_RT_H; + when SEND_PAYLOAD_RT_H => HUB_FEE_DATA <= std_logic_vector(send_real_time_buf_i(31 downto 16)); HUB_FEE_DATAREADY <= '1'; @@ -875,74 +978,6 @@ begin cbm_data2send_start <= cbm_data2send_start1; -- when tp_mux_i = '0' else cbm_data2send_start2; cbm_data2send_end <= cbm_data2send_end1; -- when tp_mux_i = '0' else cbm_data2send_end2; --- proc_data_send: process begin --- wait until rising_edge(rclk_125_i); --- --- cbm_data2send2 <= (others => '0'); --- cbm_data2send_start2 <= "0"; --- cbm_data2send_end2 <= "0"; --- --- if reset_i = '1' or send_enabled_i = '0' then --- send_fsm_i <= start; --- send_num_pack_counter_i <= (others => '0'); --- --- else --- case(send_fsm_i) is --- when start => --- if cbm_link_active='1' and cbm_data2send_stop = "0" then --- send_fsm_i <= send_header; --- send_num_pack_counter_i <= send_num_pack_counter_i + 1; --- send_length_i2(4 downto 0) <= unsigned("0" & send_num_pack_counter_i(3 downto 0)) + 1; --- --- if send_burst_counter_i = to_unsigned(0, send_burst_counter_i'length) then --- send_burst_counter_i <= send_burst_threshold_i; --- else --- send_burst_counter_i <= send_burst_counter_i - 1; --- end if; --- end if; --- --- when send_header => --- cbm_data2send2 <= x"f123"; --- cbm_data2send_start2 <= "1"; --- send_fsm_i <= send_pack_num; --- --- when send_pack_num => --- cbm_data2send2 <= send_num_pack_counter_i; --- send_fsm_i <= send_length; --- --- when send_length => --- cbm_data2send2(send_length_i2'range) <= send_length_i2; --- send_fsm_i <= send_data; --- --- when send_data => --- send_length_i2 <= send_length_i2 - 1; --- cbm_data2send2(15 downto 8) <= "0" & std_logic_vector(send_length_i2(2 downto 0)) & std_logic_vector(send_length_i2(3 downto 0)); --- cbm_data2send2(send_length_i2'high + 0 downto 0) <= send_length_i2; --- --- if send_length_i2 = to_unsigned(1, send_length_i2'length) then --- send_fsm_i <= send_footer; --- end if; --- --- when send_footer => --- cbm_data2send2 <= x"f321"; --- cbm_data2send_end2 <= "1"; --- --- send_wait_counter_i2 <= (others => '0'); --- send_fsm_i <= after_send_wait; --- --- when after_send_wait => --- send_wait_counter_i2 <= std_logic_vector( unsigned(send_wait_counter_i2) + 1 ); --- if send_wait_counter_i2(4 downto 0) >= send_wait_threshold_i or send_burst_counter_i /= to_unsigned(0, send_burst_counter_i'length) then --- send_fsm_i <= start; --- end if; --- --- when others => --- send_fsm_i <= start; --- --- end case; --- end if; --- end process; - PROC_DLM_COUNTER: process is variable dlm_type_v : integer range 15 downto 0; begin @@ -1047,7 +1082,7 @@ begin --cbm_debug_overrides_i <= debug_data_in(21 downto 20); when 16#30# => - if UNSIGNED(debug_data_in(15 downto 0)) /= 0 then + if UNSIGNED(debug_data_in(15 downto 0)) > 1 then send_length_min_i <= UNSIGNED(debug_data_in(15 downto 0)); end if; when 16#31# => @@ -1064,7 +1099,7 @@ begin if reset_i='1' then send_length_step_i <= TO_UNSIGNED( 1, 16); - send_length_min_i <= TO_UNSIGNED( 1, 16); + send_length_min_i <= TO_UNSIGNED( 2, 16); send_length_max_i <= TO_UNSIGNED(200, 16); end if; end process; @@ -1268,14 +1303,15 @@ begin DEBUG_LVL1_HANDLER_OUT => open ); + timing_trg_received_i <= TRIGGER_LEFT; --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"a000", 3=>x"a800", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 6, 3=>6, others => 0) + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"a000", 3=>x"a800", 4=>x"a900", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 6, 3=>6, 4=>4, others => 0) ) port map( CLK => clk_100_i, @@ -1342,7 +1378,21 @@ begin BUS_WRITE_ACK_IN(3) => cbm_rdo_regio_write_ack_i, BUS_NO_MORE_DATA_IN(3) => '0', BUS_UNKNOWN_ADDR_IN(3) => cbm_rdo_regio_unknown_addr_i, - + + --CBMNet (read-out) + BUS_READ_ENABLE_OUT(4) => sync_regio_read_en, + BUS_WRITE_ENABLE_OUT(4) => sync_regio_write_en, + BUS_DATA_OUT(4*32+31 downto 4*32) => sync_regio_config_data, + BUS_ADDR_OUT(4*16+3 downto 4*16) => sync_regio_addr, + BUS_ADDR_OUT(4*16+15 downto 4*16+4) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(4*32+31 downto 4*32) => sync_regio_status_data, + BUS_DATAREADY_IN(4) => sync_regio_read_ack, + BUS_WRITE_ACK_IN(4) => sync_regio_write_ack, + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => sync_regio_unknown, + + STAT_DEBUG => open ); diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index a5a7dc9..53a3c37 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -547,6 +547,7 @@ architecture trb3_central_arch of trb3_central is -- cbmnet signal cbm_clk_i : std_logic; + signal cbm_clk250_i : std_logic; signal cbm_reset_i : std_logic; signal cbm_reset_n_i : std_logic; @@ -632,11 +633,10 @@ architecture trb3_central_arch of trb3_central is signal cbm_sync_dlm_sensed_i : std_logic; signal cbm_sync_pulser_i : std_logic; + signal cbm_sync_timing_trigger_i : std_logic; signal cbm_dlm_trigger_i : std_logic; - --signal reset_fifo_i : std_logic_vector(3 downto 0) := (others => '0'); - signal cbm_phy_debug : std_logic_vector(511 downto 0); signal do_reboot_i : std_logic; @@ -853,7 +853,7 @@ begin PHY_RXDATA_K_OUT => cbm_data_from_link_i(17 downto 16), CLK_RX_HALF_OUT => cbm_clk_i, - CLK_RX_FULL_OUT => open, + CLK_RX_FULL_OUT => cbm_clk250_i, CLK_RX_RESET_OUT => cbm_reset_i, LINK_ACTIVE_OUT => open, @@ -1085,7 +1085,11 @@ begin --data output for read-out TRB_TRIGGER_IN => cts_trigger_out, -- in std_logic; -- TODO: we may want to feed the reference time via an external input - TRB_RDO_VALID_IN => cts_rdo_trg_data_valid, + + TRB_RDO_VALID_DATA_TRG_IN => cts_rdo_trg_data_valid, + TRB_RDO_VALID_NO_TIMING_IN => cts_rdo_valid_notiming_trg, + + TRB_RDO_DATA_OUT => cts_rdo_additional_data(32*cts_rdo_additional_ports-1 downto 32*cts_rdo_additional_ports-32), -- out std_logic_vector(31 downto 0); TRB_RDO_WRITE_OUT => cts_rdo_additional_write(cts_rdo_additional_ports-1), -- out std_logic; -- TRB_RDO_STATUSBIT_OUT => cts_rdo_add(32*cts_rdo_additional_ports-1 downto 32*cts_rdo_additional_ports-32), -- out std_logic_vector(31 downto 0); @@ -1104,9 +1108,13 @@ begin -- CBMNET CBM_CLK_IN => cbm_clk_i, -- in std_logic; + CBM_CLK_250_IN => cbm_clk250_i, CBM_RESET_IN => cbm_reset_i, -- in std_logic; + CBM_LINK_ACTIVE_IN => cbm_link_active_i, CBM_PHY_BARREL_SHIFTER_POS_IN => x"0", -- in std_logic_vector(3 downto 0); + CBM_TIMING_TRIGGER_OUT => cbm_sync_timing_trigger_i, + -- DLM port CBM_DLM_REC_IN => cbm_dlm_rec_type_i, -- in std_logic_vector(3 downto 0); CBM_DLM_REC_VALID_IN => cbm_dlm_rec_va_i, -- in std_logic; diff --git a/cts/trb3_central_syn.fdc b/cts/trb3_central_syn.fdc index 3fac7d4..8452362 100644 --- a/cts/trb3_central_syn.fdc +++ b/cts/trb3_central_syn.fdc @@ -38,7 +38,6 @@ create_clock {p:CLK_GPLL_RIGHT} -period {8} ###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) -set_false_path -disable ###==== END "Delay Paths" ###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) -- 2.43.0