From d93d79363ca37af77e30f4cb6aed17ad6d677ad5 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 22 Dec 2017 17:14:20 +0100 Subject: [PATCH] add "first idle after data" signal in tx_control --- media_interfaces/sync/tx_control.vhd | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index 220d45d..c0809a6 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -20,6 +20,7 @@ entity tx_control is TX_DATA_OUT : out std_logic_vector( 7 downto 0); TX_K_OUT : out std_logic; + TX_CD_OUT : out std_logic; REQUEST_RETRANSMIT_IN : in std_logic := '0'; REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); @@ -101,7 +102,7 @@ architecture arch of tx_control is signal crc_q : std_logic_vector(7 downto 0); signal crc_en : std_logic; signal crc_data : std_logic_vector(7 downto 0); - + signal first_idle : std_logic; begin ---------------------------------------------------------------------- @@ -237,12 +238,15 @@ begin if rising_edge(CLK_200) then -- ram_read <= '0'; TX_K_OUT <= '0'; + TX_CD_OUT <= '0'; debug_sending_dlm <= '0'; + first_idle <= '1'; case current_state is when SEND_IDLE_L => TX_DATA_OUT <= K_IDLE; TX_K_OUT <= '1'; current_state <= SEND_IDLE_H; + first_idle <= first_idle; when SEND_IDLE_H => if rx_allow_qtx = '1' then @@ -250,6 +254,8 @@ begin else TX_DATA_OUT <= D_IDLE0; end if; + TX_CD_OUT <= first_idle; + first_idle <= '0'; when SEND_DATA_L => TX_DATA_OUT <= ram_dout(7 downto 0); -- 2.43.0