From da4282918183c3effd922ec8d965f879b0e31ad7 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Wed, 13 Jan 2021 16:08:44 +0100 Subject: [PATCH] Trb5sc with CRI connectivity for e.g. the CBM RICH detector. Later used for temperature/magneitc field monitoring access and additional TDC input into data stream (e.g. Laser trigger) --- cbmrich/compile.pl | 1 + cbmrich/config.vhd | 172 ++++ cbmrich/config_compile_frankfurt.pl | 25 + cbmrich/config_compile_giessen.pl | 26 + cbmrich/core/FIFO_36x128/FIFO_36x128.ipx | 9 + cbmrich/core/FIFO_36x128/FIFO_36x128.lpc | 50 + cbmrich/core/FIFO_36x128/FIFO_36x128.vhd | 790 +++++++++++++++ cbmrich/core/FIFO_36x64/FIFO_36x64.ipx | 9 + cbmrich/core/FIFO_36x64/FIFO_36x64.lpc | 50 + cbmrich/core/FIFO_36x64/FIFO_36x64.vhd | 770 +++++++++++++++ .../RAM_pseudo_DP_wReg_36x1k.ipx | 10 + .../RAM_pseudo_DP_wReg_36x1k.lpc | 52 + .../RAM_pseudo_DP_wReg_36x1k.vhd | 260 +++++ cbmrich/nodelist_frankfurt.txt | 13 + cbmrich/par.p2t | 69 ++ cbmrich/tdc_release | 1 + cbmrich/trb5sc_cbmrich.lpf | 43 + cbmrich/trb5sc_cbmrich.prj | 301 ++++++ cbmrich/trb5sc_cbmrich.vhd | 902 ++++++++++++++++++ 19 files changed, 3553 insertions(+) create mode 120000 cbmrich/compile.pl create mode 100644 cbmrich/config.vhd create mode 100644 cbmrich/config_compile_frankfurt.pl create mode 100644 cbmrich/config_compile_giessen.pl create mode 100644 cbmrich/core/FIFO_36x128/FIFO_36x128.ipx create mode 100644 cbmrich/core/FIFO_36x128/FIFO_36x128.lpc create mode 100644 cbmrich/core/FIFO_36x128/FIFO_36x128.vhd create mode 100644 cbmrich/core/FIFO_36x64/FIFO_36x64.ipx create mode 100644 cbmrich/core/FIFO_36x64/FIFO_36x64.lpc create mode 100644 cbmrich/core/FIFO_36x64/FIFO_36x64.vhd create mode 100644 cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.ipx create mode 100644 cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.lpc create mode 100644 cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.vhd create mode 100644 cbmrich/nodelist_frankfurt.txt create mode 100644 cbmrich/par.p2t create mode 120000 cbmrich/tdc_release create mode 100644 cbmrich/trb5sc_cbmrich.lpf create mode 100644 cbmrich/trb5sc_cbmrich.prj create mode 100644 cbmrich/trb5sc_cbmrich.vhd diff --git a/cbmrich/compile.pl b/cbmrich/compile.pl new file mode 120000 index 0000000..933ff60 --- /dev/null +++ b/cbmrich/compile.pl @@ -0,0 +1 @@ +../../trb3/scripts/compile.pl \ No newline at end of file diff --git a/cbmrich/config.vhd b/cbmrich/config.vhd new file mode 100644 index 0000000..e50a74b --- /dev/null +++ b/cbmrich/config.vhd @@ -0,0 +1,172 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F570"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"81"; + + constant INCLUDE_UART : integer := c_YES; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_CALIBRATION : integer := c_YES; + constant INCLUDE_TDC : integer := c_YES; -- IMPORTANT: TDC part into entity has to be commented in/out by hand + -- (no generic possible due to constraints naming) + + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_YES; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 0; + constant TRIG_GEN_OUTPUT_NUM : integer := 0; + constant MONITOR_INPUT_NUM : integer := 32; + + constant INCLUDE_GBE : integer := c_NO; + + constant GEN_BUSY_OUTPUT : integer := c_NO; + + constant TRIGGER_COIN_COUNT : integer := 1; + constant TRIGGER_PULSER_COUNT : integer := 2; + constant TRIGGER_RAND_PULSER : integer := 1; + constant TRIGGER_ADDON_COUNT : integer := 2; + constant PERIPH_TRIGGER_COUNT : integer := 0; + constant ADDON_LINE_COUNT : integer := 2;--44; + constant CTS_OUTPUT_MULTIPLEXERS : integer := 1; + + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; + + constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + --constant ETM_ID : std_logic_vector(7 downto 0); + + constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM; --for TDC + + constant FPGA_SIZE : string := "85KUM"; + + +------------------------------------------------------------------------------ +-- Hub config +----------------------------------------------------------------------------- + + constant INTERFACE_NUM : integer := 1; + constant MII_IS_UPLINK : hub_mii_config_t := (0, 0,1,0, 0,0,0,0, 0,0,0,0 ,0,0,0,0, 0); + constant MII_IS_DOWNLINK : hub_mii_config_t := (1, 1,0,0, 0,0,0,0, 0,0,0,0 ,0,0,0,0, 0); + constant MII_IS_UPLINK_ONLY : hub_mii_config_t := (0, 0,1,0, 0,0,0,0, 0,0,0,0 ,0,0,0,0, 0); + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/cbmrich/config_compile_frankfurt.pl b/cbmrich/config_compile_frankfurt.pl new file mode 100644 index 0000000..a681cf6 --- /dev/null +++ b/cbmrich/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_template", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_tdc', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/cbmrich/config_compile_giessen.pl b/cbmrich/config_compile_giessen.pl new file mode 100644 index 0000000..903b491 --- /dev/null +++ b/cbmrich/config_compile_giessen.pl @@ -0,0 +1,26 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_cbmrich", +lm_license_file_for_synplify => "7788\@fb07pc-u102325", +lm_license_file_for_par => "7788\@fb07pc-u102325", +lattice_path => '/usr/local/diamond/3.11_x64/', +synplify_path => '/usr/local/diamond/3.11_x64/synpbase', +synplify_command => "synpwrap -fg -options", +#synplify_command => "ssh adrian\@jspc37.x-matter.uni-frankfurt.de \"cd /local/adrian/git/dirich/combiner_cts/; LM_LICENSE_FILE=27020\@jspc29 /d/jspc29/lattice/synplify/O-2018.09-SP1/bin/synplify_premier -batch combiner.prj\"", + +nodelist_file => '../nodes_lxhadeb07.txt', +par_options => '../par.p2t', + +#Include only necessary lpf files +pinout_file => 'trb5sc_tdc', #name of pin-out file, if not equal TOPNAME +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/cbmrich/core/FIFO_36x128/FIFO_36x128.ipx b/cbmrich/core/FIFO_36x128/FIFO_36x128.ipx new file mode 100644 index 0000000..fe115bb --- /dev/null +++ b/cbmrich/core/FIFO_36x128/FIFO_36x128.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/cbmrich/core/FIFO_36x128/FIFO_36x128.lpc b/cbmrich/core/FIFO_36x128/FIFO_36x128.lpc new file mode 100644 index 0000000..9743f60 --- /dev/null +++ b/cbmrich/core/FIFO_36x128/FIFO_36x128.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=FIFO_36x128 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/13/2021 +Time=11:55:20 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=128 +Width=36 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Dual Threshold +PeAssert=2 +PeDeassert=4 +FullFlg=1 +PfMode=Static - Dual Threshold +PfAssert=126 +PfDeassert=124 +Reset=Async +Reset1=Sync +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n FIFO_36x128 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 128 -width 36 -no_enable -pe 2 -pe2 4 -pf 126 -pf2 124 -reset_rel SYNC diff --git a/cbmrich/core/FIFO_36x128/FIFO_36x128.vhd b/cbmrich/core/FIFO_36x128/FIFO_36x128.vhd new file mode 100644 index 0000000..7a4085c --- /dev/null +++ b/cbmrich/core/FIFO_36x128/FIFO_36x128.vhd @@ -0,0 +1,790 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- Module Version: 5.1 +--/usr/local/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 128 -width 36 -no_enable -pe 2 -pe2 4 -pf 126 -pf2 124 -reset_rel SYNC + +-- Wed Jan 13 11:55:20 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity FIFO_36x128 is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end FIFO_36x128; + +architecture Structure of FIFO_36x128 is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ae: std_logic; + signal ae_d: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co3: std_logic; + signal co2: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal co1_2: std_logic; + signal co2_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co3_1: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co3_2: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal cmp_ci_2: std_logic; + signal co0_5: std_logic; + signal co1_5: std_logic; + signal co2_5: std_logic; + signal ae_set_d: std_logic; + signal ae_set_d_c: std_logic; + signal cmp_ci_3: std_logic; + signal co0_6: std_logic; + signal co1_6: std_logic; + signal co2_6: std_logic; + signal ae_clr_d: std_logic; + signal ae_clr_d_c: std_logic; + signal cmp_ci_4: std_logic; + signal co0_7: std_logic; + signal co1_7: std_logic; + signal co2_7: std_logic; + signal af_set_d: std_logic; + signal af_set_d_c: std_logic; + signal cmp_ci_5: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_8: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_8: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_8: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal af_clr_d: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_clr_d_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x128.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_3: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_2: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>ae, AD2=>ae_set_d, AD1=>ae_clr_d, AD0=>scuba_vlo, + DO0=>ae_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set_d, AD1=>af_clr_d, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), + DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), + DI29=>Data(29), DI28=>Data(28), DI27=>Data(27), + DI26=>Data(26), DI25=>Data(25), DI24=>Data(24), + DI23=>Data(23), DI22=>Data(22), DI21=>Data(21), + DI20=>Data(20), DI19=>Data(19), DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>scuba_vlo, ADW7=>scuba_vlo, ADW6=>wcount_6, + ADW5=>wcount_5, ADW4=>wcount_4, ADW3=>wcount_3, + ADW2=>wcount_2, ADW1=>wcount_1, ADW0=>wcount_0, + BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi, + BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW2=>scuba_vlo, + CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>scuba_vlo, + ADR12=>scuba_vlo, ADR11=>rcount_6, ADR10=>rcount_5, + ADR9=>rcount_4, ADR8=>rcount_3, ADR7=>rcount_2, + ADR6=>rcount_1, ADR5=>rcount_0, ADR4=>scuba_vlo, + ADR3=>scuba_vlo, ADR2=>scuba_vlo, ADR1=>scuba_vlo, + ADR0=>scuba_vlo, CER=>rden_i, OCER=>rden_i, CLKR=>Clock, + CSR2=>scuba_vlo, CSR1=>scuba_vlo, CSR0=>scuba_vlo, + RST=>Reset, DO35=>Q(17), DO34=>Q(16), DO33=>Q(15), + DO32=>Q(14), DO31=>Q(13), DO30=>Q(12), DO29=>Q(11), + DO28=>Q(10), DO27=>Q(9), DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), + DO23=>Q(5), DO22=>Q(4), DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), + DO18=>Q(0), DO17=>Q(35), DO16=>Q(34), DO15=>Q(33), + DO14=>Q(32), DO13=>Q(31), DO12=>Q(30), DO11=>Q(29), + DO10=>Q(28), DO9=>Q(27), DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), + DO5=>Q(23), DO4=>Q(22), DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), + DO0=>Q(18)); + + FF_27: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_26: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_25: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_24: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_23: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_22: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_21: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_20: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_19: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_18: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_17: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_16: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_15: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_14: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_13: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_12: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_11: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_10: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_9: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_8: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_7: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_6: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_5: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_4: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_3: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_2: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_1: FD1S3BX + port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>ae); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>af); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i_inv, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_2); + + ae_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + ae_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcnt_en_inv_inv, A1=>cnt_con_inv, B0=>fcount_0, + B1=>fcount_1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open, + COUT=>co0_5); + + ae_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5); + + ae_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>co2_5); + + ae_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_5, S0=>open, S1=>open, + COUT=>ae_set_d_c); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>ae_set_d_c, S0=>ae_set_d, S1=>open, + COUT=>open); + + ae_clr_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_3); + + ae_clr_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcnt_en_inv_inv, A1=>cnt_con, B0=>fcount_0, + B1=>fcount_1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_3, S0=>open, S1=>open, + COUT=>co0_6); + + ae_clr_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con_inv, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, COUT=>co1_6); + + ae_clr_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, COUT=>co2_6); + + ae_clr_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>ae_clr_d_c); + + a3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>ae_clr_d_c, S0=>ae_clr_d, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_4); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_4, S0=>open, S1=>open, + COUT=>co0_7); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_7, S0=>open, S1=>open, COUT=>co1_7); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_7, S0=>open, S1=>open, COUT=>co2_7); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_7, S0=>open, S1=>open, + COUT=>af_set_d_c); + + a4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_d_c, S0=>af_set_d, S1=>open, + COUT=>open); + + af_clr_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_5); + + af_clr_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_5, S0=>open, S1=>open, + COUT=>co0_8); + + af_clr_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_8, S0=>open, S1=>open, COUT=>co1_8); + + af_clr_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_8, S0=>open, S1=>open, COUT=>co2_8); + + af_clr_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_8, S0=>open, S1=>open, + COUT=>af_clr_d_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_clr_d_c, S0=>af_clr_d, S1=>open, + COUT=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostEmpty <= ae; + AlmostFull <= af; +end Structure; diff --git a/cbmrich/core/FIFO_36x64/FIFO_36x64.ipx b/cbmrich/core/FIFO_36x64/FIFO_36x64.ipx new file mode 100644 index 0000000..19de3be --- /dev/null +++ b/cbmrich/core/FIFO_36x64/FIFO_36x64.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/cbmrich/core/FIFO_36x64/FIFO_36x64.lpc b/cbmrich/core/FIFO_36x64/FIFO_36x64.lpc new file mode 100644 index 0000000..321490f --- /dev/null +++ b/cbmrich/core/FIFO_36x64/FIFO_36x64.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=FIFO_36x64 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/13/2021 +Time=11:49:50 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=64 +Width=36 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Dual Threshold +PeAssert=2 +PeDeassert=4 +FullFlg=1 +PfMode=Static - Dual Threshold +PfAssert=62 +PfDeassert=60 +Reset=Async +Reset1=Sync +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n FIFO_36x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 64 -width 36 -no_enable -pe 2 -pe2 4 -pf 62 -pf2 60 -reset_rel SYNC diff --git a/cbmrich/core/FIFO_36x64/FIFO_36x64.vhd b/cbmrich/core/FIFO_36x64/FIFO_36x64.vhd new file mode 100644 index 0000000..0e347aa --- /dev/null +++ b/cbmrich/core/FIFO_36x64/FIFO_36x64.vhd @@ -0,0 +1,770 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- Module Version: 5.1 +--/usr/local/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 64 -width 36 -no_enable -pe 2 -pe2 4 -pf 62 -pf2 60 -reset_rel SYNC + +-- Wed Jan 13 11:49:50 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity FIFO_36x64 is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end FIFO_36x64; + +architecture Structure of FIFO_36x64 is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ae: std_logic; + signal ae_d: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal co3: std_logic; + signal co2: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal co1_2: std_logic; + signal wren_i: std_logic; + signal co2_2: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal co3_1: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal co3_2: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal cmp_ci_2: std_logic; + signal co0_5: std_logic; + signal co1_5: std_logic; + signal co2_5: std_logic; + signal ae_set_d: std_logic; + signal ae_set_d_c: std_logic; + signal cmp_ci_3: std_logic; + signal co0_6: std_logic; + signal co1_6: std_logic; + signal co2_6: std_logic; + signal ae_clr_d: std_logic; + signal ae_clr_d_c: std_logic; + signal cmp_ci_4: std_logic; + signal co0_7: std_logic; + signal co1_7: std_logic; + signal co2_7: std_logic; + signal af_set_d: std_logic; + signal af_set_d_c: std_logic; + signal cmp_ci_5: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_8: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_8: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_8: std_logic; + signal fcount_6: std_logic; + signal af_clr_d: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_clr_d_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x64.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_3: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_2: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>ae, AD2=>ae_set_d, AD1=>ae_clr_d, AD0=>scuba_vlo, + DO0=>ae_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set_d, AD1=>af_clr_d, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), + DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), + DI29=>Data(29), DI28=>Data(28), DI27=>Data(27), + DI26=>Data(26), DI25=>Data(25), DI24=>Data(24), + DI23=>Data(23), DI22=>Data(22), DI21=>Data(21), + DI20=>Data(20), DI19=>Data(19), DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>scuba_vlo, ADW7=>scuba_vlo, ADW6=>scuba_vlo, + ADW5=>wcount_5, ADW4=>wcount_4, ADW3=>wcount_3, + ADW2=>wcount_2, ADW1=>wcount_1, ADW0=>wcount_0, + BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi, + BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW2=>scuba_vlo, + CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>scuba_vlo, + ADR12=>scuba_vlo, ADR11=>scuba_vlo, ADR10=>rcount_5, + ADR9=>rcount_4, ADR8=>rcount_3, ADR7=>rcount_2, + ADR6=>rcount_1, ADR5=>rcount_0, ADR4=>scuba_vlo, + ADR3=>scuba_vlo, ADR2=>scuba_vlo, ADR1=>scuba_vlo, + ADR0=>scuba_vlo, CER=>rden_i, OCER=>rden_i, CLKR=>Clock, + CSR2=>scuba_vlo, CSR1=>scuba_vlo, CSR0=>scuba_vlo, + RST=>Reset, DO35=>Q(17), DO34=>Q(16), DO33=>Q(15), + DO32=>Q(14), DO31=>Q(13), DO30=>Q(12), DO29=>Q(11), + DO28=>Q(10), DO27=>Q(9), DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), + DO23=>Q(5), DO22=>Q(4), DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), + DO18=>Q(0), DO17=>Q(35), DO16=>Q(34), DO15=>Q(33), + DO14=>Q(32), DO13=>Q(31), DO12=>Q(30), DO11=>Q(29), + DO10=>Q(28), DO9=>Q(27), DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), + DO5=>Q(23), DO4=>Q(22), DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), + DO0=>Q(18)); + + FF_24: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_23: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_22: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_21: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_20: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_19: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_18: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_17: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_16: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_15: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_14: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_13: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_12: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_11: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_10: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_9: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_8: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_7: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_6: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_5: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_4: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_3: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_2: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_1: FD1S3BX + port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>ae); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>af); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>open, COUT=>co3); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>open, + COUT=>co3_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>open, + COUT=>co3_2); + + ae_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + ae_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcnt_en_inv_inv, A1=>cnt_con_inv, B0=>fcount_0, + B1=>fcount_1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open, + COUT=>co0_5); + + ae_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5); + + ae_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>co2_5); + + ae_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_5, S0=>open, S1=>open, + COUT=>ae_set_d_c); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>ae_set_d_c, S0=>ae_set_d, S1=>open, + COUT=>open); + + ae_clr_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_3); + + ae_clr_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcnt_en_inv_inv, A1=>cnt_con, B0=>fcount_0, + B1=>fcount_1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_3, S0=>open, S1=>open, + COUT=>co0_6); + + ae_clr_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con_inv, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, COUT=>co1_6); + + ae_clr_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, COUT=>co2_6); + + ae_clr_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>ae_clr_d_c); + + a3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>ae_clr_d_c, S0=>ae_clr_d, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_4); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_4, S0=>open, S1=>open, + COUT=>co0_7); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_7, S0=>open, S1=>open, COUT=>co1_7); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_7, S0=>open, S1=>open, COUT=>co2_7); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_7, S0=>open, S1=>open, + COUT=>af_set_d_c); + + a4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_d_c, S0=>af_set_d, S1=>open, + COUT=>open); + + af_clr_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_5); + + af_clr_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_5, S0=>open, S1=>open, + COUT=>co0_8); + + af_clr_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_8, S0=>open, S1=>open, COUT=>co1_8); + + af_clr_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_8, S0=>open, S1=>open, COUT=>co2_8); + + af_clr_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_8, S0=>open, S1=>open, + COUT=>af_clr_d_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_clr_d_c, S0=>af_clr_d, S1=>open, + COUT=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostEmpty <= ae; + AlmostFull <= af; +end Structure; diff --git a/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.ipx b/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.ipx new file mode 100644 index 0000000..eaac442 --- /dev/null +++ b/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.lpc b/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.lpc new file mode 100644 index 0000000..2762045 --- /dev/null +++ b/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.lpc @@ -0,0 +1,52 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP +CoreRevision=6.5 +ModuleName=RAM_pseudo_DP_wReg_36x1k +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/13/2021 +Time=11:56:00 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +RAddress=1024 +RData=36 +WAddress=1024 +WData=36 +enByte=0 +ByteSize=9 +OutputEn=1 +ClockEn=0 +Optimization=Speed +Reset=Sync +Reset1=Sync +Init=0 +MemFile= +MemFormat=bin +EnECC=0 +Pipeline=0 +init_data=0 + +[FilesGenerated] +=mem + +[Command] +cmd_line= -w -n RAM_pseudo_DP_wReg_36x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ramdps -device LFE5UM-85F -raddr_width 10 -rwidth 36 -waddr_width 10 -wwidth 36 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 diff --git a/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.vhd b/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.vhd new file mode 100644 index 0000000..b1fd4df --- /dev/null +++ b/cbmrich/core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.vhd @@ -0,0 +1,260 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- Module Version: 6.5 +--/usr/local/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n RAM_pseudo_DP_wReg_36x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type bram -wp 10 -rp 0011 -rdata_width 36 -data_width 36 -num_rows 1024 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 + +-- Wed Jan 13 11:56:01 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity RAM_pseudo_DP_wReg_36x1k is + port ( + WrAddress: in std_logic_vector(9 downto 0); + RdAddress: in std_logic_vector(9 downto 0); + Data: in std_logic_vector(35 downto 0); + WE: in std_logic; + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + WrClock: in std_logic; + WrClockEn: in std_logic; + Q: out std_logic_vector(35 downto 0)); +end RAM_pseudo_DP_wReg_36x1k; + +architecture Structure of RAM_pseudo_DP_wReg_36x1k is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE of RAM_pseudo_DP_wReg_36x1k_0_0_1 : label is "RAM_pseudo_DP_wReg_36x1k.lpc"; + attribute MEM_INIT_FILE of RAM_pseudo_DP_wReg_36x1k_0_0_1 : label is "INIT_ALL_0s"; + attribute MEM_LPC_FILE of RAM_pseudo_DP_wReg_36x1k_0_1_0 : label is "RAM_pseudo_DP_wReg_36x1k.lpc"; + attribute MEM_INIT_FILE of RAM_pseudo_DP_wReg_36x1k_0_1_0 : label is "INIT_ALL_0s"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + RAM_pseudo_DP_wReg_36x1k_0_0_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>WrAddress(9), ADA12=>WrAddress(8), + ADA11=>WrAddress(7), ADA10=>WrAddress(6), ADA9=>WrAddress(5), + ADA8=>WrAddress(4), ADA7=>WrAddress(3), ADA6=>WrAddress(2), + ADA5=>WrAddress(1), ADA4=>WrAddress(0), ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>WrClockEn, OCEA=>WrClockEn, CLKA=>WrClock, WEA=>WE, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>RdAddress(9), ADB12=>RdAddress(8), + ADB11=>RdAddress(7), ADB10=>RdAddress(6), ADB9=>RdAddress(5), + ADB8=>RdAddress(4), ADB7=>RdAddress(3), ADB6=>RdAddress(2), + ADB5=>RdAddress(1), ADB4=>RdAddress(0), ADB3=>scuba_vlo, + ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo, + CEB=>RdClockEn, OCEB=>RdClockEn, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>scuba_vlo, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), + DOB15=>Q(15), DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), + DOB11=>Q(11), DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), + DOB7=>Q(7), DOB6=>Q(6), DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), + DOB2=>Q(2), DOB1=>Q(1), DOB0=>Q(0)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + RAM_pseudo_DP_wReg_36x1k_0_1_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(35), DIA16=>Data(34), DIA15=>Data(33), + DIA14=>Data(32), DIA13=>Data(31), DIA12=>Data(30), + DIA11=>Data(29), DIA10=>Data(28), DIA9=>Data(27), + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>WrAddress(9), ADA12=>WrAddress(8), + ADA11=>WrAddress(7), ADA10=>WrAddress(6), ADA9=>WrAddress(5), + ADA8=>WrAddress(4), ADA7=>WrAddress(3), ADA6=>WrAddress(2), + ADA5=>WrAddress(1), ADA4=>WrAddress(0), ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>WrClockEn, OCEA=>WrClockEn, CLKA=>WrClock, WEA=>WE, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>RdAddress(9), ADB12=>RdAddress(8), + ADB11=>RdAddress(7), ADB10=>RdAddress(6), ADB9=>RdAddress(5), + ADB8=>RdAddress(4), ADB7=>RdAddress(3), ADB6=>RdAddress(2), + ADB5=>RdAddress(1), ADB4=>RdAddress(0), ADB3=>scuba_vlo, + ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo, + CEB=>RdClockEn, OCEB=>RdClockEn, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>scuba_vlo, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>Q(35), DOB16=>Q(34), + DOB15=>Q(33), DOB14=>Q(32), DOB13=>Q(31), DOB12=>Q(30), + DOB11=>Q(29), DOB10=>Q(28), DOB9=>Q(27), DOB8=>Q(26), + DOB7=>Q(25), DOB6=>Q(24), DOB5=>Q(23), DOB4=>Q(22), + DOB3=>Q(21), DOB2=>Q(20), DOB1=>Q(19), DOB0=>Q(18)); + +end Structure; diff --git a/cbmrich/nodelist_frankfurt.txt b/cbmrich/nodelist_frankfurt.txt new file mode 100644 index 0000000..2e858da --- /dev/null +++ b/cbmrich/nodelist_frankfurt.txt @@ -0,0 +1,13 @@ +// nodes file for parallel place&route + +[jspc37] +SYSTEM = linux +CORENUM = 7 +ENV = /d/jspc29/lattice/310_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir + +[jspc57] +SYSTEM = linux +CORENUM = 3 +ENV = /d/jspc29/lattice/310_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir diff --git a/cbmrich/par.p2t b/cbmrich/par.p2t new file mode 100644 index 0000000..e168739 --- /dev/null +++ b/cbmrich/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 11 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/cbmrich/tdc_release b/cbmrich/tdc_release new file mode 120000 index 0000000..887cdbb --- /dev/null +++ b/cbmrich/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3/ \ No newline at end of file diff --git a/cbmrich/trb5sc_cbmrich.lpf b/cbmrich/trb5sc_cbmrich.lpf new file mode 100644 index 0000000..5ad9471 --- /dev/null +++ b/cbmrich/trb5sc_cbmrich.lpf @@ -0,0 +1,43 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + diff --git a/cbmrich/trb5sc_cbmrich.prj b/cbmrich/trb5sc_cbmrich.prj new file mode 100644 index 0000000..0463bb2 --- /dev/null +++ b/cbmrich/trb5sc_cbmrich.prj @@ -0,0 +1,301 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_cbmrich" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_cbmrich.edf" +set_option log_file "workdir/trb5sc_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/ram_18x256_oreg/ram_18x256_oreg.vhd" +add_file -vhdl -lib work "./core/FIFO_36x64/FIFO_36x64.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" + +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +#CRI +add_file -vhdl -lib work "../../cri/src/trb_net16_cri_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../cri/src/cri_data_sender.vhd" +add_file -vhdl -lib work "../../cri/src/mbs_generator_cbmrich.vhd" +add_file -vhdl -lib work "../../cri/src/cri_cbm_rich_calib.vhd" + +add_file -vhdl -lib work "../../trb3/cts/source/mbs_master.vhd" +add_file -vhdl -lib work "../../trb3sc/hub_cts/code/mbs_vulom_recv.vhd" + +#CTS +add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_input.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" + +#TDC Calibration +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Calibration.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Cal_Limits_v2.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/cnt_val.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/default_val.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/LUT.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Memory.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Memory_curr.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/read_cnt.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/compare_old.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Calc_output.vhd" + +add_file -vhdl -lib work "./core/RAM_pseudo_DP_wReg_36x1k/RAM_pseudo_DP_wReg_36x1k.vhd" + +#TDC +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" + + +add_file -vhdl -lib work "./trb5sc_cbmrich.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/cbmrich/trb5sc_cbmrich.vhd b/cbmrich/trb5sc_cbmrich.vhd new file mode 100644 index 0000000..10579d5 --- /dev/null +++ b/cbmrich/trb5sc_cbmrich.vhd @@ -0,0 +1,902 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; +use work.trb_net16_hub_func.all; +use work.trb_net_gbe_components.all; +use work.cts_pkg.all; + + +entity trb5sc_cbmrich is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --AddOn +-- FE_GPIO : inout std_logic_vector(11 downto 0); +-- FE_CLK : out std_logic_vector( 2 downto 1); +-- FE_DIFF : inout std_logic_vector(63 downto 0); + INP : in std_logic_vector(63 downto 0); + + CS : out std_logic_vector(4 downto 1); + MISO : in std_logic_vector(4 downto 1); + MOSI : out std_logic; + SCK : out std_logic; + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); + HDR_IO : inout std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of trb5sc_cbmrich is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to INTERFACE_NUM); + signal int2med : int2med_array_t(0 to INTERFACE_NUM); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + -- Hub + signal med_dataready_out : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_data_out : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_dataready_in : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_data_in : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_stat_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal rdack, wrack : std_logic; + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , bus_mbs_gen_tx, bustdccal_tx, buscts_tx, buscrireg_tx, busCriDataDbgReg_tx, bus_mbs_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, bus_mbs_gen_rx, bustdccal_rx, buscts_rx, buscrireg_rx, busCriDataDbgReg_rx, bus_mbs_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1); + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0); + + signal trigger_busy_i : std_logic; + signal cts_trigger_out : std_logic; + + -- CRI / CTS /Streaming CTS part + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + + signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_rdo_data : std_logic_vector(31 downto 0); + signal cts_rdo_write : std_logic; + signal cts_rdo_finished : std_logic; + + signal cts_ext_trigger : std_logic; + signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_ext_control : std_logic_vector(31 downto 0); + signal cts_ext_debug : std_logic_vector(31 downto 0); + signal cts_ext_header : std_logic_vector(1 downto 0) := "00"; + + signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0); + signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); + + signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); + signal cts_rdo_rx : READOUT_RX; + + signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); + + signal cts_trg_send : std_logic; + signal cts_trg_type : std_logic_vector(3 downto 0); + signal cts_trg_number : std_logic_vector(15 downto 0); + signal cts_trg_information : std_logic_vector(23 downto 0); + signal cts_trg_code : std_logic_vector(7 downto 0); + signal cts_trg_status_bits : std_logic_vector(31 downto 0); + signal cts_trg_busy : std_logic; + + signal cts_ipu_send : std_logic; + signal cts_ipu_type : std_logic_vector(3 downto 0); + signal cts_ipu_number : std_logic_vector(15 downto 0); + signal cts_ipu_information : std_logic_vector(7 downto 0); + signal cts_ipu_code : std_logic_vector(7 downto 0); + signal cts_ipu_status_bits : std_logic_vector(31 downto 0); + signal cts_ipu_busy : std_logic; + + signal async_ext_trig : std_logic; + signal mbs_trigger : std_logic; + + signal mbs_local_trigger_num_in : std_logic_vector(15 downto 0); + signal mbs_local_trigger_in : std_logic; + + + --RESET sequence from CRI (as on combiner; ToBe checked) + signal reset_via_cri_long, reset_via_cri_timer, last_reset_via_cri_long, make_reset : std_logic; + signal reset_via_cri : std_logic := '0'; + signal last_cri_resetPulse : std_logic; + + + signal dlm_rx_word : std_logic_vector(7 downto 0); + signal dlm_rx_i : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal link_stat_in_reg : std_logic; + + + +begin + +trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(INTERFACE_NUM).stat_op(13), --make_reset --Used on combiner_CTS + SEND_RESET_IN => med2int(INTERFACE_NUM).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + -- Reset as on combiner_CTS: + -- maybe not needed; is currently not connected + reset_via_cri <= med2int(INTERFACE_NUM).stat_op(13); + + proc_make_reset : process begin + wait until rising_edge(clk_sys); + if( reset_via_cri = '1') then + reset_via_cri_long <= '1'; + reset_via_cri_timer <= '1'; + end if; + if timer.tick_us = '1' then + reset_via_cri_timer <= '0'; + reset_via_cri_long <= reset_via_cri_timer; + end if; + last_reset_via_cri_long <= reset_via_cri_long; + make_reset <= last_reset_via_cri_long and not reset_via_cri_long; + end process; + +--------------------------------------------------------------------------- +-- Calibration clock for TDC on Trb5sc +--------------------------------------------------------------------------- + +THE_CAL_PLL : entity work.pll_in125_out50 + port map( + CLKI => CLK_125, + CLKOP => clk_cal + ); + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(1).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(1), -- SFP uplink + MEDIA_INT2MED => int2med(1), + + --Sync operation + RX_DLM => dlm_rx_i, + RX_DLM_WORD => dlm_rx_word, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +-------------------------------------------------------------------------- +-- Hub +--------------------------------------------------------------------------- + THE_HUB : trb_net16_hub_streaming_port_sctrl_cts + generic map( + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, --DiRICH MEDIA INTERFACES + MII_IS_UPLINK => MII_IS_UPLINK, + MII_IS_DOWNLINK => MII_IS_DOWNLINK, + MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0000", + BROADCAST_BITMASK => x"7E", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + USE_ONEWIRE => c_I2C, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, + RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + RDO_HEADER_BUFFER_DEPTH => 9, + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 + --COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media interfacces --------------------------------------------------------------- + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0), + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0), + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0), + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0), + + -- Gbe Read-out Path --------------------------------------------------------------- + --Event information coming from CTS for GbE + GBE_CTS_NUMBER_OUT => gbe_cts_number, + GBE_CTS_CODE_OUT => gbe_cts_code, + GBE_CTS_INFORMATION_OUT => gbe_cts_information, + GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, + --Information sent to CTS + GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, + -- Data from Frontends + GBE_FEE_DATA_OUT => gbe_fee_data, + GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, + GBE_FEE_READ_IN => gbe_fee_read, + GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + GBE_FEE_BUSY_OUT => gbe_fee_busy, + + -- CTS Request Sending ------------------------------------------------------------- + --LVL1 trigger + CTS_TRG_SEND_IN => cts_trg_send, + CTS_TRG_TYPE_IN => cts_trg_type, + CTS_TRG_NUMBER_IN => cts_trg_number, + CTS_TRG_INFORMATION_IN => cts_trg_information, + CTS_TRG_RND_CODE_IN => cts_trg_code, + CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits, + CTS_TRG_BUSY_OUT => cts_trg_busy, + --IPU Channel + CTS_IPU_SEND_IN => cts_ipu_send, + CTS_IPU_TYPE_IN => cts_ipu_type, + CTS_IPU_NUMBER_IN => cts_ipu_number, + CTS_IPU_INFORMATION_IN => cts_ipu_information, + CTS_IPU_RND_CODE_IN => cts_ipu_code, + -- Receiver port + CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits, + CTS_IPU_BUSY_OUT => cts_ipu_busy, + + -- CTS Data Readout ---------------------------------------------------------------- + --Trigger to CTS out + RDO_TRIGGER_IN => cts_trigger_out, + RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid, + RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg, + RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg, + RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg, + RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type, + RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, + + --Data from CTS in + RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, + RDO_DATA_IN => cts_rdo_data, + RDO_DATA_WRITE_IN => cts_rdo_write, + RDO_DATA_FINISHED_IN => cts_rdo_finished, + --Data from additional modules + RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional, + RDO_ADDITIONAL_DATA => cts_rdo_additional_data, + RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, + RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, + + -- Slow Control -------------------------------------------------------------------- + COMMON_STAT_REGS => common_stat_reg, + COMMON_CTRL_REGS => common_ctrl_reg, + ONEWIRE => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + ONEWIRE_MONITOR_IN => open, + + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, + TIMER_TICKS_OUT(0) => timer.tick_us, + TIMER_TICKS_OUT(1) => timer.tick_ms, + TEMPERATURE_OUT => timer.temperature, + EXTERNAL_SEND_RESET => reset_via_cri,--med2int(INTERFACE_NUM).stat_op(15),--reset_via_cri, + + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + gen_media_record : for i in 0 to INTERFACE_NUM-1 generate + med_data_in(i*16+15 downto i*16) <= (others => '0');--med2int(i).data; + med_packet_num_in(i*3+2 downto i*3) <= (others => '0');--med2int(i).packet_num; + med_dataready_in(i) <= '0';--med2int(i).dataready; + med_read_in(i) <= '0';--med2int(i).tx_read; + med_stat_op(i*16+15 downto i*16+4) <= (others => '0');--med2int(i).stat_op; + med_stat_op(i*16+3 downto i*16) <= x"7"; + + int2med(i).data <= med_data_out(i*16+15 downto i*16); + int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3); + int2med(i).dataready <= med_dataready_out(i); + int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16); + end generate; + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + +------------------------------------------------------------------------- +--- GBE channels to CRI Board --- +------------------------------------------------------------------------- + +THE_CRI_INTERFACE : entity work.trb_net16_cri_interface + generic map ( + INCLUDE_READOUT => 1, + READOUT_BUFFER_SIZE => 4 + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + --Media Interface + MEDIA_MED2INT(0) => med2int(INTERFACE_NUM), + MEDIA_INT2MED(0) => int2med(INTERFACE_NUM), + + MY_ADDRESS_IN => timer.network_address, + + --Event information coming from CTS for CRI + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + + --Information sent to CTS + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_STATUS_BITS_OUT => gbe_cts_status_bits, + + --Data from Frontends + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, + + BUS_REG_RX => buscrireg_rx, + BUS_REG_TX => buscrireg_tx, + + BUS_DBG_RX => busCriDataDbgReg_rx, + BUS_DBG_TX => busCriDataDbgReg_tx, + + BUS_CALIBRATON_RX => bustdccal_rx, + BUS_CALIBRATON_TX => bustdccal_tx, + + TIMER_TICKS_IN(0) => timer.tick_us, + TIMER_TICKS_IN(1) => timer.tick_ms + ); + + +--------------------------------------------------------------------------- +-- Central Trigger System +--------------------------------------------------------------------------- + +THE_CTS : CTS + generic map ( + EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic + PLATTFORM => 1, -- TRB3sc+KEL+RJ45 + OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, + ADDON_GROUPS => 1, + ADDON_GROUP_UPPER => (1, others => 0) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + + TRIGGER_BUSY_OUT => trigger_busy_i, + TIME_REFERENCE_OUT => cts_trigger_out, + + ADDON_TRIGGERS_IN => cts_addon_triggers_in, + ADDON_GROUP_ACTIVITY_OUT => open, + ADDON_GROUP_SELECTED_OUT => open, + + EXT_TRIGGER_IN => cts_ext_trigger, + EXT_STATUS_IN => cts_ext_status, + EXT_CONTROL_OUT => cts_ext_control, + EXT_HEADER_BITS_IN => cts_ext_header, + EXT_FORCE_TRIGGER_INFO_IN => (others => '0'), + + PERIPH_TRIGGER_IN => (others => '0'), + + OUTPUT_MULTIPLEXERS_OUT => open, + + CTS_TRG_SEND_OUT => cts_trg_send, + CTS_TRG_TYPE_OUT => cts_trg_type, + CTS_TRG_NUMBER_OUT => cts_trg_number, + CTS_TRG_INFORMATION_OUT => cts_trg_information, + CTS_TRG_RND_CODE_OUT => cts_trg_code, + CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits, + CTS_TRG_BUSY_IN => cts_trg_busy, + + CTS_IPU_SEND_OUT => cts_ipu_send, + CTS_IPU_TYPE_OUT => cts_ipu_type, + CTS_IPU_NUMBER_OUT => cts_ipu_number, + CTS_IPU_INFORMATION_OUT => cts_ipu_information, + CTS_IPU_RND_CODE_OUT => cts_ipu_code, + CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits, + CTS_IPU_BUSY_IN => cts_ipu_busy, + + CTS_REGIO_ADDR_IN => buscts_rx.addr, + CTS_REGIO_DATA_IN => buscts_rx.data, + CTS_REGIO_READ_ENABLE_IN => buscts_rx.read, + CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write, + CTS_REGIO_DATA_OUT => buscts_tx.data, + CTS_REGIO_DATAREADY_OUT => buscts_tx.rack, + CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, + CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, + + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, + LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, + LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, + + FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, + FEE_DATA_OUT => cts_rdo_data, + FEE_DATA_WRITE_OUT => cts_rdo_write, + FEE_DATA_FINISHED_OUT => cts_rdo_finished + ); + + buscts_tx.nack <= '0'; + buscts_tx.ack <= '0'; + + + gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate + cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; + cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; + + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; + cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; + end generate; + + +--------------------------------------------------------------------------- +-- MBS +--------------------------------------------------------------------------- + + THE_MBS_GENERATOR : entity work.mbs_generator_cbmrich + port map ( + CLK_SYS => clk_sys, + CLK_RX => med2int(INTERFACE_NUM).clk_full, + RESET_IN => reset_i, + + DLM_RX_IN => dlm_rx_i, + DLM_RX_DATA => dlm_rx_word, + + MBS_LOC_TRIG => mbs_local_trigger_in, + MBS_LOC_TRIG_NUM => mbs_local_trigger_num_in, + + BUS_RX => bus_mbs_gen_rx, + BUS_TX => bus_mbs_gen_tx + ); + + + THE_MBS_MASTER : entity work.mbs_master + port map ( + CLK => med2int(INTERFACE_NUM).clk_half, + RESET_IN => reset_i, + + MBS_CLOCK_OUT => open, + MBS_DATA_OUT => mbs_trigger, + + --data output for read-out + TRIGGER_IN => mbs_local_trigger_in, + TRIGGER_NUMBER_IN => mbs_local_trigger_num_in, + DATA_OUT => open, + WRITE_OUT => open, + FINISHED_OUT => open, + STATUSBIT_OUT => open + ); + + + THE_MBS_REC : entity work.mbs_recv + generic map( + USE_40MHz => c_NO + ) + port map ( + CLK => clk_sys, + RESET_IN => reset_i, + + MBS_IN => mbs_trigger, + CLK_200 => clk_full_osc, + + TRG_ASYNC_OUT => async_ext_trig,--tdc_inputs(1), + TRG_SYNC_OUT => cts_ext_trigger, + + TRIGGER_IN => cts_rdo_rx.data_valid, + TRG_NUMBER_IN => cts_trg_number, + TRG_CODE_IN => cts_trg_code, + TIMING_TRG_IN => cts_trigger_out, + + DATA_OUT => cts_rdo_additional(0).data, + WRITE_OUT => cts_rdo_additional(0).data_write, + FINISHED_OUT => cts_rdo_additional(0).data_finished, + STATUSBIT_OUT => cts_rdo_additional(0).statusbits, + + REGIO_IN => bus_mbs_rx, + REGIO_OUT => bus_mbs_tx, + + CONTROL_REG_IN => cts_ext_control, + STATUS_REG_OUT => cts_ext_status, + HEADER_REG_OUT => cts_ext_header, + + DEBUG => cts_ext_debug + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 10, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", 4 => x"e000", 5 => x"a000", 6 => x"8300", 7 => x"e500", 8 => x"e400", 9 => x"e410", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 9, 5 => 11, 6 => 8, 7 => 8, 8 => 4, 9 => 2, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => bustdc_rx, + BUS_RX(4) => bustdccal_rx, + BUS_RX(5) => buscts_rx, + BUS_RX(6) => buscrireg_rx, + BUS_RX(7) => busCriDataDbgReg_rx, + BUS_RX(8) => bus_mbs_gen_rx, + BUS_RX(9) => bus_mbs_rx, + + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => bustdc_tx, + BUS_TX(4) => bustdccal_tx, + BUS_TX(5) => buscts_tx, + BUS_TX(6) => buscrireg_tx, + BUS_TX(7) => busCriDataDbgReg_tx, + BUS_TX(8) => bus_mbs_gen_tx, + BUS_TX(9) => bus_mbs_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO(9 downto 0), + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'),--monitor_inputs_i, + TRIG_GEN_INPUTS => (others => '0'),--trigger_inputs_i, + TRIG_GEN_OUTPUTS => open, + --TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + --TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + CS <= spi_cs(3 downto 0); + spi_miso(3 downto 0) <= MISO; + + MOSI <= spi_mosi(0) when spi_cs(0) = '0' + else spi_mosi(1) when spi_cs(1) = '0' + else spi_mosi(2) when spi_cs(2) = '0' + else spi_mosi(3) when spi_cs(3) = '0' + else '0'; + + SCK <= spi_clk(0) when spi_cs(0) = '0' + else spi_clk(1) when spi_cs(1) = '0' + else spi_clk(2) when spi_cs(2) = '0' + else spi_clk(3) when spi_cs(3) = '0' + else '1'; + + + --monitor_inputs_i <= INP(MONITOR_INPUT_NUM-1 downto 0); + --trigger_inputs_i <= INP(TRIG_GEN_INPUT_NUM-1 downto 0); + --hit_in_i <= INP(NUM_TDC_CHANNELS-2 downto 0); + + assert DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error; + + HDR_IO(15 downto 10) <= (others => '0'); + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; + FLASH_NCS <= flash_ncs_i; + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(INTERFACE_NUM).stat_op(9) or led_off; + LED_SFP_RED <= not (med2int(INTERFACE_NUM).stat_op(10) or med2int(INTERFACE_NUM).stat_op(11)) or led_off; + LED_SFP_YELLOW <= not med2int(INTERFACE_NUM).stat_op(8) or led_off; + LED <= x"F0"; + LED_RJ_GREEN <= "00"; + LED_RJ_RED <= "11"; + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_NO, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => clk_full, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => cts_trigger_out, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(INCLUDE_ETM), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => open + ); + + gen_single : if (DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 ) and (INCLUDE_ETM = c_NO) generate + hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= (others => '0'); + end generate; + + gen_single : if (DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3) and ((ETM_CHOICE = ETM_CHOICE_MBS_VULOM) and (INCLUDE_ETM = c_YES)) generate + hit_in_i(1) <= async_ext_trig; + hit_in_i(2) <= cts_ext_trigger; + hit_in_i(3) <= INP(0); + hit_in_i(4) <= INP(1); + end generate; + + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + +end architecture; + + + -- 2.43.0