From da678efe70ca3e801119054b1a184eca8e24bdb4 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Thu, 30 Aug 2012 08:30:06 +0000
Subject: [PATCH] *** empty log message ***

---
 base/code/mbs_vulom_recv.vhd | 17 ++++++++++----
 base/trb3_components.vhd     | 45 +++++++++++++++++++++++++++++-------
 base/trb3_periph_mainz.lpf   |  2 +-
 3 files changed, 51 insertions(+), 13 deletions(-)

diff --git a/base/code/mbs_vulom_recv.vhd b/base/code/mbs_vulom_recv.vhd
index 8698fd1..f464f23 100644
--- a/base/code/mbs_vulom_recv.vhd
+++ b/base/code/mbs_vulom_recv.vhd
@@ -49,7 +49,7 @@ end entity;
 -- Bit 30 - 29 : Status
 -- Bit 31      : Error flag
 
-
+--statusbit 23 will be set in case of a data error from MBS
 
 architecture mbs_vulom_recv_arch of mbs_vulom_recv is
 
@@ -62,7 +62,7 @@ signal first_bits_slow : std_logic;
 signal reg_MBS_IN      : std_logic;
 signal done            : std_logic;
 
-signal numer_reg       : std_logic_vector(23 downto 0);
+signal number_reg      : std_logic_vector(23 downto 0);
 signal status_reg      : std_logic_vector(1 downto 0);
 signal error_reg       : std_logic;
 
@@ -132,7 +132,7 @@ end process;
 PROC_REG_INFO : process begin
   wait until rising_edge(CLK);
   if done = '1' then
-    numer_reg <= shift_reg(31 downto 8);
+    number_reg <= shift_reg(31 downto 8);
     status_reg <= shift_reg(7 downto 6);
     if shift_reg(36 downto 32) = "01010" and shift_reg(4 downto 0) = "10101" and xor_all(31 downto 5) = '0' then
       error_reg <= '0';
@@ -145,10 +145,19 @@ end process;
 
 PROC_RDO : process begin
   wait until rising_edge(CLK);
+  WRITE_OUT     <= '0';
+  FINISHED_OUT  <= '0';
+  STATUSBIT_OUT <= (23 => error_reg, others => '0');
   case rdostate is
     when RDO_IDLE =>
-    when RDO_WRITE =>
+      if TRIGGER_IN = '1' then
+        rdostate <= RDO_FINISH;
+        DATA_OUT <= error_reg & status_reg & "00000" & number_reg;
+        WRITE_OUT <= '1';
+      end if;
     when RDO_FINISH =>
+      FINISHED_OUT <= '1';
+      rdostate     <= RDO_IDLE;
   end case;
 end process;
 
diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index f0c88a3..8695c12 100644
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -28,7 +28,7 @@ component pll_in125_out125
 
 component TDC
   generic (
-    CHANNEL_NUMBER : integer range 0 to 64;
+    CHANNEL_NUMBER : integer range 2 to 65;
     STATUS_REG_NR  : integer range 0 to 6;
     CONTROL_REG_NR : integer range 0 to 6);
   port (
@@ -83,14 +83,16 @@ component Reference_Channel
     REF_DEBUG_OUT        : out std_logic_vector(31 downto 0));
 end component;
 
-component Channel
+component Channel is
+
   generic (
-    CHANNEL_ID : integer range 1 to 65);
+    CHANNEL_ID : integer range 1 to 64);
   port (
-    RESET_WR             : in  std_logic;
-    RESET_RD             : in  std_logic;
-    CLK_WR               : in  std_logic;
-    CLK_RD               : in  std_logic;
+    RESET_200            : in  std_logic;
+    RESET_100            : in  std_logic;
+    CLK_200              : in  std_logic;
+    CLK_100              : in  std_logic;
+--
     HIT_IN               : in  std_logic;
     READ_EN_IN           : in  std_logic;
     FIFO_DATA_OUT        : out std_logic_vector(31 downto 0);
@@ -98,11 +100,38 @@ component Channel
     FIFO_FULL_OUT        : out std_logic;
     FIFO_ALMOST_FULL_OUT : out std_logic;
     COARSE_COUNTER_IN    : in  std_logic_vector(10 downto 0);
+--
     LOST_HIT_NUMBER      : out std_logic_vector(23 downto 0);
     HIT_DETECT_NUMBER    : out std_logic_vector(23 downto 0);
     ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
     FIFO_WR_NUMBER       : out std_logic_vector(23 downto 0);
-    Channel_DEBUG_01     : out std_logic_vector(31 downto 0));
+--
+    Channel_DEBUG        : out std_logic_vector(31 downto 0)
+    );
+
+end component;
+
+
+component Channel_200 is
+
+  generic (
+    CHANNEL_ID : integer range 0 to 64);  
+  port (
+    CLK_200              : in  std_logic;   -- 200 MHz clk
+    RESET_200            : in  std_logic;   -- reset sync with 200Mhz clk
+    CLK_100              : in  std_logic;   -- 100 MHz clk
+    RESET_100            : in  std_logic;   -- reset sync with 100Mhz clk
+--
+    HIT_IN               : in  std_logic;   -- hit in
+    COARSE_CNTR_IN       : in  std_logic_vector(10 downto 0);  -- coarse counter in
+    READ_EN_IN           : in  std_logic;   -- read en signal
+    FIFO_DATA_OUT        : out std_logic_vector(31 downto 0);  -- fifo data out
+    FIFO_EMPTY_OUT       : out std_logic;   -- fifo empty signal
+    FIFO_FULL_OUT        : out std_logic;   -- fifo full signal
+    FIFO_ALMOST_FULL_OUT : out std_logic;   -- fifo almost full signal
+    FIFO_WR_OUT          : out std_logic;   -- fifo wr en signal
+    ENCODER_START_OUT    : out std_logic);  -- encoder start signal
+
 end component;
 
 component ROM_FIFO
diff --git a/base/trb3_periph_mainz.lpf b/base/trb3_periph_mainz.lpf
index d45a387..e82b00b 100644
--- a/base/trb3_periph_mainz.lpf
+++ b/base/trb3_periph_mainz.lpf
@@ -6,7 +6,7 @@ BLOCK RD_DURING_WR_PATHS ;
 #################################################################
 # Basic Settings
 #################################################################
-
+SYSCONFIG MCCLK_FREQ = 20;
 FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
 FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-- 
2.43.0