From db2c4f0225f4f57420e436d23153e5ab9e7d0273 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 22 Oct 2010 08:59:03 +0000 Subject: [PATCH] *** empty log message *** --- gbe_ecp2m/trb_net16_gbe_buf.vhd | 42 +++++++++++++---------- gbe_ecp2m/trb_net16_gbe_packet_constr.vhd | 3 -- gbe_ecp2m/trb_net16_gbe_setup.vhd | 12 +++---- gbe_ecp2m/trb_net16_ipu2gbe.vhd | 2 +- gbe_ecp2m/trb_net_gbe_components.vhd | 10 ++++-- 5 files changed, 39 insertions(+), 30 deletions(-) diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd index 46eb018..ad46d18 100755 --- a/gbe_ecp2m/trb_net16_gbe_buf.vhd +++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd @@ -7,7 +7,7 @@ use IEEE.std_logic_arith.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; ---use work.trb_net16_hub_func.all; +use work.trb_net16_hub_func.all; use work.trb_net_gbe_components.all; --use work.version.all; @@ -457,6 +457,9 @@ signal link_state : std_logic_vector(3 downto 0); signal monitor_empty : std_logic_vector(31 downto 0); +-- gk 07.10.10 +signal pc_eos : std_logic; + begin stage_ctrl_regs <= STAGE_CTRL_REGS_IN; @@ -544,8 +547,8 @@ port map( DBG_FT1_IN => dbg_ft1, DBG_FT2_IN => dbg_ft2, DBG_FIFO_RD_EN_OUT => dbg_rd_en, - DBG_FIFO_Q_IN => dbg_q, - DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10 + DBG_FIFO_Q_IN => dbg_q + --DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10 ); -- IP configurator: allows IP config to change for each event builder @@ -625,7 +628,7 @@ port map( CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10 DATA_GBE_ENABLE_IN => use_gbe, --'1', --: in std_logic; -- IPU data is forwarded to GbE -- gk 22.04.10 DATA_IPU_ENABLE_IN => use_trbnet, --'0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10 - MULTI_EVT_ENABLE_IN => use_multievents, --'1', --: in std_logic; -- enable multi event packets -- gk 22.04.10 + MULT_EVT_ENABLE_IN => use_multievents, MAX_MESSAGE_SIZE_IN => max_packet, --x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10 MIN_MESSAGE_SIZE_IN => min_packet, -- gk 20.07.10 READOUT_CTR_IN => readout_ctr, -- gk 26.04.10 @@ -636,6 +639,7 @@ port map( PC_DATA_OUT => pc_data, PC_READY_IN => pc_ready, PC_SOS_OUT => pc_sos, + PC_EOS_OUT => pc_eos, -- gk 07.10.10 PC_EOD_OUT => pc_eod, PC_SUB_SIZE_OUT => pc_sub_size, PC_TRIG_NR_OUT => pc_trig_nr, @@ -667,10 +671,12 @@ port map( -- ports for user logic RESET => RESET, CLK => CLK, + MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10 PC_WR_EN_IN => pc_wr_en, PC_DATA_IN => pc_data, PC_READY_OUT => pc_ready, PC_START_OF_SUB_IN => pc_sos, + PC_END_OF_SUB_IN => pc_eos, -- gk 07.10.10 PC_END_OF_DATA_IN => pc_eod, -- queue and subevent layer headers PC_SUB_SIZE_IN => pc_sub_size, @@ -1229,20 +1235,20 @@ discfrm_sync : signal_sync -- otherwise, the frame will be kept to readout via slow control db_fifo_rst <= '1' when ((RESET = '1') or ((mac_tx_done = '1') and (discfrm_ctr = x"00000000"))) else '0'; -debug_fifo : fifo_4096x9 -port map( - Data(7 downto 0) => pcs_txd, - Data(8) => '0', - WrClock => serdes_clk_125, - RdClock => CLK, - WrEn => pcs_tx_en, - RdEn => dbg_rd_en, - Reset => db_fifo_rst, - RPReset => db_fifo_rst, - Q => dbg_q(8 downto 0), - Empty => open, - Full => open -); +-- debug_fifo : fifo_4096x9 +-- port map( +-- Data(7 downto 0) => pcs_txd, +-- Data(8) => '0', +-- WrClock => serdes_clk_125, +-- RdClock => CLK, +-- WrEn => pcs_tx_en, +-- RdEn => dbg_rd_en, +-- Reset => db_fifo_rst, +-- RPReset => db_fifo_rst, +-- Q => dbg_q(8 downto 0), +-- Empty => open, +-- Full => open +-- ); ------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd index 2b03703..1102f44 100755 --- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd @@ -160,9 +160,6 @@ all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for de sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging --- Fixed numbers - ---max_frame_size <= x"0578"; -- 1400 max_frame_size <= PC_MAX_FRAME_SIZE_IN; -- Ready signal for PacketConstructor diff --git a/gbe_ecp2m/trb_net16_gbe_setup.vhd b/gbe_ecp2m/trb_net16_gbe_setup.vhd index 04545df..942f906 100644 --- a/gbe_ecp2m/trb_net16_gbe_setup.vhd +++ b/gbe_ecp2m/trb_net16_gbe_setup.vhd @@ -72,8 +72,8 @@ port( DBG_FT1_IN : in std_logic_vector(31 downto 0); DBG_FT2_IN : in std_logic_vector(31 downto 0); DBG_FIFO_RD_EN_OUT : out std_logic; - DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0); - DBG_RESET_FIFO_OUT : out std_logic -- gk 28.09.10 + DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0) + --DBG_RESET_FIFO_OUT : out std_logic -- gk 28.09.10 ); end entity; @@ -125,7 +125,7 @@ begin BUS_DATA_OUT <= data_out; -- gk 26.04.10 GBE_DELAY_OUT <= delay; -- gk 28.04.10 GBE_ALLOW_LARGE_OUT <= allow_large; -- gk 21.07.10 - DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10 + --DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10 end if; end process OUT_PROC; @@ -152,12 +152,12 @@ begin subevent_id <= x"0000_00cf"; subevent_dec <= x"0002_0001"; queue_dec <= x"0003_0062"; - max_packet <= x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester + max_packet <= x"0000_0fd0"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester min_packet <= x"0000_0007"; -- gk 20.07.10 max_frame <= x"0578"; - use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured + use_gbe <= '1'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured use_trbnet <= '0'; - use_multievents <= '0'; + use_multievents <= '1'; reset_values <= '0'; readout_ctr <= x"00_0000"; -- gk 26.04.10 -- gk 07.06.10 corrected bug found by Sergey readout_ctr_valid <= '0'; -- gk 26.04.10 diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd index ee61bdc..73c8d7a 100755 --- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd +++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd @@ -34,7 +34,7 @@ port( CONFIG_DONE_IN : in std_logic; -- configuration finished DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULTI_EVT_ENABLE_IN : in std_logic; -- enable multi event packets + MULT_EVT_ENABLE_IN : in std_logic; MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 diff --git a/gbe_ecp2m/trb_net_gbe_components.vhd b/gbe_ecp2m/trb_net_gbe_components.vhd index b329b0d..daafa85 100644 --- a/gbe_ecp2m/trb_net_gbe_components.vhd +++ b/gbe_ecp2m/trb_net_gbe_components.vhd @@ -36,7 +36,7 @@ port( CONFIG_DONE_IN : in std_logic; -- configuration finished DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULTI_EVT_ENABLE_IN : in std_logic; -- enable multi event packets + MULT_EVT_ENABLE_IN : in std_logic; MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 @@ -47,11 +47,12 @@ port( PC_DATA_OUT : out std_logic_vector (7 downto 0); PC_READY_IN : in std_logic; PC_SOS_OUT : out std_logic; + PC_EOS_OUT : out std_logic; -- gk 07.10.10 PC_EOD_OUT : out std_logic; PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(191 downto 0); + MONITOR_OUT : out std_logic_vector(223 downto 0); DEBUG_OUT : out std_logic_vector(383 downto 0) ); end component; @@ -60,11 +61,13 @@ component trb_net16_gbe_packet_constr is port( RESET : in std_logic; CLK : in std_logic; + MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10 -- ports for user logic PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic PC_DATA_IN : in std_logic_vector(7 downto 0); PC_READY_OUT : out std_logic; PC_START_OF_SUB_IN : in std_logic; + PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 PC_END_OF_DATA_IN : in std_logic; -- queue and subevent layer headers PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap @@ -249,6 +252,8 @@ port( MONITOR_HDR_IN : in std_logic_vector(31 downto 0); MONITOR_FIFOS_IN : in std_logic_vector(31 downto 0); MONITOR_DISCFRM_IN : in std_logic_vector(31 downto 0); + MONITOR_LINK_DWN_IN : in std_logic_vector(31 downto 0); -- gk 30.09.10 + MONITOR_EMPTY_IN : in std_logic_vector(31 downto 0); -- gk 01.10.10 -- gk 01.06.10 DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0); DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0); @@ -270,6 +275,7 @@ port( DBG_FT2_IN : in std_logic_vector(31 downto 0); DBG_FIFO_RD_EN_OUT : out std_logic; DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0) + --DBG_FIFO_RESET_OUT : out std_logic ); end component; -- 2.43.0