From dc09cb0aa76a9e42d1588a2dcbfaac5e88b1879a Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 10 Feb 2023 13:44:25 +0100 Subject: [PATCH] add external reset to clock handler --- gbe_trb_ecp5/base/clock_reset_handler.vhd | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gbe_trb_ecp5/base/clock_reset_handler.vhd b/gbe_trb_ecp5/base/clock_reset_handler.vhd index ea801cb..593b8fe 100644 --- a/gbe_trb_ecp5/base/clock_reset_handler.vhd +++ b/gbe_trb_ecp5/base/clock_reset_handler.vhd @@ -12,6 +12,7 @@ entity clock_reset_handler is port ( CLOCK_IN : in std_logic; -- oscillator GLOBAL_RESET_IN : in std_logic; + RESET_FROM_NET : in std_logic := '0'; -- reset via gbe RESET_OUT : out std_logic; CLEAR_OUT : out std_logic; @@ -102,7 +103,7 @@ THE_RESET_HANDLER : trb_net_reset_handler SYSCLK_IN => sys_clk_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => '0', -- TRBnet reset signal (SYSCLK) + TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK) CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE! RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => debug_reset_handler -- 2.43.0