From dd4b1c41a0175b62fef0f0dbf490d1b3da10672f Mon Sep 17 00:00:00 2001
From: hadaq <hadaq>
Date: Wed, 26 May 2010 10:14:34 +0000
Subject: [PATCH] *** empty log message ***

---
 slowcontrol.tex | 53 +++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 43 insertions(+), 10 deletions(-)

diff --git a/slowcontrol.tex b/slowcontrol.tex
index f9b5a9b..8a9d71e 100755
--- a/slowcontrol.tex
+++ b/slowcontrol.tex
@@ -212,10 +212,11 @@ Table \ref{regioaddressmap} shows a list of most defined registers within the sl
 \hline
 \textbf{Address} & \textbf{Name} & \textbf{Description} \\
 \hline\hline
-00 & common status register 0 & Basic Error Flags and Temperature (see below) (r) \\
-01 & common status register 1 & LVL1 trigger number (Bits 15..0), timing Trigger number (Bits 31..16) (r) \\
-20 & common control register 0 & Strobes for board resets and test triggers (see below) (w)\\
-21 & common control register 1 & Sets LVL1 trigger number (Bits 15..0) (r/w)\\
+00 & common status register 0 (CSR0) & Basic Error Flags and Temperature (see below) (r) \\
+01 & common status register 1 (CSR1) & LVL1 trigger number (Bits 15..0), timing Trigger number (Bits 31..16) (r) \\
+20 & common control register 0 (CCR0) & Strobes for board resets and test triggers (see below) (w)\\
+21 & common control register 1 (CCR1) & Sets LVL1 trigger number (Bits 15..0) (r/w)\\
+22 & common control register 2 (CCR2) & frontend enable, trigger enable, debug enable (r/w)\\
 40 & information ROM 0 & Compile Time (set by generic) (r)\\
 41 & information ROM 1 & Design Version (set by generic) (r) \\
 42 & information ROM 2 & Hardware Information (set by generic) (r)\\
@@ -252,10 +253,21 @@ E000 -- FFFF & Debugging & Memories and Registers for Debugging \\
 
 \paragraph{Common Control and Status Registers}
 
-The first common status register is described in table \ref{CommonStatReg0}. It is used for error flags and readback of the boards temperature. The second status register is used to read the LVL1 trigger number of the last timing trigger (Bits 15 - 0) and the number of the event last read on the IPU channel (Bits 31 - 16).
+The first common status register is described in table \ref{CommonStatReg0}. It is used for error flags 
+and readback of the boards temperature. The second status register is used to read the LVL1 trigger number 
+of the last timing trigger (Bits 15 -- 0) and the number of the event last read on the IPU channel 
+(Bits 31 -- 16).
 
+\noindent The first common control register consists of strobe signals for dummy timing triggers and reset 
+signals as shown in table \ref{CommonCtrlReg0}. N.B. before a complete reset or reboot is executed, a 
+delay of about 3~us has to be included to allow the endpoint to send back a correct answer. 
 
-The first common control register consists of strobe signals for dummy timing triggers and reset signals as shown in table \ref{CommonCtrlReg0}. N.B. before a complete reset or reboot is executed, a delay of about 3~us has to be included to allow the endpoint to send back a correct answer. The second common control register is used to set the current LVL1 trigger number (Bits 15 - 0) and the number of received timing triggers (Bits 31-16).
+\noindent The second common control register is used to set the current LVL1 trigger number (Bits 15 -- 0) 
+and the number of received timing triggers (Bits 31-16). 
+
+\noindent The third control register includes frontend enable bits (Bits 15 -- 0), as well as a trigger 
+enable bit (Bit 31), a debug enable bit (Bit 30), and three data format bits for general usage (Bits 23 -- 20). 
+A detailed bit definition can be found in table~\ref{CommonCtrlReg2}.
 
 \begin{table}
 \begin{center}
@@ -298,18 +310,39 @@ The first common control register consists of strobe signals for dummy timing tr
 3 & master reset \\
 10 & reset sequence counter \\
 15 & reboot FPGA \\
-16 - 19 & dummy timing triggers \\
-20 - 21 & reserved \\
+16 -- 19 & dummy timing triggers \\
+20 -- 21 & reserved \\
 22 & Begin Run trigger \\
 23 & End Run trigger \\
-24 - 31 & user defined \\
+24 -- 31 & user defined \\
 \hline
 \end{tabular}
-\caption{Common Control Register 0. All bits are strobe signals.}
+\caption{Common Control Register 0 (CCR1). All bits are strobe signals.}
 \label{CommonCtrlReg0}
 \end{center}
 \end{table}
 
+
+\begin{table}
+\begin{center}
+\begin{tabular}{|c|c|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+0 -- 15 & reset frontends \\
+16 -- 19 & reserved \\
+20 -- 23 & data format \\
+24 - 29 & reserved \\
+30 & enable debug \\
+31 & enable trigger \\
+\hline
+\end{tabular}
+\caption{Common Control Register 2 (CCR2)}
+\label{CommonCtrlReg2}
+\end{center}
+\end{table}
+
+
 \paragraph{Hardware Information (0x42)}
 This register holds information about the type of hardware. The upper 16 bit define the hardware type, the lower 16 bit are kept free to mark minor differences in the hardware setup such as optional patch wires used in the design. Design variants can also be marked using these bits. Their definition is given in the section dealing with detector specific features. The upper 16 bit are defined in table \ref{HardwareInformation}
 
-- 
2.43.0