From dd6e4192ba828335c282af32b39eb910c5312dee Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Thu, 29 Jul 2010 09:59:47 +0000
Subject: [PATCH] *** empty log message ***

---
 gbe_ecp2m/trb_net16_gbe_buf.vhd           |  347 ++-
 gbe_ecp2m/trb_net16_gbe_frame_constr.vhd  |   15 +-
 gbe_ecp2m/trb_net16_gbe_packet_constr.vhd |  429 ++--
 gbe_ecp2m/trb_net16_gbe_setup.vhd         |  119 +-
 gbe_ecp2m/trb_net16_ipu2gbe.vhd           | 2319 ++++++++++++---------
 gbe_ecp2m/trb_net_gbe_components.vhd      |   54 +-
 6 files changed, 1737 insertions(+), 1546 deletions(-)

diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd
index bda8c3e..e5ec7ec 100755
--- a/gbe_ecp2m/trb_net16_gbe_buf.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd
@@ -8,7 +8,8 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb_net16_hub_func.all;
-use work.version.all;
+use work.trb_net_gbe_components.all;
+--use work.version.all;
 
 entity trb_net16_gbe_buf is
 generic( 
@@ -82,102 +83,6 @@ port(
 	SFP_PRSNT_N_IN				: in	std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
 	SFP_LOS_IN					: in	std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
 	SFP_TXDIS_OUT				: out	std_logic; -- SFP disable
-	-------------------------------------------------------------------------------------------
-	-------------------------------------------------------------------------------------------
-	-- PacketConstructor interface
-	IG_CTS_CTR_TST				: out	std_logic_vector(2 downto 0);
-	IG_REM_CTR_TST				: out	std_logic_vector(3 downto 0);
-	IG_BSM_LOAD_TST				: out	std_logic_vector(3 downto 0);
-	IG_BSM_SAVE_TST				: out	std_logic_vector(3 downto 0);
-	IG_DATA_TST					: out	std_logic_vector(15 downto 0);
-	IG_WCNT_TST					: out	std_logic_vector(15 downto 0);
-	IG_RCNT_TST					: out	std_logic_vector(16 downto 0);
-	IG_RD_EN_TST				: out	std_logic;
-	IG_WR_EN_TST				: out	std_logic;
-	IG_EMPTY_TST				: out	std_logic;
-	IG_AEMPTY_TST				: out	std_logic;
-	IG_FULL_TST					: out	std_logic;
-	IG_AFULL_TST				: out	std_logic;
-	PC_WR_EN_TST				: out	std_logic;
-	PC_DATA_TST					: out	std_logic_vector (7 downto 0);
-	PC_READY_TST				: out	std_logic;
-	PC_START_OF_SUB_TST			: out	std_logic;
-	PC_END_OF_DATA_TST			: out	std_logic;
-	PC_SUB_SIZE_TST				: out	std_logic_vector(31 downto 0);
-	PC_TRIG_NR_TST				: out	std_logic_vector(31 downto 0);
-	PC_PADDING_TST				: out	std_logic;
-	PC_DECODING_TST				: out	std_logic_vector(31 downto 0);
-	PC_EVENT_ID_TST				: out	std_logic_vector(31 downto 0);
-	PC_QUEUE_DEC_TST			: out	std_logic_vector(31 downto 0);
-	PC_BSM_CONSTR_TST			: out	std_logic_vector(3 downto 0);
-	PC_BSM_LOAD_TST				: out	std_logic_vector(3 downto 0);
-	PC_BSM_SAVE_TST				: out	std_logic_vector(3 downto 0);
-	PC_SHF_EMPTY_TST			: out	std_logic;
-	PC_SHF_FULL_TST				: out	std_logic;
-	PC_SHF_WR_EN_TST			: out	std_logic;
-	PC_SHF_RD_EN_TST			: out	std_logic;
-	PC_SHF_Q_TST				: out	std_logic_vector(7 downto 0);
-	PC_DF_EMPTY_TST				: out	std_logic;
-	PC_DF_FULL_TST				: out	std_logic;
-	PC_DF_WR_EN_TST				: out	std_logic;
-	PC_DF_RD_EN_TST				: out	std_logic;
-	PC_DF_Q_TST					: out	std_logic_vector(7 downto 0);
-	PC_ALL_CTR_TST				: out	std_logic_vector(4 downto 0);
-	PC_SUB_CTR_TST				: out	std_logic_vector(4 downto 0);
-	PC_BYTES_LOADED_TST			: out	std_logic_vector(15 downto 0);
-	PC_SIZE_LEFT_TST			: out	std_logic_vector(31 downto 0);
-	PC_SUB_SIZE_TO_SAVE_TST		: out	std_logic_vector(31 downto 0);
-	PC_SUB_SIZE_LOADED_TST		: out	std_logic_vector(31 downto 0);
-	PC_SUB_BYTES_LOADED_TST		: out	std_logic_vector(31 downto 0);
-	PC_QUEUE_SIZE_TST			: out	std_logic_vector(31 downto 0);
-	PC_ACT_QUEUE_SIZE_TST		: out	std_logic_vector(31 downto 0);
-	-------------------------------------------------------------------------------------------
-	-------------------------------------------------------------------------------------------
-	-- FrameConstructor interface
-	FC_WR_EN_TST				: out	std_logic;
-	FC_DATA_TST					: out	std_logic_vector(7 downto 0);
-	FC_H_READY_TST				: out	std_logic;
-	FC_READY_TST				: out	std_logic;
-	FC_IP_SIZE_TST				: out	std_logic_vector(15 downto 0);
-	FC_UDP_SIZE_TST				: out	std_logic_vector(15 downto 0);
-	FC_IDENT_TST				: out	std_logic_vector(15 downto 0);
-	FC_FLAGS_OFFSET_TST			: out	std_logic_vector(15 downto 0);
-	FC_SOD_TST					: out	std_logic;
-	FC_EOD_TST					: out	std_logic;
-	FC_BSM_CONSTR_TST			: out	std_logic_vector(7 downto 0);
-	FC_BSM_TRANS_TST			: out	std_logic_vector(3 downto 0);
-	-------------------------------------------------------------------------------------------
-	-------------------------------------------------------------------------------------------
-	-- FrameTransmitter interface
-	FT_DATA_TST 				: out	std_logic_vector(8 downto 0);
-	FT_TX_EMPTY_TST				: out	std_logic;
-	FT_START_OF_PACKET_TST		: out	std_logic;
-	FT_BSM_INIT_TST				: out	std_logic_vector(3 downto 0);
-	FT_BSM_MAC_TST				: out	std_logic_vector(3 downto 0);
-	FT_BSM_TRANS_TST			: out	std_logic_vector(3 downto 0);
-	-------------------------------------------------------------------------------------------
-	-------------------------------------------------------------------------------------------
-	-- MAC interface
-	MAC_HADDR_TST				: out	std_logic_vector(7 downto 0);
-	MAC_HDATA_TST				: out	std_logic_vector(7 downto 0);
-	MAC_HCS_TST					: out	std_logic;
-	MAC_HWRITE_TST				: out	std_logic;
-	MAC_HREAD_TST				: out	std_logic;
-	MAC_HREADY_TST				: out	std_logic;
-	MAC_HDATA_EN_TST			: out	std_logic;
-	MAC_FIFOAVAIL_TST			: out	std_logic;
-	MAC_FIFOEOF_TST				: out	std_logic;
-	MAC_FIFOEMPTY_TST			: out	std_logic;
-	MAC_TX_READ_TST				: out	std_logic;
-	MAC_TX_DONE_TST				: out	std_logic;
-	-------------------------------------------------------------------------------------------
-	-------------------------------------------------------------------------------------------
-	-- pcs and serdes
-	PCS_AN_LP_ABILITY_TST		: out	std_logic_vector(15 downto 0);
-	PCS_AN_COMPLETE_TST			: out	std_logic;
-	PCS_AN_PAGE_RX_TST			: out	std_logic;
-	-------------------------------------------------------------------------------------------
-	-------------------------------------------------------------------------------------------
 	-- debug ports
 	ANALYZER_DEBUG_OUT			: out	std_logic_vector(63 downto 0)
 );
@@ -331,6 +236,21 @@ port(
 );
 end component;
 
+component fifo_4096x9 is
+port( 
+	Data    : in    std_logic_vector(8 downto 0);
+	WrClock : in    std_logic;
+	RdClock : in    std_logic;
+	WrEn    : in    std_logic;
+	RdEn    : in    std_logic;
+	Reset   : in    std_logic;
+	RPReset : in    std_logic;
+	Q       : out   std_logic_vector(8 downto 0);
+	Empty   : out   std_logic;
+	Full    : out   std_logic
+);
+end component;
+
 signal ig_bsm_save				: std_logic_vector(3 downto 0);
 signal ig_bsm_load				: std_logic_vector(3 downto 0);
 signal ig_cts_ctr				: std_logic_vector(2 downto 0);
@@ -462,6 +382,7 @@ signal ip_cfg_mem_clk			: std_logic;
 
 -- gk 22.04.10
 signal max_packet                    : std_logic_vector(31 downto 0);
+signal min_packet                    : std_logic_vector(31 downto 0);
 signal use_gbe                       : std_logic;
 signal use_trbnet                    : std_logic;
 signal use_multievents               : std_logic;
@@ -476,6 +397,16 @@ signal ft_eod                        : std_logic;
 -- gk 01.06.10
 signal dbg_ipu2gbe1                  : std_logic_vector(31 downto 0);
 signal dbg_ipu2gbe2                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe3                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe4                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe5                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe6                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe7                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe8                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe9                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe10                 : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe11                 : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe12                 : std_logic_vector(31 downto 0);
 signal dbg_pc1                       : std_logic_vector(31 downto 0);
 signal dbg_pc2                       : std_logic_vector(31 downto 0);
 signal dbg_fc1                       : std_logic_vector(31 downto 0);
@@ -487,6 +418,23 @@ signal mac_tx_staten                 : std_logic;
 signal mac_tx_statevec               : std_logic_vector(30 downto 0);
 signal mac_tx_discfrm                : std_logic;
 
+signal dbg_rd_en                     : std_logic;
+signal dbg_q                         : std_logic_vector(15 downto 0);
+
+-- gk 21.07.10
+signal allow_large                   : std_logic;
+
+-- gk 23.07.10
+signal reset_fifo                    : std_logic;
+
+-- gk 28.07.10
+signal bytes_sent_ctr                : std_logic_vector(31 downto 0);
+signal monitor_sent                  : std_logic_vector(31 downto 0);
+signal monitor_dropped               : std_logic_vector(31 downto 0);
+signal monitor_sm                    : std_logic_vector(31 downto 0);
+signal monitor_lr                    : std_logic_vector(31 downto 0);
+signal monitor_hr                    : std_logic_vector(31 downto 0);
+
 begin
 
 stage_ctrl_regs <= STAGE_CTRL_REGS_IN;
@@ -530,6 +478,7 @@ port map(
 	GBE_SUBEVENT_DEC_OUT      => pc_decoding,
 	GBE_QUEUE_DEC_OUT         => pc_queue_dec,
 	GBE_MAX_PACKET_OUT        => max_packet,
+	GBE_MIN_PACKET_OUT        => min_packet,  -- gk 20.07.10
 	GBE_MAX_FRAME_OUT         => pc_max_frame_size,
 	GBE_USE_GBE_OUT           => use_gbe,
 	GBE_USE_TRBNET_OUT        => use_trbnet,
@@ -537,15 +486,35 @@ port map(
 	GBE_READOUT_CTR_OUT       => readout_ctr,  -- gk 26.04.10
 	GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid,  -- gk 26.04.10
 	GBE_DELAY_OUT             => pc_delay,
+	GBE_ALLOW_LARGE_OUT       => allow_large,  -- gk 21.07.10
+	-- gk 28.07.10
+	MONITOR_BYTES_IN          => bytes_sent_ctr,
+	MONITOR_SENT_IN           => monitor_sent,
+	MONITOR_DROPPED_IN        => monitor_dropped,
+	MONITOR_SM_IN             => monitor_sm,
+	MONITOR_LR_IN             => monitor_lr,
+	MONITOR_HDR_IN            => monitor_hr,
 	-- gk 01.06.10
 	DBG_IPU2GBE1_IN           => dbg_ipu2gbe1,
 	DBG_IPU2GBE2_IN           => dbg_ipu2gbe2,
+	DBG_IPU2GBE3_IN           => dbg_ipu2gbe3,
+	DBG_IPU2GBE4_IN           => dbg_ipu2gbe4,
+	DBG_IPU2GBE5_IN           => dbg_ipu2gbe5,
+	DBG_IPU2GBE6_IN           => dbg_ipu2gbe6,
+	DBG_IPU2GBE7_IN           => dbg_ipu2gbe7,
+	DBG_IPU2GBE8_IN           => dbg_ipu2gbe8,
+	DBG_IPU2GBE9_IN           => dbg_ipu2gbe9,
+	DBG_IPU2GBE10_IN          => dbg_ipu2gbe10,
+	DBG_IPU2GBE11_IN          => dbg_ipu2gbe11,
+	DBG_IPU2GBE12_IN          => dbg_ipu2gbe12,
 	DBG_PC1_IN                => dbg_pc1,
 	DBG_PC2_IN                => dbg_pc2,
 	DBG_FC1_IN                => dbg_fc1,
 	DBG_FC2_IN                => dbg_fc2,
 	DBG_FT1_IN                => dbg_ft1,
-	DBG_FT2_IN                => dbg_ft2
+	DBG_FT2_IN                => dbg_ft2,
+	DBG_FIFO_RD_EN_OUT        => dbg_rd_en,
+	DBG_FIFO_Q_IN             => dbg_q
 );
 
 -- IP configurator: allows IP config to change for each event builder
@@ -628,35 +597,37 @@ port map(
 	DATA_IPU_ENABLE_IN			=> use_trbnet, --'0', --: in	std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10
 	MULTI_EVT_ENABLE_IN			=> use_multievents, --'1', --: in	std_logic; -- enable multi event packets  -- gk 22.04.10
 	MAX_MESSAGE_SIZE_IN			=> max_packet, --x"0000_FDE8",  -- gk 08.04.10  -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10
+	MIN_MESSAGE_SIZE_IN			=> min_packet, -- gk 20.07.10
 	READOUT_CTR_IN				=> readout_ctr, -- gk 26.04.10
 	READOUT_CTR_VALID_IN			=> readout_ctr_valid, -- gk 26.04.10
+	ALLOW_LARGE_IN				=> allow_large, -- gk 21.07.10
 	-- PacketConstructor interface
 	PC_WR_EN_OUT				=> pc_wr_en,
-	PC_DATA_OUT					=> pc_data,
-	PC_READY_IN					=> pc_ready,
-	PC_SOS_OUT					=> pc_sos,
-	PC_EOD_OUT					=> pc_eod,
+	PC_DATA_OUT				=> pc_data,
+	PC_READY_IN				=> pc_ready,
+	PC_SOS_OUT				=> pc_sos,
+	PC_EOD_OUT				=> pc_eod,
 	PC_SUB_SIZE_OUT				=> pc_sub_size,
 	PC_TRIG_NR_OUT				=> pc_trig_nr,
 	PC_PADDING_OUT				=> pc_padding,
-	-- Debug
-	BSM_SAVE_OUT				=> ig_bsm_save,
-	BSM_LOAD_OUT				=> ig_bsm_load,
-	DBG_CTS_CTR_OUT				=> ig_cts_ctr,
-	DBG_REM_CTR_OUT				=> ig_rem_ctr,
-	DBG_SF_WCNT_OUT				=> ig_wcnt,
-	DBG_SF_RCNT_OUT				=> ig_rcnt,
-    DBG_SF_DATA_OUT				=> ig_data, 
-    DBG_SF_RD_EN_OUT			=> ig_rd_en,
-	DBG_SF_WR_EN_OUT			=> ig_wr_en,
-	DBG_SF_EMPTY_OUT			=> ig_empty,
-	DBG_SF_AEMPTY_OUT			=> ig_aempty,
-	DBG_SF_FULL_OUT				=> ig_full,
-	DBG_SF_AFULL_OUT			=> ig_afull,
-	--DEBUG_OUT					=> ig_debug
+	MONITOR_OUT(31 downto 0)                => monitor_sent,
+	MONITOR_OUT(63 downto 32)               => monitor_dropped,
+	MONITOR_OUT(95 downto 64)               => monitor_hr,
+	MONITOR_OUT(127 downto 96)              => monitor_sm,
+	MONITOR_OUT(159 downto 128)             => monitor_lr,
 	DEBUG_OUT(31 downto 0)                  => dbg_ipu2gbe1,
-	DEBUG_OUT(63 downto 32)                 => dbg_ipu2gbe2
-);      
+	DEBUG_OUT(63 downto 32)                 => dbg_ipu2gbe2,
+	DEBUG_OUT(95 downto 64)                 => dbg_ipu2gbe3,
+	DEBUG_OUT(127 downto 96)                => dbg_ipu2gbe4,
+	DEBUG_OUT(159 downto 128)               => dbg_ipu2gbe5,
+	DEBUG_OUT(191 downto 160)               => dbg_ipu2gbe6,
+	DEBUG_OUT(223 downto 192)               => dbg_ipu2gbe7,
+	DEBUG_OUT(255 downto 224)               => dbg_ipu2gbe8,
+	DEBUG_OUT(287 downto 256)               => dbg_ipu2gbe9,
+	DEBUG_OUT(319 downto 288)               => dbg_ipu2gbe10,
+	DEBUG_OUT(351 downto 320)               => dbg_ipu2gbe11,
+	DEBUG_OUT(383 downto 352)               => dbg_ipu2gbe12
+);
 
 -- Second stage: Packet constructor
 PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr
@@ -689,30 +660,6 @@ port map(
 	FC_FLAGS_OFFSET_OUT		=> fc_flags_offset,
 	FC_SOD_OUT				=> fc_sod,
 	FC_EOD_OUT				=> fc_eod,
-	-- debug ports
-	BSM_CONSTR_OUT			=> pc_bsm_constr,
-	BSM_LOAD_OUT			=> pc_bsm_load,
-	BSM_SAVE_OUT			=> pc_bsm_save,
-	DBG_SHF_EMPTY			=> pc_shf_empty,
-	DBG_SHF_FULL			=> pc_shf_full,
-	DBG_SHF_WR_EN			=> pc_shf_wr_en,
-	DBG_SHF_RD_EN			=> pc_shf_rd_en,
-	DBG_SHF_Q				=> pc_shf_q,
-	DBG_DF_EMPTY			=> pc_df_empty,
-	DBG_DF_FULL				=> pc_df_full,
-	DBG_DF_WR_EN			=> pc_df_wr_en,
-	DBG_DF_RD_EN			=> pc_df_rd_en,
-    DBG_DF_Q				=> pc_df_q,
-    DBG_ALL_CTR				=> pc_all_ctr,
-	DBG_SUB_CTR				=> pc_sub_ctr,
-	DBG_MY_CTR              => open,
-	DBG_BYTES_LOADED		=> pc_bytes_loaded,
-	DBG_SIZE_LEFT			=> pc_size_left,
-	DBG_SUB_SIZE_TO_SAVE	=> pc_sub_size_to_save,
-	DBG_SUB_SIZE_LOADED		=> pc_sub_size_loaded,
-	DBG_SUB_BYTES_LOADED	=> pc_sub_bytes_loaded,
-	DBG_QUEUE_SIZE			=> pc_queue_size,
-	DBG_ACT_QUEUE_SIZE		=> pc_act_queue_size,
 	DEBUG_OUT(31 downto 0)		=> dbg_pc1,
 	DEBUG_OUT(63 downto 32)         => dbg_pc2
 );
@@ -1066,6 +1013,35 @@ sim_gen: if (DO_SIMULATION = 1) generate
 
 end generate sim_gen;
 
+-- gk 28.07.10
+BYTES_SENT_CTR_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			bytes_sent_ctr <= (others => '0');
+		elsif (fc_wr_en = '1') then
+			bytes_sent_ctr <= bytes_sent_ctr + x"1";
+		end if;
+	end if;
+end process BYTES_SENT_CTR_PROC;
+
+
+-- reset_fifo <= '1' when RESET = '1' or pc_sos = '1' else '0';
+-- 
+-- debug_fifo : fifo_4096x9
+-- port map( 
+-- 	Data(7 downto 0)    => pcs_txd,
+-- 	Data(8) => '0',
+-- 	WrClock	=> serdes_clk_125,
+-- 	RdClock	=> CLK,
+-- 	WrEn	=> pcs_tx_en,
+-- 	RdEn	=> dbg_rd_en,
+-- 	Reset	=> reset_fifo,
+-- 	RPReset	=> reset_fifo,
+-- 	Q	=> dbg_q(8 downto 0),
+-- 	Empty	=> open,
+-- 	Full	=> open
+-- );
 
 ------------------------------------------------------------------------------------------------
 ------------------------------------------------------------------------------------------------
@@ -1077,91 +1053,6 @@ end generate sim_gen;
 --***************
 analyzer_debug <= pcs_stat_debug;
 
--- Interconnection signals
-IG_CTS_CTR_TST           <= ig_cts_ctr;
-IG_REM_CTR_TST           <= ig_rem_ctr;
-IG_BSM_LOAD_TST          <= ig_bsm_load;
-IG_BSM_SAVE_TST          <= ig_bsm_save;
-IG_DATA_TST              <= ig_data;
-IG_WCNT_TST              <= ig_wcnt;
-IG_RCNT_TST              <= ig_rcnt;
-IG_RD_EN_TST             <= ig_rd_en;
-IG_WR_EN_TST             <= ig_wr_en;
-IG_EMPTY_TST             <= ig_empty;
-IG_AEMPTY_TST            <= ig_aempty;
-IG_FULL_TST              <= ig_full;
-IG_AFULL_TST             <= ig_afull;
--- PacketConstructor signals
-PC_WR_EN_TST             <= pc_wr_en;
-PC_DATA_TST              <= pc_data;
-PC_READY_TST             <= pc_ready;
-PC_START_OF_SUB_TST      <= pc_sos;
-PC_END_OF_DATA_TST       <= pc_eod;
-PC_SUB_SIZE_TST          <= pc_sub_size;
-PC_TRIG_NR_TST           <= pc_trig_nr;
-PC_PADDING_TST           <= pc_padding;
-PC_DECODING_TST          <= pc_decoding;
-PC_EVENT_ID_TST          <= pc_event_id;
-PC_QUEUE_DEC_TST         <= pc_queue_dec;
-PC_BSM_CONSTR_TST        <= pc_bsm_constr;
-PC_BSM_LOAD_TST          <= pc_bsm_load;
-PC_BSM_SAVE_TST          <= pc_bsm_save;
-PC_SHF_EMPTY_TST         <= pc_shf_empty;
-PC_SHF_FULL_TST          <= pc_shf_full;
-PC_SHF_WR_EN_TST         <= pc_shf_wr_en;
-PC_SHF_RD_EN_TST         <= pc_shf_rd_en;
-PC_SHF_Q_TST             <= pc_shf_q;
-PC_DF_EMPTY_TST          <= pc_df_empty;
-PC_DF_FULL_TST           <= pc_df_full;
-PC_DF_WR_EN_TST          <= pc_df_wr_en;
-PC_DF_RD_EN_TST          <= pc_df_rd_en;
-PC_DF_Q_TST              <= pc_df_q;
-PC_ALL_CTR_TST           <= pc_all_ctr;
-PC_SUB_CTR_TST           <= pc_sub_ctr;
-PC_BYTES_LOADED_TST      <= pc_bytes_loaded;
-PC_SIZE_LEFT_TST         <= pc_size_left;
-PC_SUB_SIZE_TO_SAVE_TST  <= pc_sub_size_to_save;
-PC_SUB_SIZE_LOADED_TST   <= pc_sub_size_loaded;
-PC_SUB_BYTES_LOADED_TST  <= pc_sub_bytes_loaded;
-PC_QUEUE_SIZE_TST        <= pc_queue_size;
-PC_ACT_QUEUE_SIZE_TST    <= pc_act_queue_size;
--- FrameConstructor signals
-FC_WR_EN_TST             <= fc_wr_en;
-FC_DATA_TST              <= fc_data;
-FC_SOD_TST               <= fc_sod;
-FC_EOD_TST               <= fc_eod;
-FC_IP_SIZE_TST           <= fc_ip_size;
-FC_UDP_SIZE_TST          <= fc_udp_size;
-FC_H_READY_TST           <= fc_h_ready;
-FC_READY_TST             <= fc_ready;
-FC_IDENT_TST             <= fc_ident;
-FC_FLAGS_OFFSET_TST      <= fc_flags_offset;
-FC_BSM_CONSTR_TST        <= fc_bsm_constr;
-FC_BSM_TRANS_TST         <= fc_bsm_trans;
--- FrameTransmitter signals
-FT_TX_EMPTY_TST          <= ft_tx_empty;
-FT_DATA_TST              <= ft_data;  -- gk 04.05.10
-FT_START_OF_PACKET_TST   <= ft_start_of_packet;
-FT_BSM_INIT_TST          <= ft_bsm_init;
-FT_BSM_MAC_TST           <= ft_bsm_mac;
-FT_BSM_TRANS_TST         <= ft_bsm_trans;
--- MAC
-MAC_HADDR_TST            <= mac_haddr;
-MAC_HDATA_TST            <= mac_hdataout;
-MAC_HCS_TST              <= mac_hcs;
-MAC_HWRITE_TST           <= mac_hwrite;
-MAC_HREAD_TST            <= mac_hread;
-MAC_HREADY_TST           <= mac_hready;
-MAC_HDATA_EN_TST         <= mac_hdata_en;
-MAC_FIFOAVAIL_TST        <= mac_fifoavail;
-MAC_FIFOEOF_TST          <= mac_fifoeof;
-MAC_FIFOEMPTY_TST        <= mac_fifoempty;
-MAC_TX_DONE_TST          <= mac_tx_done;
-MAC_TX_READ_TST          <= mac_tx_read;
-PCS_AN_LP_ABILITY_TST    <= pcs_an_lp_ability;
-PCS_AN_COMPLETE_TST      <= pcs_an_complete;
-PCS_AN_PAGE_RX_TST       <= pcs_an_page_rx;
-
 -- Outputs
 FEE_READ_OUT             <= fee_read;
 
diff --git a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
index 628e05d..d9ece24 100755
--- a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
@@ -85,6 +85,7 @@ signal fpf_data             : std_logic_vector(7 downto 0);
 signal fpf_empty            : std_logic;
 signal fpf_full             : std_logic;
 signal fpf_wr_en            : std_logic;
+signal fpf_rd_en            : std_logic;
 signal fpf_q                : std_logic_vector(8 downto 0);
 signal ip_size              : std_logic_vector(15 downto 0);
 signal ip_checksum          : std_logic_vector(31 downto 0);
@@ -217,7 +218,6 @@ begin
 	end if;
 end process constructMachineProc;
 
-
 --find next state of construct machine
 constructMachine: process( constructCurrentState, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX )
 begin
@@ -314,7 +314,7 @@ begin
 		if (RESET = '1') or (constructCurrentState = IDLE) then
 			headers_int_counter <= 0;
 		else
-			if headers_int_counter = cur_max then
+			if (headers_int_counter = cur_max) then
 				headers_int_counter <= 0;
 			else
 				headers_int_counter <= headers_int_counter + 1;
@@ -380,6 +380,7 @@ begin
 	end case;
 end process fpfDataProc;
 
+
 readyFramesCtrProc: process( CLK )
 begin
 	if rising_edge(CLK) then
@@ -406,7 +407,6 @@ port map(
 	Full                => fpf_full
 );
 
-
 transferToRdClock : signal_sync
 	generic map(
 	  DEPTH => 2,
@@ -415,7 +415,7 @@ transferToRdClock : signal_sync
 	port map(
 	  RESET    => RESET,
 	  D_IN     => ready_frames_ctr,
-	  CLK0     => RD_CLK,
+	  CLK0     => RD_CLK, --CLK,
 	  CLK1     => RD_CLK,
 	  D_OUT    => ready_frames_ctr_q
 	  );
@@ -436,7 +436,7 @@ begin
 	case transmitCurrentState is
 		when T_IDLE =>
 			bsm_trans <= x"0";
-			if( sent_frames_ctr /= ready_frames_ctr_q ) then
+			if( (sent_frames_ctr /= ready_frames_ctr_q) ) then
 				transmitNextState <= T_LOAD;
 			else
 				transmitNextState <= T_IDLE;
@@ -469,7 +469,7 @@ begin
 	if rising_edge(RD_CLK) then
 		if   ( RESET = '1' ) then
 			ft_sop <= '0';
-		elsif( (transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q) ) then
+		elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then
 			ft_sop <= '1';
 		else
 			ft_sop <= '0';
@@ -495,7 +495,8 @@ debug(28)              <= fpf_full;
 debug(29)              <= fpf_empty;
 debug(30)              <= ready;
 debug(31)              <= headers_ready;
-debug(47 downto 32)    <= ready_frames_ctr;
+debug(47 downto 32)    <= ready_frames_ctr_q;
+debug(48)              <= '0';
 
 
 -- Output
diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd
index 4e76533..d09e4b0 100755
--- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd
@@ -21,7 +21,7 @@ port(
 	PC_END_OF_DATA_IN       : in    std_logic;
 	-- queue and subevent layer headers
 	PC_SUB_SIZE_IN          : in    std_logic_vector(31 downto 0); -- store and swap
-	PC_PADDING_IN           : in std_logic;  -- gk 29.03.10
+	PC_PADDING_IN           : in    std_logic;  -- gk 29.03.10
 	PC_DECODING_IN          : in    std_logic_vector(31 downto 0); -- swap
 	PC_EVENT_ID_IN          : in    std_logic_vector(31 downto 0); -- swap
 	PC_TRIG_NR_IN           : in    std_logic_vector(31 downto 0); -- store and swap!
@@ -39,47 +39,22 @@ port(
 	FC_FLAGS_OFFSET_OUT     : out   std_logic_vector(15 downto 0);
 	FC_SOD_OUT              : out   std_logic;
 	FC_EOD_OUT              : out   std_logic;
-	-- debug ports
-	BSM_CONSTR_OUT          : out   std_logic_vector(3 downto 0);
-	BSM_LOAD_OUT            : out   std_logic_vector(3 downto 0);
-	BSM_SAVE_OUT            : out   std_logic_vector(3 downto 0);
-	DBG_SHF_EMPTY           : out   std_logic;
-	DBG_SHF_FULL            : out   std_logic;
-	DBG_SHF_WR_EN           : out   std_logic;
-	DBG_SHF_RD_EN           : out   std_logic;
-	DBG_SHF_Q               : out   std_logic_vector(7 downto 0);
-	DBG_DF_EMPTY            : out   std_logic;
-	DBG_DF_FULL             : out   std_logic;
-	DBG_DF_WR_EN            : out   std_logic;
-	DBG_DF_RD_EN            : out   std_logic;
-	DBG_DF_Q                : out   std_logic_vector(7 downto 0);
-	DBG_ALL_CTR             : out   std_logic_vector(4 downto 0);
-	DBG_SUB_CTR             : out   std_logic_vector(4 downto 0);
-	DBG_MY_CTR              : out   std_logic_vector(1 downto 0);
-	DBG_BYTES_LOADED        : out   std_logic_vector(15 downto 0);
-	DBG_SIZE_LEFT           : out   std_logic_vector(31 downto 0);
-	DBG_SUB_SIZE_TO_SAVE    : out   std_logic_vector(31 downto 0);
-	DBG_SUB_SIZE_LOADED     : out   std_logic_vector(31 downto 0);
-	DBG_SUB_BYTES_LOADED    : out   std_logic_vector(31 downto 0);
-	DBG_QUEUE_SIZE          : out   std_logic_vector(31 downto 0);
-	DBG_ACT_QUEUE_SIZE      : out   std_logic_vector(31 downto 0);
 	DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_packet_constr;
 
 architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is
 
--- FIFO for packet payload data
-component fifo_64kx8
+component fifo_64kx9
 port (
-	Data        : in  std_logic_vector(7 downto 0); 
+	Data        : in  std_logic_vector(8 downto 0); 
 	WrClock     : in  std_logic; 
 	RdClock     : in  std_logic; 
 	WrEn        : in  std_logic; 
 	RdEn        : in  std_logic; 
 	Reset       : in  std_logic; 
 	RPReset     : in  std_logic; 
-	Q           : out  std_logic_vector(7 downto 0); 
+	Q           : out  std_logic_vector(8 downto 0); 
 	Empty       : out  std_logic; 
 	Full        : out  std_logic
 );
@@ -158,13 +133,16 @@ signal pc_ready             : std_logic;
 
 signal pc_sub_size          : std_logic_vector(31 downto 0);
 signal pc_trig_nr           : std_logic_vector(31 downto 0);
-signal pc_padding           : std_logic; -- gk 29.03.10
 signal rst_after_sub_comb   : std_logic;  -- gk 08.04.10
 signal rst_after_sub        : std_logic;  -- gk 08.04.10
 signal load_int_ctr         : integer range 0 to 3;  -- gk 08.04.10
 signal delay_ctr            : std_logic_vector(31 downto 0);  -- gk 28.04.10
 signal ticks_ctr            : std_logic_vector(7 downto 0);  -- gk 28.04.10
 
+-- gk 26.07.10
+signal load_eod             : std_logic;
+signal load_eod_q           : std_logic;
+
 begin
 
 -- Fakes
@@ -177,8 +155,6 @@ all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for de
 sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging
 my_ctr  <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging
 
-pc_padding <= PC_PADDING_IN; -- gk 29.03.10  used to correct the subevent size written to subevent headers
-
 -- Fixed numbers
 
 --max_frame_size <= x"0578"; -- 1400 
@@ -202,19 +178,34 @@ begin
 end process;
 
 -- Data FIFO for incoming packet data from IPU buffer
-DATA_FIFO : fifo_64kx8
+-- gk 26.07.10
+DATA_FIFO : fifo_64kx9
 port map(
-	Data        =>  PC_DATA_IN,
+	Data(7 downto 0) => PC_DATA_IN,
+	Data(8)          => PC_END_OF_DATA_IN,
 	WrClock     =>  CLK,
 	RdClock     =>  CLK,
 	WrEn        =>  df_wr_en,
 	RdEn        =>  df_rd_en,
 	Reset       =>  RESET,
 	RPReset     =>  RESET,
-	Q           =>  df_q,
+	Q(7 downto 0) =>  df_q,
+	Q(8)          => load_eod,
 	Empty       =>  df_empty,
 	Full        =>  df_full
 );
+
+LOAD_EOD_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			load_eod_q <= '0';
+		else
+			load_eod_q <= load_eod;
+		end if;
+	end if;
+end process LOAD_EOD_PROC;
+
 -- Write enable for the data FIFO
 -- !!!combinatorial signal!!!
 -- could be avoided as IPU2GBE does only send data in case of PC_READY.
@@ -271,136 +262,14 @@ begin
 	end case;
 end process constructMachine;
 
-
---***********************
---      SUBEVENT HEADERS WRITE AND READ
---***********************
-
-SUBEVENT_HEADERS_FIFO : fifo_2048x8
-port map(
-	Data        =>  shf_data,
-	WrClock     =>  CLK,
-	RdClock     =>  CLK,
-	WrEn        =>  shf_wr_en,
-	RdEn        =>  shf_rd_en,
-	Reset       =>  RESET,
-	RPReset     =>  RESET,
-	Q           =>  shf_q,
-	Empty       =>  shf_empty,
-	Full        =>  shf_full
-);
-
--- write enable for SHF 
-shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))
-				 else '0';
-
--- data multiplexing for SHF (convert 32bit LWs to 8bit)
--- CHANGED. 
--- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.
-shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, 
-					  pc_trig_nr, my_int_ctr, fc_data)
-begin
-	case saveSubCurrentState is
-		when SIDLE          =>  shf_data <= x"ac";
-		when SAVE_SIZE      =>  shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
-		when SAVE_DECODING  =>  shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
-		when SAVE_ID        =>  shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
-		when SAVE_TRIG_NR   =>  shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
-		when SAVE_TERM      =>  shf_data <= fc_data;
-		when others         =>  shf_data <= x"00";
-	end case;
-end process shfDataProc;
-
-saveSubMachineProc : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if (RESET = '1') then
-			saveSubCurrentState <= SIDLE;
-		else
-			saveSubCurrentState <= saveSubNextState;
-		end if;
-	end if;
-end process saveSubMachineProc;
-
-saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, FC_H_READY_IN)
-begin
-	case saveSubCurrentState is
-		when SIDLE =>
-			save_state <= x"0";
-			if (PC_START_OF_SUB_IN = '1') then
-				saveSubNextState <= SAVE_SIZE;
-			-- this branch is dangerous!
-			elsif (loadCurrentState = WAIT_FOR_FC) and (FC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len
-				saveSubNextState <= SAVE_TERM;
-			else
-				saveSubNextState <= SIDLE;
-			end if;
-		when SAVE_SIZE =>
-			save_state <= x"1";
-			if (sub_int_ctr = 3) then
-				saveSubNextState <= SAVE_DECODING;
-			else
-				saveSubNextState <= SAVE_SIZE;
-			end if;
-		when SAVE_DECODING =>
-			save_state <= x"2";
-			if (sub_int_ctr = 3) then
-				saveSubNextState <= SAVE_ID;
-			else
-				saveSubNextState <= SAVE_DECODING;
-			end if;
-		when SAVE_ID =>
-			save_state <= x"3";
-			if (sub_int_ctr = 3) then
-				saveSubNextState <= SAVE_TRIG_NR;
-			else
-				saveSubNextState <= SAVE_ID;
-			end if;
-		when SAVE_TRIG_NR =>
-			save_state <= x"4";
-			if (sub_int_ctr = 3) then
-				saveSubNextState <= SIDLE;
-			else
-				saveSubNextState <= SAVE_TRIG_NR;
-			end if;
-		when SAVE_TERM =>
-			save_state <= x"5";
-			if (sub_int_ctr = 31) then
-				saveSubNextState <= SIDLE;
-			else
-				saveSubNextState <= SAVE_TERM;
-			end if;
-		when others =>
-			save_state <= x"f";
-			saveSubNextState <= SIDLE;
-	end case;
-end process;
-
--- This counter is used for breaking down 32bit information words into 8bit bytes for 
--- storing them in the SHF.
--- It is also used for the termination 32byte sequence.
-subIntProc: process( CLK )
-begin
-	if rising_edge(CLK) then
-		if (RESET = '1') or (saveSubCurrentState = SIDLE) then
-			sub_int_ctr <= 0;
-		elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then
-			sub_int_ctr <= 0;
-		elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then
-			sub_int_ctr <= 0;
-		elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then
-			sub_int_ctr <= sub_int_ctr + 1;
-		end if;
-	end if;
-end process subIntProc;
-
 --***********************
 --      SIZE COUNTERS FOR SAVING SIDE
 --***********************
 
 -- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size
 -- that's why they are removed if pc_padding flag is asserted
-sub_size_to_save <= x"10" + pc_sub_size when pc_padding = '0' else x"c" + pc_sub_size; -- subevent headers + data
+sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')
+			else (x"c" + pc_sub_size); -- subevent headers + data
 
 -- BUG HERE BUG HERE BUG HERE BUG HERE
 -- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents
@@ -433,7 +302,7 @@ end process loadMachineProc;
 
 loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,
 					  sub_bytes_loaded, sub_size_loaded, size_left, FC_H_READY_IN, max_frame_size, 
-					  bytes_loaded, divide_position, PC_DELAY_IN, delay_ctr)
+					  bytes_loaded, divide_position, PC_DELAY_IN, delay_ctr, load_eod_q)
 begin
 	case loadCurrentState is
 		when LIDLE =>
@@ -480,12 +349,21 @@ begin
 			load_state <= x"6";
 			if (bytes_loaded = max_frame_size - 1) then
 				loadNextState <= DIVIDE;
-			elsif (sub_bytes_loaded = sub_size_loaded) then  -- if all subevent bytes are loaded
-				if (size_left = x"00000021") then  -- and there is no more data, only termination left
-					loadNextState <= LOAD_TERM;  -- add termination and close packet
-				else -- there is more data in fifo
-					loadNextState <= LOAD_SUB;  -- add another subevent
-				end if;
+			-- gk 26.07.10
+			-- close packet after one event loaded
+			elsif (load_eod_q = '1') then
+				loadNextState <= LOAD_TERM;
+-- 			elsif (sub_bytes_loaded = sub_size_loaded) then  -- if all subevent bytes are loaded
+-- 				if (size_left = x"00000021") then  -- and there is no more data, only termination left
+-- 					-- gk 21.07.10
+-- 					if (PC_SKIP_TERM_IN = '0') then
+-- 						loadNextState <= LOAD_TERM;  -- add termination and close packet
+-- 					else
+-- 						loadNextState <= CLEANUP;
+-- 					end if;
+-- 				else -- there is more data in fifo
+-- 					loadNextState <= LOAD_SUB;  -- add another subevent
+-- 				end if;
 			else
 				loadNextState <= LOAD_DATA;
 			end if;
@@ -533,31 +411,6 @@ begin
 	end case;
 end process loadMachine;
 
--- delay counters
--- gk 28.04.10
-DELAY_CTR_PROC : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if ((RESET = '1') or (loadCurrentState = LIDLE)) then
-			delay_ctr <= PC_DELAY_IN;
-		elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then
-			delay_ctr <= delay_ctr - x"1";
-		end if;
-	end if;
-end process DELAY_CTR_PROC;
-
--- gk 28.04.10
-TICKS_CTR_PROC : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then
-			ticks_ctr <= x"00";
-		elsif (loadCurrentState = DELAY) then
-			ticks_ctr <= ticks_ctr + x"1";
-		end if;
-	end if;
-end process TICKS_CTR_PROC;
-
 dividePositionProc : process(CLK)
 begin
 	if rising_edge(CLK) then
@@ -567,12 +420,17 @@ begin
 			if (loadCurrentState = LIDLE) then
 				divide_position <= "00";
 			elsif (loadCurrentState = LOAD_DATA) then
-				if (sub_bytes_loaded = sub_size_loaded) and (size_left = x"00000021") then
+				-- gk 26.07.10
+				if (load_eod_q = '1') then -- if termination is about to be loaded divide on term
 					divide_position <= "11";
-				elsif  (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021") then
-					divide_position <= "01";
 				else
-					divide_position <= "00";
+					divide_position <= "00"; -- still data loaded divide on data
+-- 				if (sub_bytes_loaded = sub_size_loaded) and (size_left = x"00000021") then
+-- 					divide_position <= "11";
+-- 				elsif  (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021") then
+-- 					divide_position <= "01";
+-- 				else
+-- 					divide_position <= "00";
 				end if;
 			elsif (loadCurrentState = LOAD_SUB) then
 				if (all_int_ctr = 15) then
@@ -653,8 +511,11 @@ begin
 --          df_rd_en <= '0';
 		if (bytes_loaded = max_frame_size - x"1") then
 			df_rd_en <= '0';
-		elsif (sub_bytes_loaded = sub_size_loaded) then
+		-- gk 26.07.10
+		elsif (load_eod = '1') or (load_eod_q = '1') then
 			df_rd_en <= '0';
+--		elsif (sub_bytes_loaded = sub_size_loaded) then
+--			df_rd_en <= '0';
 		else
 			df_rd_en <= '1';
 		end if;
@@ -715,6 +576,31 @@ begin
 	end case;
 end process fcDataProc;
 
+-- delay counters
+-- gk 28.04.10
+DELAY_CTR_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if ((RESET = '1') or (loadCurrentState = LIDLE)) then
+			delay_ctr <= PC_DELAY_IN;
+		elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then
+			delay_ctr <= delay_ctr - x"1";
+		end if;
+	end if;
+end process DELAY_CTR_PROC;
+
+-- gk 28.04.10
+TICKS_CTR_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then
+			ticks_ctr <= x"00";
+		elsif (loadCurrentState = DELAY) then
+			ticks_ctr <= ticks_ctr + x"1";
+		end if;
+	end if;
+end process TICKS_CTR_PROC;
+
 
 --***********************
 --      SIZE COUNTERS FOR LOADING SIDE
@@ -724,7 +610,7 @@ queue_size_temp <= queue_size - x"20"; -- size of data without termination
 
 -- gk 08.04.10
 rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or
-			((loadCurrentState = LOAD_DATA) and (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021"))
+			((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) 
 			else '0';
 
 -- gk 08.04.10
@@ -772,7 +658,7 @@ end process subSizeLoadedProc;
 subBytesLoadedProc : process(CLK)
 begin
 	if rising_edge(CLK) then
-		if (RESET = '1') or (loadCurrentState = LIDLE) or (sub_bytes_loaded = sub_size_loaded) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then  -- gk 08.04.10
+		if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then   -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10
 			sub_bytes_loaded <= x"00000011";  -- subevent headers doesnt count
 		elsif (loadCurrentState = LOAD_DATA) then
 			sub_bytes_loaded <= sub_bytes_loaded + x"1";
@@ -917,6 +803,130 @@ fcUDPSizeProc : process(CLK)
 end process fcUDPSizeProc;
 
 
+--***********************
+--      SUBEVENT HEADERS WRITE AND READ
+--***********************
+
+SUBEVENT_HEADERS_FIFO : fifo_2048x8
+port map(
+	Data        =>  shf_data,
+	WrClock     =>  CLK,
+	RdClock     =>  CLK,
+	WrEn        =>  shf_wr_en,
+	RdEn        =>  shf_rd_en,
+	Reset       =>  RESET,
+	RPReset     =>  RESET,
+	Q           =>  shf_q,
+	Empty       =>  shf_empty,
+	Full        =>  shf_full
+);
+
+-- write enable for SHF 
+shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))
+				 else '0';
+
+-- data multiplexing for SHF (convert 32bit LWs to 8bit)
+-- CHANGED. 
+-- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.
+shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, 
+					  pc_trig_nr, my_int_ctr, fc_data)
+begin
+	case saveSubCurrentState is
+		when SIDLE          =>  shf_data <= x"ac";
+		when SAVE_SIZE      =>  shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
+		when SAVE_DECODING  =>  shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
+		when SAVE_ID        =>  shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
+		when SAVE_TRIG_NR   =>  shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
+		when SAVE_TERM      =>  shf_data <= fc_data;
+		when others         =>  shf_data <= x"00";
+	end case;
+end process shfDataProc;
+
+saveSubMachineProc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			saveSubCurrentState <= SIDLE;
+		else
+			saveSubCurrentState <= saveSubNextState;
+		end if;
+	end if;
+end process saveSubMachineProc;
+
+saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, FC_H_READY_IN)
+begin
+	case saveSubCurrentState is
+		when SIDLE =>
+			save_state <= x"0";
+			if (PC_START_OF_SUB_IN = '1') then
+				saveSubNextState <= SAVE_SIZE;
+			-- this branch is dangerous!
+			elsif (loadCurrentState = WAIT_FOR_FC) and (FC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len
+				saveSubNextState <= SAVE_TERM;
+			else
+				saveSubNextState <= SIDLE;
+			end if;
+		when SAVE_SIZE =>
+			save_state <= x"1";
+			if (sub_int_ctr = 3) then
+				saveSubNextState <= SAVE_DECODING;
+			else
+				saveSubNextState <= SAVE_SIZE;
+			end if;
+		when SAVE_DECODING =>
+			save_state <= x"2";
+			if (sub_int_ctr = 3) then
+				saveSubNextState <= SAVE_ID;
+			else
+				saveSubNextState <= SAVE_DECODING;
+			end if;
+		when SAVE_ID =>
+			save_state <= x"3";
+			if (sub_int_ctr = 3) then
+				saveSubNextState <= SAVE_TRIG_NR;
+			else
+				saveSubNextState <= SAVE_ID;
+			end if;
+		when SAVE_TRIG_NR =>
+			save_state <= x"4";
+			if (sub_int_ctr = 3) then
+				saveSubNextState <= SIDLE;
+			else
+				saveSubNextState <= SAVE_TRIG_NR;
+			end if;
+		when SAVE_TERM =>
+			save_state <= x"5";
+			if (sub_int_ctr = 31) then
+				saveSubNextState <= SIDLE;
+			else
+				saveSubNextState <= SAVE_TERM;
+			end if;
+		when others =>
+			save_state <= x"f";
+			saveSubNextState <= SIDLE;
+	end case;
+end process;
+
+-- This counter is used for breaking down 32bit information words into 8bit bytes for 
+-- storing them in the SHF.
+-- It is also used for the termination 32byte sequence.
+subIntProc: process( CLK )
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') or (saveSubCurrentState = SIDLE) then
+			sub_int_ctr <= 0;
+		elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then
+			sub_int_ctr <= 0;
+		elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then
+			sub_int_ctr <= 0;
+		elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then
+			sub_int_ctr <= sub_int_ctr + 1;
+		end if;
+	end if;
+end process subIntProc;
+
+
+
 debug(3 downto 0)             <= constr_state;
 debug(7 downto 4)             <= save_state;
 debug(11 downto 8)            <= load_state;
@@ -941,29 +951,6 @@ FC_IDENT_OUT(7 downto 0)      <= fc_ident(15 downto 8);
 FC_FLAGS_OFFSET_OUT           <= fc_flags_offset;
 FC_SOD_OUT                    <= fc_sod;
 FC_EOD_OUT                    <= fc_eod;
-BSM_CONSTR_OUT                <= constr_state;
-BSM_LOAD_OUT                  <= load_state;
-BSM_SAVE_OUT                  <= save_state;
-DBG_SHF_EMPTY                 <= shf_empty;
-DBG_SHF_FULL                  <= shf_full;
-DBG_SHF_WR_EN                 <= shf_wr_en;
-DBG_SHF_RD_EN                 <= shf_rd_en;
-DBG_SHF_Q                     <= shf_q;
-DBG_DF_EMPTY                  <= df_empty;
-DBG_DF_FULL                   <= df_full;
-DBG_DF_WR_EN                  <= df_wr_en;
-DBG_DF_RD_EN                  <= df_rd_en;
-DBG_DF_Q                      <= df_q;
-DBG_ALL_CTR                   <= all_ctr;
-DBG_SUB_CTR                   <= sub_ctr;
-DBG_MY_CTR                    <= my_ctr;
-DBG_BYTES_LOADED              <= bytes_loaded;
-DBG_SIZE_LEFT                 <= size_left;
-DBG_SUB_SIZE_TO_SAVE          <= sub_size_to_save;
-DBG_SUB_SIZE_LOADED           <= sub_size_loaded;
-DBG_SUB_BYTES_LOADED          <= sub_bytes_loaded;
-DBG_QUEUE_SIZE                <= queue_size;
-DBG_ACT_QUEUE_SIZE            <= actual_queue_size;
 
 DEBUG_OUT                     <= debug;
 
diff --git a/gbe_ecp2m/trb_net16_gbe_setup.vhd b/gbe_ecp2m/trb_net16_gbe_setup.vhd
index a44c796..f852797 100644
--- a/gbe_ecp2m/trb_net16_gbe_setup.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_setup.vhd
@@ -7,7 +7,7 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb_net16_hub_func.all;
-use work.version.all;
+--use work.version.all;
 
 
 entity gbe_setup is
@@ -32,6 +32,7 @@ port(
 	GBE_SUBEVENT_DEC_OUT      : out std_logic_vector(31 downto 0);
 	GBE_QUEUE_DEC_OUT         : out std_logic_vector(31 downto 0);
 	GBE_MAX_PACKET_OUT        : out std_logic_vector(31 downto 0);
+	GBE_MIN_PACKET_OUT        : out std_logic_vector(31 downto 0);
 	GBE_MAX_FRAME_OUT         : out std_logic_vector(15 downto 0);
 	GBE_USE_GBE_OUT           : out std_logic;
 	GBE_USE_TRBNET_OUT        : out std_logic;
@@ -39,15 +40,35 @@ port(
 	GBE_READOUT_CTR_OUT       : out std_logic_vector(23 downto 0);  -- gk 26.04.10
 	GBE_READOUT_CTR_VALID_OUT : out std_logic;  -- gk 26.04.10
 	GBE_DELAY_OUT             : out std_logic_vector(31 downto 0);
+	GBE_ALLOW_LARGE_OUT       : out std_logic;
+	-- gk 28.07.10
+	MONITOR_BYTES_IN          : in std_logic_vector(31 downto 0);
+	MONITOR_SENT_IN           : in std_logic_vector(31 downto 0);
+	MONITOR_DROPPED_IN        : in std_logic_vector(31 downto 0);
+	MONITOR_SM_IN             : in std_logic_vector(31 downto 0);
+	MONITOR_LR_IN             : in std_logic_vector(31 downto 0);
+	MONITOR_HDR_IN            : in std_logic_vector(31 downto 0);	
 	-- gk 01.06.10
 	DBG_IPU2GBE1_IN          : in std_logic_vector(31 downto 0);
 	DBG_IPU2GBE2_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE3_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE4_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE5_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE6_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE7_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE8_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE9_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE10_IN         : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE11_IN         : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE12_IN         : in std_logic_vector(31 downto 0);
 	DBG_PC1_IN               : in std_logic_vector(31 downto 0);
 	DBG_PC2_IN               : in std_logic_vector(31 downto 0);
 	DBG_FC1_IN               : in std_logic_vector(31 downto 0);
 	DBG_FC2_IN               : in std_logic_vector(31 downto 0);
 	DBG_FT1_IN               : in std_logic_vector(31 downto 0);
-	DBG_FT2_IN               : in std_logic_vector(31 downto 0)
+	DBG_FT2_IN               : in std_logic_vector(31 downto 0);
+	DBG_FIFO_RD_EN_OUT        : out std_logic;
+	DBG_FIFO_Q_IN             : in std_logic_vector(15 downto 0)
 );
 end entity;
 
@@ -59,6 +80,7 @@ signal subevent_id       : std_logic_vector(31 downto 0);
 signal subevent_dec      : std_logic_vector(31 downto 0);
 signal queue_dec         : std_logic_vector(31 downto 0);
 signal max_packet        : std_logic_vector(31 downto 0);
+signal min_packet        : std_logic_vector(31 downto 0);  -- gk 07.20.10
 signal max_frame         : std_logic_vector(15 downto 0);
 signal use_gbe           : std_logic;
 signal use_trbnet        : std_logic;
@@ -69,6 +91,7 @@ signal ack               : std_logic;  -- gk 26.04.10
 signal ack_q             : std_logic;  -- gk 26.04.10
 signal data_out          : std_logic_vector(31 downto 0);  -- gk 26.04.10
 signal delay             : std_logic_vector(31 downto 0);  -- gk 28.04.10
+signal allow_large       : std_logic;  -- gk 21.07.10
 
 begin
 
@@ -79,6 +102,7 @@ begin
 		GBE_SUBEVENT_DEC_OUT      <= subevent_dec;
 		GBE_QUEUE_DEC_OUT         <= queue_dec;
 		GBE_MAX_PACKET_OUT        <= max_packet;
+		GBE_MIN_PACKET_OUT        <= min_packet;
 		GBE_MAX_FRAME_OUT         <= max_frame;
 		GBE_USE_GBE_OUT           <= use_gbe;
 		GBE_USE_TRBNET_OUT        <= use_trbnet;
@@ -89,6 +113,7 @@ begin
 		ack_q                     <= ack; -- gk 26.04.10
 		BUS_DATA_OUT              <= data_out;  -- gk 26.04.10
 		GBE_DELAY_OUT             <= delay; -- gk 28.04.10
+		GBE_ALLOW_LARGE_OUT       <= allow_large;  -- gk 21.07.10
 	end if;
 end process OUT_PROC;
 
@@ -108,20 +133,25 @@ end process ACK_PROC;
 
 WRITE_PROC : process(CLK)
 begin
+	DBG_FIFO_RD_EN_OUT <= '0';
+
 	if rising_edge(CLK) then
 		if ( (RESET = '1') or (reset_values = '1') ) then
 			subevent_id       <= x"0000_00cf";
 			subevent_dec      <= x"0002_0001";
 			queue_dec         <= x"0003_0062";
-			max_packet        <= x"0000_fde8"; --x"0000_fde8"; -- tester
+			max_packet        <= x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester
+			min_packet        <= x"0000_0008"; -- gk 20.07.10
 			max_frame         <= x"0578";
 			use_gbe           <= '1';
 			use_trbnet        <= '0';
 			use_multievents   <= '0';
 			reset_values      <= '0';
-			readout_ctr       <= x"00_0000"; --x"ff_ffff";  -- gk 26.04.10  -- gk 07.06.10 corrected bug found by Sergey
+			readout_ctr       <= x"00_0000";  -- gk 26.04.10  -- gk 07.06.10 corrected bug found by Sergey
 			readout_ctr_valid <= '0';  -- gk 26.04.10
 			delay             <= x"0000_0000"; -- gk 28.04.10
+			DBG_FIFO_RD_EN_OUT <= '0';
+			allow_large       <= '0';  -- gk 21.07.10
 
 		elsif (BUS_WRITE_EN_IN = '1') then
 			case BUS_ADDR_IN is
@@ -171,6 +201,21 @@ begin
 				when x"09" =>
 					delay <= BUS_DATA_IN;
 
+				when x"0a" =>
+					DBG_FIFO_RD_EN_OUT <= '1';
+
+				-- gk 20.07.10
+				when x"0b" =>
+					min_packet <= BUS_DATA_IN;
+
+				-- gk 21.07.10
+				when x"0c" =>
+					if (BUS_DATA_IN = x"0000_0000") then
+						allow_large <= '0';
+					else
+						allow_large <= '1';
+					end if;
+
 				when x"ff" =>
 					if (BUS_DATA_IN = x"ffff_ffff") then
 						reset_values <= '1';
@@ -183,6 +228,7 @@ begin
 					subevent_dec      <= subevent_dec;
 					queue_dec         <= queue_dec;
 					max_packet        <= max_packet;
+					min_packet        <= min_packet;
 					max_frame         <= max_frame;
 					use_gbe           <= use_gbe;
 					use_trbnet        <= use_trbnet;
@@ -191,6 +237,8 @@ begin
 					readout_ctr       <= readout_ctr;  -- gk 26.04.10
 					readout_ctr_valid <= readout_ctr_valid;  -- gk 26.04.10
 					delay             <= delay; -- gk 28.04.10
+					DBG_FIFO_RD_EN_OUT <= '0';
+					allow_large       <= allow_large;
 			end case;
 		else
 			reset_values <= '0';
@@ -251,6 +299,17 @@ begin
 				when x"09" =>
 					data_out <= delay;
 
+				when x"0b" =>
+					data_out <= min_packet;
+
+				-- gk 21.07.10
+				when x"0c" =>
+					if (allow_large = '0') then
+						data_out <= x"0000_0000";
+					else
+						data_out <= x"0000_0001";
+					end if;
+
 				-- gk 01.06.10
 				when x"e0" =>
 					data_out <= DBG_IPU2GBE1_IN;
@@ -276,6 +335,58 @@ begin
 				when x"e7" =>
 					data_out <= DBG_FT2_IN;
 
+				when x"e8" =>
+					data_out(15 downto 0) <= DBG_FIFO_Q_IN;
+					data_out(31 downto 16) <= (others => '0');
+
+				when x"e9" =>
+					data_out <= DBG_IPU2GBE3_IN;
+
+				when x"ea" =>
+					data_out <= DBG_IPU2GBE4_IN;
+
+				when x"eb" =>
+					data_out <= DBG_IPU2GBE5_IN;
+
+				when x"ec" =>
+					data_out <= DBG_IPU2GBE6_IN;
+
+				when x"ed" =>
+					data_out <= DBG_IPU2GBE7_IN;
+
+				when x"ee" =>
+					data_out <= DBG_IPU2GBE8_IN;
+
+				when x"ef" =>
+					data_out <= DBG_IPU2GBE9_IN;
+
+				when x"f0" =>
+					data_out <= DBG_IPU2GBE10_IN;
+
+				when x"f1" =>
+					data_out <= DBG_IPU2GBE11_IN;
+
+				when x"f2" =>
+					data_out <= DBG_IPU2GBE12_IN;
+
+				when x"f3" =>
+					data_out <= MONITOR_BYTES_IN;
+
+				when x"f4" =>
+					data_out <= MONITOR_SENT_IN;
+
+				when x"f5" =>
+					data_out <= MONITOR_DROPPED_IN;
+
+				when x"f6" =>
+					data_out <= MONITOR_SM_IN;
+
+				when x"f7" =>
+					data_out <= MONITOR_LR_IN;
+
+				when x"f8" =>
+					data_out <= MONITOR_HDR_IN;
+
 				when others =>
 					data_out <= (others => '0');
 			end case;
diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd
index 096acb0..0755d2c 100755
--- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd
+++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd
@@ -1,1043 +1,1278 @@
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-
-entity trb_net16_ipu2gbe is
-port( 
-	CLK                         : in    std_logic;
-	RESET                       : in    std_logic;
-	-- IPU interface directed toward the CTS
-	CTS_NUMBER_IN               : in    std_logic_vector (15 downto 0);
-	CTS_CODE_IN                 : in    std_logic_vector (7  downto 0);
-	CTS_INFORMATION_IN          : in    std_logic_vector (7  downto 0);
-	CTS_READOUT_TYPE_IN         : in    std_logic_vector (3  downto 0);
-	CTS_START_READOUT_IN        : in    std_logic;
-	CTS_READ_IN                 : in    std_logic;
-	CTS_DATA_OUT                : out   std_logic_vector (31 downto 0);
-	CTS_DATAREADY_OUT           : out   std_logic;
-	CTS_READOUT_FINISHED_OUT    : out   std_logic;      --no more data, end transfer, send TRM
-	CTS_LENGTH_OUT              : out   std_logic_vector (15 downto 0);
-	CTS_ERROR_PATTERN_OUT       : out   std_logic_vector (31 downto 0);
-	-- Data from Frontends
-	FEE_DATA_IN                 : in    std_logic_vector (15 downto 0);
-	FEE_DATAREADY_IN            : in    std_logic;
-	FEE_READ_OUT                : out   std_logic;
-	FEE_BUSY_IN                 : in    std_logic;
-	FEE_STATUS_BITS_IN          : in    std_logic_vector (31 downto 0);
-	-- slow control interface
-	START_CONFIG_OUT			: out	std_logic; -- reconfigure MACs/IPs/ports/packet size
-	BANK_SELECT_OUT				: out	std_logic_vector(3 downto 0); -- configuration page address
-	CONFIG_DONE_IN				: in	std_logic; -- configuration finished
-	DATA_GBE_ENABLE_IN			: in	std_logic; -- IPU data is forwarded to GbE
-	DATA_IPU_ENABLE_IN			: in	std_logic; -- IPU data is forwarded to CTS / TRBnet
-	MULTI_EVT_ENABLE_IN			: in	std_logic; -- enable multi event packets
-	MAX_MESSAGE_SIZE_IN			: in	std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue  -- gk 08.04.10
-	READOUT_CTR_IN				: in	std_logic_vector(23 downto 0); -- gk 26.04.10
-	READOUT_CTR_VALID_IN			: in	std_logic; -- gk 26.04.10
-	-- PacketConstructor interface
-	PC_WR_EN_OUT                : out   std_logic;
-	PC_DATA_OUT                 : out   std_logic_vector (7 downto 0);
-	PC_READY_IN                 : in    std_logic;
-	PC_SOS_OUT                  : out   std_logic;
-	PC_EOD_OUT                  : out   std_logic;
-	PC_SUB_SIZE_OUT             : out   std_logic_vector(31 downto 0);
-	PC_TRIG_NR_OUT              : out   std_logic_vector(31 downto 0);
-	PC_PADDING_OUT              : out   std_logic;
-	-- Debug
-	BSM_SAVE_OUT                : out   std_logic_vector(3 downto 0);
-	BSM_LOAD_OUT                : out   std_logic_vector(3 downto 0);
-	DBG_REM_CTR_OUT             : out   std_logic_vector(3 downto 0);
-	DBG_CTS_CTR_OUT             : out   std_logic_vector(2 downto 0);
-	DBG_SF_WCNT_OUT             : out   std_logic_vector(15 downto 0);
-	DBG_SF_RCNT_OUT             : out   std_logic_vector(16 downto 0);
-	DBG_SF_DATA_OUT             : out   std_logic_vector(15 downto 0);
-	DBG_SF_RD_EN_OUT            : out   std_logic;
-	DBG_SF_WR_EN_OUT            : out   std_logic;
-	DBG_SF_EMPTY_OUT            : out   std_logic;
-	DBG_SF_AEMPTY_OUT           : out   std_logic;
-	DBG_SF_FULL_OUT             : out   std_logic;
-	DBG_SF_AFULL_OUT            : out   std_logic;
-	DEBUG_OUT                   : out   std_logic_vector(63 downto 0)
-);
-end entity;
-
-architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is
-
-component fifo_32kx16x8_mb
-port( 
-	Data            : in    std_logic_vector(15 downto 0); 
-	WrClock         : in    std_logic;
-	RdClock         : in    std_logic; 
-	WrEn            : in    std_logic;
-	RdEn            : in    std_logic;
-	Reset           : in    std_logic; 
-	RPReset         : in    std_logic; 
-	AmEmptyThresh   : in    std_logic_vector(15 downto 0); 
-	AmFullThresh    : in    std_logic_vector(14 downto 0); 
-	Q               : out   std_logic_vector(7 downto 0); 
-	WCNT            : out   std_logic_vector(15 downto 0); 
-	RCNT            : out   std_logic_vector(16 downto 0);
-	Empty           : out   std_logic;
-	AlmostEmpty     : out   std_logic;
-	Full            : out   std_logic;
-	AlmostFull      : out   std_logic
-);
-end component;
-
-type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE);
-signal saveCurrentState, saveNextState : saveStates;
-signal state                : std_logic_vector(3 downto 0);
-signal data_req_comb        : std_logic;
-signal data_req             : std_logic; -- request data signal, will be used for fee_read generation
-signal rst_saved_ctr_comb   : std_logic;
-signal rst_saved_ctr        : std_logic;
-
-signal fee_read_comb        : std_logic;
-signal fee_read             : std_logic; -- fee_read signal
-signal saved_ctr            : std_logic_vector(16 downto 0);
-signal ce_saved_ctr         : std_logic;
-
--- header data
-signal cts_rnd              : std_logic_vector(15 downto 0);
-signal cts_rnd_saved        : std_logic;
-signal cts_trg              : std_logic_vector(15 downto 0);
-signal cts_trg_saved        : std_logic;
-signal cts_len              : std_logic_vector(16 downto 0);
-signal cts_len_saved        : std_logic;
-
--- CTS interface
-signal cts_error_pattern    : std_logic_vector(31 downto 0);
-signal cts_length           : std_logic_vector(15 downto 0);
-signal cts_readout_finished : std_logic;
-signal cts_dataready        : std_logic;
-signal cts_data             : std_logic_vector(31 downto 0);
-
--- Split FIFO signals
-signal sf_data              : std_logic_vector(15 downto 0);
-signal sf_wr_en_comb        : std_logic;
-signal sf_wr_en             : std_logic; -- write signal for FIFO
-signal sf_rd_en_comb        : std_logic;
-signal sf_rd_en             : std_logic; -- read signal for FIFO
-signal sf_rd_valid_comb     : std_logic;
-signal sf_rd_valid          : std_logic;
-signal sf_wcnt              : std_logic_vector(15 downto 0);
-signal sf_rcnt              : std_logic_vector(16 downto 0);
-signal sf_empty             : std_logic;
-signal sf_aempty            : std_logic;
-signal sf_full              : std_logic;
-signal sf_afull             : std_logic;
-
--------------------------------------------------------------------
-type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC);
-signal loadCurrentState, loadNextState : loadStates;
-signal state2               :   std_logic_vector(3 downto 0);
-
-signal rem_ctr              : std_logic_vector(3 downto 0); -- counter for stripping / storing header data
-signal rst_rem_ctr_comb     : std_logic;
-signal rst_rem_ctr          : std_logic; -- reset the remove counter
-signal rst_regs_comb        : std_logic;
-signal rst_regs             : std_logic; -- reset storage registers
-signal rem_phase_comb       : std_logic;
-signal rem_phase            : std_logic; -- header remove phase
-signal data_phase_comb      : std_logic;
-signal data_phase           : std_logic; -- data transport phase from split fifo to PC
-signal pad_phase_comb       : std_logic;
-signal pad_phase            : std_logic; -- padding phase
-signal calc_pad_comb        : std_logic;
-signal calc_pad             : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE
-signal pad_data_comb        : std_logic;
-signal pad_data             : std_logic; -- reset PC_DATA register to known padding byte value
-
-signal pc_sos_comb          : std_logic;
-signal pc_sos               : std_logic; -- start of data signal
-signal pc_eod_comb          : std_logic;
-signal pc_eod               : std_logic; -- end of data signal
-
-signal ce_rem_ctr_comb      : std_logic;
-signal ce_rem_ctr           : std_logic; -- count enable for remove counter
-signal remove_done_comb     : std_logic;
-signal remove_done          : std_logic; -- end of header stripping process
-signal read_done_comb       : std_logic;
-signal read_done            : std_logic; -- end of data phase (read phase from SF)
-
-signal pc_data              : std_logic_vector(7 downto 0);
-signal pc_data_q            : std_logic_vector(7 downto 0);
-signal pc_trig_nr           : std_logic_vector(15 downto 0);
-signal pc_sub_size          : std_logic_vector(17 downto 0);
-signal read_size            : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo
-signal padding_needed       : std_logic;
-signal pc_wr_en_comb        : std_logic;
-signal pc_wr_en_q           : std_logic;
-signal pc_wr_en_qq          : std_logic;
-signal pc_wr_en_qqq         : std_logic;
-signal pc_eod_q             : std_logic;
-signal pc_eod_qq            : std_logic;
-
-signal debug                : std_logic_vector(63 downto 0);
-
--- gk 
-signal bank_select          : std_logic_vector(3 downto 0);
-signal save_addr_comb       : std_logic;
-signal save_addr            : std_logic;
-signal addr_saved_comb	    : std_logic;
-signal addr_saved	    : std_logic;
-signal start_config	    : std_logic;
-signal config_done	    : std_logic;
-signal add_sub_state        : std_logic;
-signal add_sub_state_comb   : std_logic;
-signal add_sub_ctr          : std_logic_vector(3 downto 0);
-signal load_sub             : std_logic;
-signal load_sub_comb        : std_logic;
-signal load_sub_done        : std_logic;
-signal load_sub_done_comb   : std_logic;
-signal load_sub_ctr         : std_logic_vector(3 downto 0);
-signal load_sub_ctr_comb    : std_logic;
-signal actual_message_size  : std_logic_vector(31 downto 0);
-signal rst_msg              : std_logic;
-signal rst_msg_comb         : std_logic;
-signal more_subevents       : std_logic;
-signal data_phase2          : std_logic;
-signal data_phase2_comb     : std_logic;
-signal trig_random          : std_logic_vector(7 downto 0);
-signal readout_ctr          : std_logic_vector(23 downto 0);
-signal readout_ctr_lock     : std_logic;
-
-begin
-
--- Fake signals
---START_CONFIG_OUT <= '0'; -- gk 27.03.10
-BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
-START_CONFIG_OUT <= start_config;  -- gk 27.03.10
-config_done <= CONFIG_DONE_IN; -- gk 29.03.10
-
--- gk 26.04.10
-READOUT_CTR_PROC : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
-			readout_ctr <= READOUT_CTR_IN;
-			readout_ctr_lock <= '0';
-		-- gk 15.06.10
-		-- increment the counter after the event is sent
-		elsif ( (saveCurrentState = SCLOSE) and (readout_ctr_lock = '0') ) then
-			readout_ctr_lock <= '1';
-			readout_ctr <= readout_ctr + x"1";
-		elsif (saveCurrentState = SIDLE) then
-			readout_ctr_lock <= '0';
--- 		elsif ((CTS_START_READOUT_IN = '0') and (readout_ctr_lock = '0')) then
--- 			readout_ctr <= readout_ctr + x"1";
--- 			readout_ctr_lock <= '1';
--- 		elsif (CTS_START_READOUT_IN = '0') then
--- 			readout_ctr_lock <= '0';
-		end if;
-	end if;
-end process READOUT_CTR_PROC;
-
--- gk 27.03.10
-bank_select_proc : process( CLK )
-begin
-	if rising_edge( CLK ) then
-		-- gk 29.03.10 for debug only: should round robin over 4 addresses with each subevent
--- 		if( (RESET = '1') or (bank_select > "0011") ) then
--- 			bank_select <= "0000";
--- 		elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
--- 			bank_select <= bank_select + x"1";
--- 		end if;
-		-- gk 29.03.10
-		if( (RESET = '1') or (rst_msg = '1') ) then --(rst_regs = '1') ) then
-			bank_select <= "0000";
-		-- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
-			bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
-		end if;
-	end if;
-end process bank_select_proc;
-
--- gk 29.03.10
-start_config_proc : process( CLK )
-begin
-	if rising_edge( CLK ) then
-		if( (RESET = '1') or (config_done = '1') or (rst_msg = '1') ) then --(rst_regs = '1') or (config_done = '1') ) then
-			start_config <= '0';
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then  -- gk 01.06.10
-			start_config <= '1';
-		end if;
-	end if;
-end process start_config_proc;
-
--- CTS interface signals
-cts_error_pattern    <= (others => '0'); -- FAKE
-
-cts_length           <= x"0000"; -- length of data payload is always 0
-cts_data             <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'
-
-cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';
-
-cts_dataready        <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE) 
-							else '0';
-
--- Byte swapping... done here. TAKE CARE!
--- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes
--- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port.
--- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped
--- for GbE inside the packet constructor.
---
--- Long live the Endianess!
-
--- Sync all critical pathes
-THE_SYNC_PROC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		--sf_data       <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below
-		sf_wr_en      <= sf_wr_en_comb;
-		ce_rem_ctr    <= ce_rem_ctr_comb;
-		sf_rd_en      <= sf_rd_en_comb;
-		fee_read      <= fee_read_comb;
-		read_done     <= read_done_comb;
-		pc_eod_qq     <= pc_eod_q;
-		pc_eod_q      <= pc_eod;
-		pc_wr_en_qqq  <= pc_wr_en_qq;
-		pc_wr_en_qq   <= pc_wr_en_q;
-		pc_wr_en_q    <= pc_wr_en_comb;
-	end if;
-end process THE_SYNC_PROC;
-
--- gk 27.03.10 data selector for sf to write the evt builder address on top of data
-SF_DATA_PROC : process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if (RESET = '1') then  -- gk 31.05.10
-			sf_data <= (others => '0');
-		elsif( save_addr = '1' ) then
-			sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
-			sf_data(15 downto 4) <= x"abc";
-		-- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
-		elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
-			sf_data <= x"0001"; -- gk 06.11.10
-		elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
-			sf_data <= x"5555"; -- gk 06.11.10
-		elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
-			sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
-		elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
-			sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
-		else
-			sf_data <= FEE_DATA_IN;
-		end if;
-	end if;
-end process SF_DATA_PROC;
-
--- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
-					 else '0';
-
--- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
--- gk 27.03.10
---sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
---					 else '0';
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
-					(save_addr = '1') or
-					(add_sub_state = '1')  -- gk 29.03.10 save the subsubevent
-					 else '0';
-
--- Counter for header word storage
-THE_CTS_SAVED_CTR: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
-			saved_ctr <= (others => '0');
-		elsif( ce_saved_ctr = '1' ) then
-			saved_ctr <= saved_ctr + 1;
-		end if;
-	end if;
-end process THE_CTS_SAVED_CTR;
-
--- gk 27.03.10 do not count evt builder address as saved ipu bytes
---ce_saved_ctr <= sf_wr_en;
-ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en;
-
--- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO
-saveMachineProc: process( CLK )
-begin
-	if rising_edge(CLK) then
-		if RESET = '1' then
-			saveCurrentState <= SIDLE;
-			data_req         <= '0';
-			rst_saved_ctr    <= '0';
-			save_addr	 <= '0'; -- gk 27.03.10
-			addr_saved	 <= '0'; -- gk 27.03.10
-			add_sub_state    <= '0'; -- gk 29.03.10
-		else
-			saveCurrentState <= saveNextState;
-			data_req         <= data_req_comb;
-			rst_saved_ctr    <= rst_saved_ctr_comb;
-			save_addr	 <= save_addr_comb; -- gk 27.03.10
-			addr_saved	 <= addr_saved_comb; -- gk 27.03.10
-			add_sub_state    <= add_sub_state_comb; -- gk 29.03.10
-		end if;
-	end if;
-end process saveMachineProc;
-
-saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN )
-begin
-	saveNextState      <= SIDLE;
-	data_req_comb      <= '0';
-	rst_saved_ctr_comb <= '0';
-	save_addr_comb     <= '0'; -- gk 27.03.10
-	addr_saved_comb    <= '0'; -- gk 27.03.10
-	add_sub_state_comb <= '0';  -- gk 29.03.10
-	case saveCurrentState is
-		when SIDLE =>
-			state <= x"0";
-			if (CTS_START_READOUT_IN = '1') then
-				saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10
-				data_req_comb <= '1';
-				rst_saved_ctr_comb <= '1';
-			else
-				saveNextState <= SIDLE;
-			end if;
-		-- gk 27.03.10
-		when SAVE_EVT_ADDR =>
-			state <= x"5";
-			saveNextState <= WAIT_FOR_DATA;
-			data_req_comb <= '1';
-			save_addr_comb <= '1';
-		when WAIT_FOR_DATA =>
-			state <= x"1";
-			if (FEE_BUSY_IN = '1') then
-				saveNextState <= SAVE_DATA;
-				data_req_comb <= '1';
-			else
-				saveNextState <= WAIT_FOR_DATA;
-				data_req_comb <= '1';
-			end if;
-			addr_saved_comb <= '1';  -- gk 27.03.10
-		when SAVE_DATA =>
-			state <= x"2";
-			if (FEE_BUSY_IN = '0') then
-				saveNextState <= TERMINATE;
-			else
-				saveNextState <= SAVE_DATA;
-				data_req_comb <= '1';
-			end if;
-		when TERMINATE =>
-			state <= x"3";
-			if (CTS_READ_IN = '1') then
-				saveNextState <= SCLOSE;
-			else
-				saveNextState <= TERMINATE;
-			end if;
-		when SCLOSE =>
-			state <= x"4";
-			if (CTS_START_READOUT_IN = '0') then
-				saveNextState <= ADD_SUBSUB1; --SIDLE;  -- gk 29.03.10
-			else
-				saveNextState <= SCLOSE;
-			end if;
-		-- gk 29.03.10 new states during which the subsub bytes are saved
-		when ADD_SUBSUB1 =>
-			state <= x"6";
-			add_sub_state_comb <= '1';
-			saveNextState <= ADD_SUBSUB2;
-		when ADD_SUBSUB2 =>
-			state<= x"7";
-			add_sub_state_comb <= '1';
-			saveNextState <= ADD_SUBSUB3;
-		when ADD_SUBSUB3 =>
-			state<= x"8";
-			add_sub_state_comb <= '1';
-			saveNextState <= ADD_SUBSUB4;
-		when ADD_SUBSUB4 =>
-			state<= x"9";
-			add_sub_state_comb <= '1';
-			saveNextState <= SIDLE;
-		when others =>
-			state <= x"f";
-			saveNextState <= SIDLE;
-	end case;
-end process saveMachine;
-
--- gk 29.03.10
-ADD_SUB_CTR_PROC : process( CLK )
-begin
-	if( rising_edge( CLK ) ) then
-		if( (RESET = '1') or (rst_saved_ctr = '1') ) then
-			add_sub_ctr <= (others => '0');
-		elsif( add_sub_state = '1' ) then
-			add_sub_ctr <= add_sub_ctr + 1;
-		end if;
-	end if;
-end process ADD_SUB_CTR_PROC;
-
--- save triggerRnd from incoming data for cts response
-CTS_RND_PROC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
-			cts_rnd       <= (others => '0');
-			cts_rnd_saved <= '0';
-		elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then
-			cts_rnd <= sf_data;
-			cts_rnd_saved <= '1';
-		end if;
-	end if;
-end process CTS_RND_PROC;
-
--- save triggerNr from incoming data for cts response
-CTS_TRG_PROC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
-			cts_trg       <= (others => '0');
-			cts_trg_saved <= '0';
-		elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then
-			cts_trg <= sf_data;
-			cts_trg_saved <= '1';
-		end if;
-	end if;
-end process CTS_TRG_PROC;
-
--- save size from incoming data for cts response (future) and to get rid of padding
-CTS_SIZE_PROC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
-			cts_len       <= (others => '0');
-			cts_len_saved <= '0';
-		elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then
-			cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words
-			cts_len(0)           <= '0';
-		elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then
-			cts_len       <= cts_len + x"4";
-			cts_len_saved <= '1';
-		end if;
-	end if;
-end process CTS_SIZE_PROC;
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Split FIFO
-THE_SPLIT_FIFO: fifo_32kx16x8_mb
-port map( 
-	-- Byte swapping for correct byte order on readout side of FIFO
-	Data(15 downto 8) => sf_data(7 downto 0),
-	Data(7 downto 0)  => sf_data(15 downto 8),
-	WrClock         => CLK,
-	RdClock         => CLK, 
-	WrEn            => sf_wr_en,
-	RdEn            => sf_rd_en,
-	Reset           => RESET, 
-	RPReset         => RESET, 
-	AmEmptyThresh   => b"0000_0000_0000_0010", -- one byte ahead
-	AmFullThresh    =>  b"111_1111_1110_1111", -- 0x7fef = 32751
-	Q               => pc_data, --open,
-	WCNT            => sf_wcnt,
-	RCNT            => sf_rcnt,
-	Empty           => sf_empty,
-	AlmostEmpty     => sf_aempty,
-	Full            => sf_full,
-	AlmostFull      => sf_afull
-);
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- write signal for PC data
-pc_wr_en_comb <= (data_phase and sf_rd_en) or pad_phase or (load_sub and sf_rd_en) or data_phase2; -- gk 30.03.10 added load_sub  -- gk 20.04.10 added data_phase2
-
--- FIFO data delay process (also forces padding bytes to known value)
-THE_DATA_DELAY_PROC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if( pad_data = '1' ) then
-			pc_data_q <= x"aa"; -- padding for 64bit
-		else
-			pc_data_q   <= pc_data;
-		end if;
-	end if;
-end process THE_DATA_DELAY_PROC;
-
--- Statemachine for reading the data payload from the SPLIT_FIFO and feeding
--- it into the packet constructor
-loadMachineProc : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if RESET = '1' then
-			loadCurrentState <= LIDLE;
-			rst_rem_ctr      <= '0';
-			rem_phase        <= '0';
-			calc_pad         <= '0';
-			data_phase       <= '0';
-			pad_phase        <= '0';
-			pc_sos           <= '0';
-			pc_eod           <= '0';
-			rst_regs         <= '0';
-			pad_data         <= '0';
-			load_sub         <= '0'; -- gk 30.03.10
-			rst_msg          <= '0'; -- gk 08.04.10
-			data_phase2      <= '0'; -- gk 20.04.10
-		else
-			loadCurrentState <= loadNextState;
-			rst_rem_ctr      <= rst_rem_ctr_comb;
-			rem_phase        <= rem_phase_comb;
-			calc_pad         <= calc_pad_comb;
-			data_phase       <= data_phase_comb;
-			pad_phase        <= pad_phase_comb;
-			pc_sos           <= pc_sos_comb;
-			pc_eod           <= pc_eod_comb;
-			rst_regs         <= rst_regs_comb;
-			pad_data         <= pad_data_comb;
-			load_sub         <= load_sub_comb; -- gk 30.03.10
-			rst_msg          <= rst_msg_comb; -- gk 08.04.10
-			data_phase2      <= data_phase2_comb;  -- gk 20.04.10
-		end if;
-	end if;
-end process loadMachineProc;
-
-sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and  (remove_done = '0') ) or
-					( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0')   ) or
-					( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) -- gk 30.03.10
-					 else '0';
-
-ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') ) 
-					   else '0';
-
-loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done )
-begin
-	loadNextState    <= LIDLE;
-	rst_rem_ctr_comb <= '0';
-	rem_phase_comb   <= '0';
-	calc_pad_comb    <= '0';
-	data_phase_comb  <= '0';
-	pad_phase_comb   <= '0';
-	pc_sos_comb      <= '0';
-	pc_eod_comb      <= '0';
-	rst_regs_comb    <= '0';
-	pad_data_comb    <= '0';
-	load_sub_comb    <= '0';  -- gk 30.03.10
-	rst_msg_comb     <= '0';  -- gk 08.04.10
-	data_phase2_comb <= '0';  -- gk 20.04.10
-	case loadCurrentState is
-		when LIDLE =>
-			state2 <= x"0";
-			if( (sf_aempty = '0') and (PC_READY_IN = '1') ) then
-				loadNextState <= INIT;
-				rst_rem_ctr_comb <= '1';
-				rst_regs_comb <= '1';
-				rst_msg_comb <= '1';  -- gk 08.04.10
-			else
-				loadNextState <= LIDLE;
-			end if;
-		when INIT =>
-			state2 <= x"1";
-			loadNextState <= REMOVE;
-			rem_phase_comb <= '1';
-		-- gk 08.04.10 changed to gather more subevents into one queue
-		when REMOVE =>
-			state2 <= x"2";
-			if( remove_done = '1' ) then
-				loadNextState <= DECIDE;
-				if (MULTI_EVT_ENABLE_IN = '1') then
-					-- gk 03.06.10
-					if(pc_sub_size(2) = '0') then
-						if((actual_message_size + pc_sub_size + x"18") <= MAX_MESSAGE_SIZE_IN) then
-							loadNextState <= CALCA;
-							calc_pad_comb <= '1';
-						else
-							loadNextState <= CALCC;
-						end if;
-					else
-						if((actual_message_size + pc_sub_size + x"1c") <= MAX_MESSAGE_SIZE_IN) then
-							loadNextState <= CALCA;
-							calc_pad_comb <= '1';
-						else
-							loadNextState <= CALCC;
-						end if;
-					end if;
-				else
-					loadNextState <= CALCA;
-					calc_pad_comb <= '1';
-				end if;
-			else
-				loadNextState <= REMOVE;
-				rem_phase_comb <= '1';
-			end if;
-		when CALCA =>
-			state2 <= x"3";
-			loadNextState <= CALCB;
-			pc_sos_comb <= '1';
-		when CALCB =>
-			-- we need a branch in case of length "0"!!!!
-			state2 <= x"4";
-			loadNextState <= LOAD;
-			-- gk 20.04.2010
-			if (more_subevents = '0') then
-				data_phase_comb <= '1';
-			else
-				data_phase2_comb <= '1';
-			end if;
-		when LOAD =>
-			state2 <= x"5";
-			-- gk 31.03.10 after loading subevent data read the subsubevent from sf
-			if ( read_done = '1' ) then
-				loadNextState <= LOAD_SUBSUB;
-			-- gk 31.03.10 moved to the load_subsub state
--- 			if   ( (read_done = '1') and (padding_needed = '0') ) then
--- 				loadNextState <= LOAD_SUBSUB; --CALCC;  --gk 30.03.10
--- 			elsif( (read_done = '1') and (padding_needed = '1') ) then
--- 				loadNextState <= PAD0;
--- 				pad_phase_comb <= '1';
-			else
-				loadNextState <= LOAD;
-				data_phase_comb <= '1';
-			end if;
-		-- gk 31.03.10
-		when LOAD_SUBSUB =>
-			state2 <= x"d";
-			if( load_sub_done = '1' ) then
-				if( padding_needed = '0' ) then
-					if (MULTI_EVT_ENABLE_IN = '1') then
-						loadNextState <= INIT; --CALCC;  -- gk 08.04.10
-						rst_rem_ctr_comb <= '1';  -- gk 08.04.10
-						rst_regs_comb <= '1';  -- gk 08.04.10
-					else
-						loadNextState <= CALCC;
-					end if;
-				else
-					loadNextState <= PAD0;
-					pad_phase_comb <= '1';
-				end if;
-			else
-				loadNextState <= LOAD_SUBSUB;
-				load_sub_comb <= '1';
-			end if;
-		when PAD0 =>
-			state2 <= x"6";
-			loadNextState <= PAD1;
-			pad_phase_comb <= '1';
-			pad_data_comb <= '1';
-		when PAD1 =>
-			state2 <= x"7";
-			loadNextState <= PAD2;
-			pad_phase_comb <= '1';
-			pad_data_comb <= '1';
-		when PAD2 =>
-			state2 <= x"8";
-			loadNextState <= PAD3;
-			pad_phase_comb <= '1';
-			pad_data_comb <= '1';
-		when PAD3 =>
-			state2 <= x"9";
-			if (MULTI_EVT_ENABLE_IN = '1') then
-				loadNextState <= INIT; -- gk 08.04.10
-				rst_rem_ctr_comb <= '1';  -- gk 08.04.10
-				rst_regs_comb <= '1';  -- gk 08.04.10
-			else
-				loadNextState <= CALCC;
-			end if;
-			pad_data_comb <= '1';
-		-- gk 31.03.10 the load_subsub state moved straight after load and before padding
-		-- gk 30.03.10
--- 		when LOAD_SUBSUB =>
--- 			state2 <= x"d";
--- 			if( load_sub_done = '1' ) then
--- 				loadNextState <= CALCC;
--- 			else
--- 				loadNextState <= LOAD_SUBSUB;
--- 				load_sub_comb <= '1';
--- 			end if;
-		when CALCC =>
-			state2 <= x"a";
-			loadNextState <= CLOSE;
-			pc_eod_comb <= '1';
-		when CLOSE =>
-			state2 <= x"b";
-			loadNextState <= WAIT_PC;
-			--rst_regs_comb <= '1';  -- gk 08.04.10
-			rst_msg_comb <= '1';  -- gk 08.04.10
-		when WAIT_PC =>
-			state2 <= x"c";
-			if( PC_READY_IN = '1' ) then
-				if (MULTI_EVT_ENABLE_IN = '1') then
-					loadNextState <= CALCA; --LIDLE;  -- gk 08.04.10
-					calc_pad_comb <= '1';  -- gk 08.04.10
-				else
-					loadNextState <= LIDLE;
-				end if;
-			else
-				loadNextState <= WAIT_PC;
-			end if;
-		when others =>
-			state2 <= x"f";
-			loadNextState <= LIDLE;
-	end case;
-end process loadMachine;
-
--- gk 30.03.10
-load_sub_ctr_comb <= '1' when ( (load_sub = '1') and (load_sub_done = '0') and (sf_aempty = '0') )
-				else '0';
-
--- gk 30.03.10
-LOAD_SUB_CTR_PROC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_regs = '1') ) then  -- gk 08.04.10
-			load_sub_ctr <= (others => '0');
-		elsif( (load_sub_ctr_comb = '1') ) then
-			load_sub_ctr <= load_sub_ctr + 1;
-		end if;
-	end if;
-end process LOAD_SUB_CTR_PROC;
-
--- gk 30.03.10
-load_sub_done_comb <= '1' when (load_sub_ctr = x"7") else '0';
-
--- gk 30.03.10
-LOAD_SUB_DONE_PROC : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if ( (RESET = '1') or (rst_regs = '1') ) then  -- gk 08.04.10
-			load_sub_done <= '0';
-		else
-			load_sub_done <= load_sub_done_comb;
-		end if;
-	end if;
-end process LOAD_SUB_DONE_PROC;
-
--- gk 20.04.10
--- used only in multiple event mode
-MORE_SUBEVENTS_PROC : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if( (RESET = '1') or (rst_msg = '1') ) then
-			more_subevents <= '0';
-		elsif (data_phase = '1') then
-			more_subevents <= '1';
-		end if;
-	end if;
-end process MORE_SUBEVENTS_PROC;
-
--- gk 26.04.10
-TRIG_RANDOM_PROC : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if ((RESET = '1') or (rst_regs = '1')) then
-			trig_random <= (others => '0');
-		elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then
-			trig_random <= pc_data;
-		end if;
-	end if;
-end process TRIG_RANDOM_PROC;
-
-
--- Counter for stripping the unneeded parts of the data stream, and saving the important parts
-THE_REMOVE_CTR: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_rem_ctr = '1') ) then
-			rem_ctr <= (others => '0');
-		elsif( (ce_rem_ctr = '1') ) then
-			rem_ctr <= rem_ctr + 1;
-		end if;
-	end if;
-end process THE_REMOVE_CTR;
-
-remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0';  -- gk 29.03.10 two more for evt builder address
-
-THE_REM_DONE_SYNC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_rem_ctr = '1') ) then
-			remove_done <= '0';
-		else
-			remove_done <= remove_done_comb;
-		end if;
-	end if;
-end process THE_REM_DONE_SYNC;
-
--- extract the trigger number from splitfifo data
-THE_TRG_NR_PROC: process( CLK )
-begin
-	if rising_edge(CLK) then
-		if   ( (RESET = '1') or (rst_regs = '1') ) then
-			pc_trig_nr <= (others => '0');
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then  -- x"4" gk 29.03.10
-			pc_trig_nr(7 downto 0) <= pc_data;
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then  -- x"3" gk 29.03.10
-			pc_trig_nr(15 downto 8) <= pc_data;
-		end if;
-	end if;
-end process THE_TRG_NR_PROC;
-
--- check for padding
-THE_PADDING_NEEDED_PROC: process( CLK )
-begin
-	if rising_edge(CLK) then
-		if   ( (RESET = '1') or (rst_regs = '1') ) then
-			padding_needed <= '0';
-		elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then
-			padding_needed <= '1';
-		elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then
-			padding_needed <= '0';
-		end if;
-	end if;
-end process THE_PADDING_NEEDED_PROC;
-
--- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,
--- and in case of padding needed increase it accordingly
-THE_SUB_SIZE_PROC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_regs = '1') ) then
-			pc_sub_size <= (others => '0');
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then  -- x"6" gk 29.03.10
-			pc_sub_size(9 downto 2) <= pc_data;
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then  -- x"5" gk 29.03.10
-			pc_sub_size(17 downto 10) <= pc_data;
-		-- gk 30.03.10 bug fixed in the way that is written below
-		-- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
-		elsif( (calc_pad = '1') and (padding_needed = '1') ) then
-			pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
-		elsif( (calc_pad = '1') and (padding_needed = '0') ) then
-			pc_sub_size <= pc_sub_size + x"8";
-		end if;
-	end if;
-end process THE_SUB_SIZE_PROC;
-
--- number of bytes to read from split fifo
-THE_READ_SIZE_PROC: process( CLK )
-begin
-	if( rising_edge(CLK) ) then
-		if   ( (RESET = '1') or (rst_rem_ctr = '1') ) then
-			read_size   <= (others => '0');
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then  -- x"6" gk 29.03.10
-			read_size(9 downto 2) <= pc_data;
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then  -- x"5" gk 29.03.10
-			read_size(17 downto 10) <= pc_data;
---      elsif( ((calc_pad = '1') and (read_done = '0')) ) then
---          read_size <= read_size - 2;
-		elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then
-			read_size <= read_size - 1;
-		end if;
-	end if;
-end process THE_READ_SIZE_PROC;
-
--- gk 08.04.10
--- used only in multi event mode
-ACTUAL_MSG_SIZE_PROC : process(CLK)
-begin
-	if(rising_edge(CLK)) then
-		if( (RESET = '1') or (rst_msg = '1') ) then
-			actual_message_size <= x"0000_0028"; -- gk 29.04.10 termination + queue headers
-		-- gk 28.04.10
-		elsif (pc_sos = '1') then
-			actual_message_size <= actual_message_size + pc_sub_size + x"10";  -- gk 28.04.10 +x10 for subevent headers
---		elsif ( (read_done = '1') and (data_phase = '1') ) then
---			actual_message_size <= actual_message_size + pc_sub_size;
--- 		elsif( (calc_pad = '1') and (padding_needed = '1') ) then
--- 			actual_message_size <= actual_message_size + pc_sub_size + 4 + 8;
--- 		elsif( (calc_pad = '1') and (padding_needed = '0') ) then
--- 			actual_message_size <= actual_message_size + pc_sub_size + 8;
-		end if;
-	end if;
-end process ACTUAL_MSG_SIZE_PROC;
-
-read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
-
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
--- Debug signals
-debug(0)              <= sf_full;
-debug(1)              <= sf_empty;
-debug(2)              <= sf_afull;
-debug(3)              <= sf_aempty;
-
-debug(7 downto  4)    <= state2;
-
-debug(11 downto 8)    <= state;
-
-dbg_bs_proc : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if RESET = '1' then
-			debug(15 downto 12) <= (others => '0');
-		elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
-			debug(15 downto 12) <= bank_select;
-		end if;
-	end if;
-end process dbg_bs_proc;
-
-debug(16)             <= config_done;
-debug(17)             <= remove_done;
-debug(18)             <= read_done;
-debug(19)             <= padding_needed;
-
-debug(20)             <= load_sub_done;
-
-dbg_cts_inf_proc : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if RESET = '1' then
-			debug(39 downto 32) <= (others => '0');
-		elsif ( save_addr = '1' ) then
-			debug(39 downto 32) <= CTS_INFORMATION_IN;
-		end if;
-	end if;
-end process dbg_cts_inf_proc;
---debug(47 downto 32)   <= pc_sub_size(15 downto 0);
-debug(47 downto 40) <= (others => '0');
-debug(63 downto 48)   <= actual_message_size(15 downto 0);
-
--- debug(31)           <= remove_done;
--- debug(30)           <= read_done;
--- debug(29)           <= ce_rem_ctr;
--- debug(28)           <= rst_rem_ctr;
--- debug(27)           <= rst_regs;
--- debug(26)           <= rem_phase;
--- debug(25)           <= data_phase;
--- debug(24)           <= pad_phase;
--- debug(23)           <= pad_data;
--- debug(22 downto 17) <= (others => '0');
--- debug(16 downto 0)  <= saved_ctr;
-
--- Outputs
-FEE_READ_OUT             <= fee_read;
-CTS_ERROR_PATTERN_OUT    <= cts_error_pattern;
-CTS_DATA_OUT             <= cts_data;
-CTS_DATAREADY_OUT        <= cts_dataready;
-CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
-CTS_LENGTH_OUT           <= cts_length;
-
-PC_SOS_OUT               <= pc_sos;
-PC_EOD_OUT               <= pc_eod_q;
-PC_DATA_OUT              <= pc_data_q;
-PC_WR_EN_OUT             <= pc_wr_en_qq;
-PC_TRIG_NR_OUT           <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random; -- x"0000" & pc_trig_nr;  -- gk 26.04.10
-PC_SUB_SIZE_OUT          <= b"0000_0000_0000_00" & pc_sub_size;
-PC_PADDING_OUT           <= padding_needed;
-
-BSM_SAVE_OUT             <= state;
-BSM_LOAD_OUT             <= state2;
-DBG_CTS_CTR_OUT          <= saved_ctr(2 downto 0);
-DBG_REM_CTR_OUT          <= rem_ctr;
-DBG_SF_DATA_OUT          <= sf_data;
-DBG_SF_WCNT_OUT          <= sf_wcnt;
-DBG_SF_RCNT_OUT          <= read_size(16 downto 0); --sf_rcnt;
-DBG_SF_RD_EN_OUT         <= sf_rd_en;
-DBG_SF_WR_EN_OUT         <= sf_wr_en;
-DBG_SF_EMPTY_OUT         <= sf_empty;
-DBG_SF_AEMPTY_OUT        <= sf_aempty;
-DBG_SF_FULL_OUT          <= sf_full;
-DBG_SF_AFULL_OUT         <= sf_afull;
-
-DEBUG_OUT                <= debug;
-
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use IEEE.std_logic_arith.all;
+
+library work;
+
+entity trb_net16_ipu2gbe is
+port( 
+	CLK                         : in    std_logic;
+	RESET                       : in    std_logic;
+	-- IPU interface directed toward the CTS
+	CTS_NUMBER_IN               : in    std_logic_vector (15 downto 0);
+	CTS_CODE_IN                 : in    std_logic_vector (7  downto 0);
+	CTS_INFORMATION_IN          : in    std_logic_vector (7  downto 0);
+	CTS_READOUT_TYPE_IN         : in    std_logic_vector (3  downto 0);
+	CTS_START_READOUT_IN        : in    std_logic;
+	CTS_READ_IN                 : in    std_logic;
+	CTS_DATA_OUT                : out   std_logic_vector (31 downto 0);
+	CTS_DATAREADY_OUT           : out   std_logic;
+	CTS_READOUT_FINISHED_OUT    : out   std_logic;      --no more data, end transfer, send TRM
+	CTS_LENGTH_OUT              : out   std_logic_vector (15 downto 0);
+	CTS_ERROR_PATTERN_OUT       : out   std_logic_vector (31 downto 0);
+	-- Data from Frontends
+	FEE_DATA_IN                 : in    std_logic_vector (15 downto 0);
+	FEE_DATAREADY_IN            : in    std_logic;
+	FEE_READ_OUT                : out   std_logic;
+	FEE_BUSY_IN                 : in    std_logic;
+	FEE_STATUS_BITS_IN          : in    std_logic_vector (31 downto 0);
+	-- slow control interface
+	START_CONFIG_OUT			: out	std_logic; -- reconfigure MACs/IPs/ports/packet size
+	BANK_SELECT_OUT				: out	std_logic_vector(3 downto 0); -- configuration page address
+	CONFIG_DONE_IN				: in	std_logic; -- configuration finished
+	DATA_GBE_ENABLE_IN			: in	std_logic; -- IPU data is forwarded to GbE
+	DATA_IPU_ENABLE_IN			: in	std_logic; -- IPU data is forwarded to CTS / TRBnet
+	MULTI_EVT_ENABLE_IN			: in	std_logic; -- enable multi event packets
+	MAX_MESSAGE_SIZE_IN			: in	std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue  -- gk 08.04.10
+	MIN_MESSAGE_SIZE_IN			: in	std_logic_vector(31 downto 0); -- gk 20.07.10
+	READOUT_CTR_IN				: in	std_logic_vector(23 downto 0); -- gk 26.04.10
+	READOUT_CTR_VALID_IN			: in	std_logic; -- gk 26.04.10
+	-- PacketConstructor interface
+	ALLOW_LARGE_IN				: in	std_logic;  -- gk 21.07.10
+	PC_WR_EN_OUT                : out   std_logic;
+	PC_DATA_OUT                 : out   std_logic_vector (7 downto 0);
+	PC_READY_IN                 : in    std_logic;
+	PC_SOS_OUT                  : out   std_logic;
+	PC_EOD_OUT                  : out   std_logic;
+	PC_SUB_SIZE_OUT             : out   std_logic_vector(31 downto 0);
+	PC_TRIG_NR_OUT              : out   std_logic_vector(31 downto 0);
+	PC_PADDING_OUT              : out   std_logic;
+	MONITOR_OUT                 : out   std_logic_vector(191 downto 0);
+	DEBUG_OUT                   : out   std_logic_vector(383 downto 0)
+);
+end entity;
+
+architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is
+
+component fifo_32kx16x8_mb2
+port( 
+	Data            : in    std_logic_vector(17 downto 0); 
+	WrClock         : in    std_logic;
+	RdClock         : in    std_logic; 
+	WrEn            : in    std_logic;
+	RdEn            : in    std_logic;
+	Reset           : in    std_logic; 
+	RPReset         : in    std_logic; 
+	AmEmptyThresh   : in    std_logic_vector(15 downto 0); 
+	AmFullThresh    : in    std_logic_vector(14 downto 0); 
+	Q               : out   std_logic_vector(8 downto 0); 
+	WCNT            : out   std_logic_vector(15 downto 0); 
+	RCNT            : out   std_logic_vector(16 downto 0);
+	Empty           : out   std_logic;
+	AlmostEmpty     : out   std_logic;
+	Full            : out   std_logic;
+	AlmostFull      : out   std_logic
+);
+end component;
+
+type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE);
+signal saveCurrentState, saveNextState : saveStates;
+signal state                : std_logic_vector(3 downto 0);
+signal data_req_comb        : std_logic;
+signal data_req             : std_logic; -- request data signal, will be used for fee_read generation
+signal rst_saved_ctr_comb   : std_logic;
+signal rst_saved_ctr        : std_logic;
+
+signal fee_read_comb        : std_logic;
+signal fee_read             : std_logic; -- fee_read signal
+signal saved_ctr            : std_logic_vector(16 downto 0);
+signal ce_saved_ctr         : std_logic;
+
+-- header data
+signal cts_rnd              : std_logic_vector(15 downto 0);
+signal cts_rnd_saved        : std_logic;
+signal cts_trg              : std_logic_vector(15 downto 0);
+signal cts_trg_saved        : std_logic;
+signal cts_len              : std_logic_vector(16 downto 0);
+signal cts_len_saved        : std_logic;
+
+-- CTS interface
+signal cts_error_pattern    : std_logic_vector(31 downto 0);
+signal cts_length           : std_logic_vector(15 downto 0);
+signal cts_readout_finished : std_logic;
+signal cts_dataready        : std_logic;
+signal cts_data             : std_logic_vector(31 downto 0);
+
+-- Split FIFO signals
+signal sf_data              : std_logic_vector(15 downto 0);
+signal sf_wr_en_comb        : std_logic;
+signal sf_wr_en             : std_logic; -- write signal for FIFO
+signal sf_rd_en_comb        : std_logic;
+signal sf_rd_en             : std_logic; -- read signal for FIFO
+signal sf_wcnt              : std_logic_vector(15 downto 0);
+signal sf_rcnt              : std_logic_vector(16 downto 0);
+signal sf_empty             : std_logic;
+signal sf_aempty            : std_logic;
+signal sf_full              : std_logic;
+signal sf_afull             : std_logic;
+
+-------------------------------------------------------------------
+type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2);
+signal loadCurrentState, loadNextState : loadStates;
+signal state2               :   std_logic_vector(3 downto 0);
+
+signal rem_ctr              : std_logic_vector(3 downto 0); -- counter for stripping / storing header data
+signal rst_rem_ctr_comb     : std_logic;
+signal rst_rem_ctr          : std_logic; -- reset the remove counter
+signal rst_regs_comb        : std_logic;
+signal rst_regs             : std_logic; -- reset storage registers
+signal rem_phase_comb       : std_logic;
+signal rem_phase            : std_logic; -- header remove phase
+signal data_phase_comb      : std_logic;
+signal data_phase           : std_logic; -- data transport phase from split fifo to PC
+signal pad_phase_comb       : std_logic;
+signal pad_phase            : std_logic; -- padding phase
+signal calc_pad_comb        : std_logic;
+signal calc_pad             : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE
+signal pad_data_comb        : std_logic;
+signal pad_data             : std_logic; -- reset PC_DATA register to known padding byte value
+
+signal pc_sos_comb          : std_logic;
+signal pc_sos               : std_logic; -- start of data signal
+signal pc_eod_comb          : std_logic;
+signal pc_eod               : std_logic; -- end of data signal
+
+signal ce_rem_ctr_comb      : std_logic;
+signal ce_rem_ctr           : std_logic; -- count enable for remove counter
+signal remove_done_comb     : std_logic;
+signal remove_done          : std_logic; -- end of header stripping process
+signal read_done_comb       : std_logic;
+signal read_done            : std_logic; -- end of data phase (read phase from SF)
+
+signal pc_data              : std_logic_vector(7 downto 0);
+signal pc_data_q            : std_logic_vector(7 downto 0);
+signal pc_trig_nr           : std_logic_vector(15 downto 0);
+signal pc_sub_size          : std_logic_vector(17 downto 0);
+signal read_size            : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo
+signal padding_needed       : std_logic;
+signal pc_wr_en_comb        : std_logic;
+signal pc_wr_en_q           : std_logic;
+signal pc_wr_en_qq          : std_logic;
+signal pc_wr_en_qqq         : std_logic;
+signal pc_eod_q             : std_logic;
+
+signal debug                : std_logic_vector(383 downto 0);
+
+-- gk 
+signal bank_select          : std_logic_vector(3 downto 0);
+signal save_addr_comb       : std_logic;
+signal save_addr            : std_logic;
+signal addr_saved_comb	    : std_logic;
+signal addr_saved	    : std_logic;
+signal start_config	    : std_logic;
+signal config_done	    : std_logic;
+signal add_sub_state        : std_logic;
+signal add_sub_state_comb   : std_logic;
+signal add_sub_ctr          : std_logic_vector(3 downto 0);
+signal load_sub             : std_logic;
+signal load_sub_comb        : std_logic;
+signal load_sub_done        : std_logic;
+signal load_sub_done_comb   : std_logic;
+signal load_sub_ctr         : std_logic_vector(3 downto 0);
+signal load_sub_ctr_comb    : std_logic;
+signal actual_message_size  : std_logic_vector(31 downto 0);
+signal more_subevents       : std_logic;
+signal trig_random          : std_logic_vector(7 downto 0);
+signal readout_ctr          : std_logic_vector(23 downto 0);
+signal readout_ctr_lock     : std_logic;
+signal pc_trig_nr_q         : std_logic_vector(31 downto 0);
+
+-- gk 20.07.10
+signal inc_data_ctr         : std_logic_vector(31 downto 0);
+signal dropped_sm_events_ctr : std_logic_vector(31 downto 0);
+signal dropped_lr_events_ctr : std_logic_vector(31 downto 0);
+signal dropped_ctr          : std_logic_vector(31 downto 0);
+-- gk 22.07.10
+signal headers_invalid      : std_logic;
+signal headers_invalid_ctr  : std_logic_vector(31 downto 0);
+signal cts_len_q            : std_logic_vector(15 downto 0);
+signal cts_trg_q            : std_logic_vector(15 downto 0);
+signal cts_rnd_q            : std_logic_vector(15 downto 0);
+signal first_run_trg        : std_logic_vector(15 downto 0);
+signal first_run_addr       : std_logic_vector(15 downto 0);
+signal first_run_lock       : std_logic;
+signal cts_addr             : std_logic_vector(15 downto 0);
+signal cts_addr_q           : std_logic_vector(15 downto 0);
+signal cts_addr_saved       : std_logic;
+
+-- gk 24.07.10
+signal save_eod             : std_logic;
+signal save_eod_comb        : std_logic;
+
+signal load_eod             : std_logic;
+signal endpoint_addr        : std_logic_vector(15 downto 0);
+signal endp_addr_lock       : std_logic;
+
+signal saved_events_ctr     : std_logic_vector(15 downto 0);
+signal loaded_events_ctr    : std_logic_vector(15 downto 0);
+signal constr_events_ctr    : std_logic_vector(31 downto 0);
+signal event_waiting        : std_logic;
+
+signal drop_sub             : std_logic;
+signal drop_sub_comb        : std_logic;
+signal drop_event           : std_logic;
+signal drop_event_comb      : std_logic;
+signal drop_small           : std_logic;
+signal drop_large           : std_logic;
+signal drop_headers         : std_logic;
+signal drop_small_comb      : std_logic;
+signal drop_large_comb      : std_logic;
+signal drop_headers_comb    : std_logic;
+signal inc_trg_ctr          : std_logic;
+signal inc_trg_ctr_comb     : std_logic;
+
+signal invalid_hsize_ctr    : std_logic_vector(15 downto 0);
+signal invalid_hsize_lock   : std_logic;
+
+begin
+
+-- Fake signals
+--START_CONFIG_OUT <= '0'; -- gk 27.03.10
+BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
+START_CONFIG_OUT <= start_config;  -- gk 27.03.10
+config_done <= CONFIG_DONE_IN; -- gk 29.03.10
+
+-- CTS interface signals
+cts_error_pattern    <= (others => '0'); -- FAKE
+
+cts_length           <= x"0000"; -- length of data payload is always 0
+cts_data             <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1'
+
+cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0';
+
+cts_dataready        <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE) 
+							else '0';
+
+-- Byte swapping... done here. TAKE CARE!
+-- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes
+-- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port.
+-- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped
+-- for GbE inside the packet constructor.
+--
+-- Long live the Endianess!
+
+-- Sync all critical pathes
+THE_SYNC_PROC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		--sf_data       <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below
+		sf_wr_en      <= sf_wr_en_comb;
+		ce_rem_ctr    <= ce_rem_ctr_comb;
+		sf_rd_en      <= sf_rd_en_comb;
+		fee_read      <= fee_read_comb;
+		read_done     <= read_done_comb;
+		pc_eod_q      <= pc_eod;
+		pc_wr_en_qqq  <= pc_wr_en_qq;
+		pc_wr_en_qq   <= pc_wr_en_q;
+		pc_wr_en_q    <= pc_wr_en_comb;
+	end if;
+end process THE_SYNC_PROC;
+
+-- gk 27.03.10 data selector for sf to write the evt builder address on top of data
+SF_DATA_PROC : process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if (RESET = '1') then  -- gk 31.05.10
+			sf_data <= (others => '0');
+		elsif( save_addr = '1' ) then
+			sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
+			sf_data(15 downto 4) <= x"abc";
+		-- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
+		elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
+			sf_data <= x"0001"; -- gk 11.06.10
+		elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
+			sf_data <= x"5555"; -- gk 11.06.10
+		elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
+			sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
+		elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
+			sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
+		else
+			sf_data <= FEE_DATA_IN;
+		end if;
+	end if;
+end process SF_DATA_PROC;
+
+-- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
+fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
+					 else '0';
+
+-- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
+sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
+					(save_addr = '1') or
+					(add_sub_state = '1')  -- gk 29.03.10 save the subsubevent
+					 else '0';
+
+-- gk 27.03.10 do not count evt builder address as saved ipu bytes
+--ce_saved_ctr <= sf_wr_en;
+ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en;
+
+-- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO
+saveMachineProc: process( CLK )
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			saveCurrentState <= SIDLE;
+			data_req         <= '0';
+			rst_saved_ctr    <= '0';
+			save_addr	 <= '0'; -- gk 27.03.10
+			addr_saved	 <= '0'; -- gk 27.03.10
+			add_sub_state    <= '0'; -- gk 29.03.10
+			save_eod         <= '0'; -- gk 25.07.10
+		else
+			saveCurrentState <= saveNextState;
+			data_req         <= data_req_comb;
+			rst_saved_ctr    <= rst_saved_ctr_comb;
+			save_addr	 <= save_addr_comb; -- gk 27.03.10
+			addr_saved	 <= addr_saved_comb; -- gk 27.03.10
+			add_sub_state    <= add_sub_state_comb; -- gk 29.03.10
+			save_eod         <= save_eod_comb; -- gk 25.07.10
+		end if;
+	end if;
+end process saveMachineProc;
+
+saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN)
+begin
+	saveNextState      <= SIDLE;
+	data_req_comb      <= '0';
+	rst_saved_ctr_comb <= '0';
+	save_addr_comb     <= '0'; -- gk 27.03.10
+	addr_saved_comb    <= '0'; -- gk 27.03.10
+	add_sub_state_comb <= '0'; -- gk 29.03.10
+	save_eod_comb      <= '0'; -- gk 25.07.10
+	case saveCurrentState is
+		when SIDLE =>
+			state <= x"0";
+			if (CTS_START_READOUT_IN = '1') then
+				saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10
+				data_req_comb <= '1';
+				rst_saved_ctr_comb <= '1';
+			else
+				saveNextState <= SIDLE;
+			end if;
+		-- gk 27.03.10
+		when SAVE_EVT_ADDR =>
+			state <= x"5";
+			saveNextState <= WAIT_FOR_DATA;
+			data_req_comb <= '1';
+			save_addr_comb <= '1';
+		when WAIT_FOR_DATA =>
+			state <= x"1";
+			if (FEE_BUSY_IN = '1') then
+				saveNextState <= SAVE_DATA;
+				data_req_comb <= '1';
+			else
+				saveNextState <= WAIT_FOR_DATA;
+				data_req_comb <= '1';
+			end if;
+			addr_saved_comb <= '1';  -- gk 27.03.10
+		when SAVE_DATA =>
+			state <= x"2";
+			if (FEE_BUSY_IN = '0') then
+				saveNextState <= TERMINATE;
+			else
+				saveNextState <= SAVE_DATA;
+				data_req_comb <= '1';
+			end if;
+		when TERMINATE =>
+			state <= x"3";
+			if (CTS_READ_IN = '1') then
+				saveNextState <= SCLOSE;
+			else
+				saveNextState <= TERMINATE;
+			end if;
+		when SCLOSE =>
+			state <= x"4";
+			if (CTS_START_READOUT_IN = '0') then
+				saveNextState <= ADD_SUBSUB1; --SIDLE;  -- gk 29.03.10
+			else
+				saveNextState <= SCLOSE;
+			end if;
+		-- gk 29.03.10 new states during which the subsub bytes are saved
+		when ADD_SUBSUB1 =>
+			state <= x"6";
+			saveNextState <= ADD_SUBSUB2;
+			add_sub_state_comb <= '1';
+		when ADD_SUBSUB2 =>
+			state<= x"7";
+			saveNextState <= ADD_SUBSUB3;
+			add_sub_state_comb <= '1';
+			save_eod_comb <= '1';
+		when ADD_SUBSUB3 =>
+			state<= x"8";
+			saveNextState <= ADD_SUBSUB4;
+			add_sub_state_comb <= '1';
+		when ADD_SUBSUB4 =>
+			state<= x"9";
+			saveNextState <= SIDLE;
+			add_sub_state_comb <= '1';
+		when others =>
+			state <= x"f";
+			saveNextState <= SIDLE;
+	end case;
+end process saveMachine;
+
+-- gk 29.03.10
+ADD_SUB_CTR_PROC : process( CLK )
+begin
+	if( rising_edge( CLK ) ) then
+		if( (RESET = '1') or (rst_saved_ctr = '1') ) then
+			add_sub_ctr <= (others => '0');
+		elsif( add_sub_state = '1' ) then
+			add_sub_ctr <= add_sub_ctr + 1;
+		end if;
+	end if;
+end process ADD_SUB_CTR_PROC;
+
+--********
+-- SAVE INCOMING EVENT HEADERS
+--********
+
+-- Counter for header word storage
+THE_CTS_SAVED_CTR: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+			saved_ctr <= (others => '0');
+		elsif( ce_saved_ctr = '1' ) then
+			saved_ctr <= saved_ctr + 1;
+		end if;
+	end if;
+end process THE_CTS_SAVED_CTR;
+
+-- save triggerRnd from incoming data for cts response
+CTS_RND_PROC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+			cts_rnd       <= (others => '0');
+			cts_rnd_saved <= '0';
+		elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then
+			cts_rnd <= sf_data;
+			cts_rnd_saved <= '1';
+		end if;
+	end if;
+end process CTS_RND_PROC;
+
+-- save triggerNr from incoming data for cts response
+CTS_TRG_PROC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+			cts_trg       <= (others => '0');
+			cts_trg_saved <= '0';
+		elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then
+			cts_trg <= sf_data;
+			cts_trg_saved <= '1';
+		end if;
+	end if;
+end process CTS_TRG_PROC;
+
+-- save size from incoming data for cts response (future) and to get rid of padding
+CTS_SIZE_PROC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+			cts_len       <= (others => '0');
+			cts_len_saved <= '0';
+		elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then
+			cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words
+			cts_len(0)           <= '0';
+		elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then
+			cts_len       <= cts_len + x"4";
+			cts_len_saved <= '1';
+		end if;
+	end if;
+end process CTS_SIZE_PROC;
+
+-- gk 22.07.10
+CTS_ADDR_PROC : process(CLK)
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_saved_ctr = '1') ) then
+			cts_addr       <= (others => '0');
+			cts_addr_saved <= '0';
+		elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then
+			cts_addr       <= sf_data;
+			cts_addr_saved <= '1';
+		end if;
+	end if;
+end process CTS_ADDR_PROC;
+
+--******
+-- SAVE FIRST EVENT HEADER VALUES
+--******
+
+-- gk 22.07.10
+FIRST_RUN_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			first_run_trg <= (others => '0');
+			first_run_addr <= (others => '0');
+			first_run_lock <= '0';
+		elsif (first_run_lock = '0') and (cts_addr_saved = '1') then
+			first_run_trg <= cts_trg;
+			first_run_addr <= cts_addr;
+			first_run_lock <= '1';
+		-- important: value saved by saveMachine but incremented by loadMachine
+		elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then
+			first_run_trg <= first_run_trg + x"1";
+		end if;
+	end if;
+end process FIRST_RUN_PROC;
+
+-- gk 25.07.10
+SAVED_EVT_CTR_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			saved_events_ctr <= (others => '0');
+		elsif (save_eod = '1') then
+			saved_events_ctr <= saved_events_ctr + x"1";
+		end if;
+	end if;
+end process SAVED_EVT_CTR_PROC;
+
+
+-- gk 20.07.10
+INC_DATA_CTR_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') or (rst_saved_ctr = '1') then
+			inc_data_ctr <= (others => '0');
+		elsif (sf_wr_en = '1') and (data_req = '1') then
+			inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
+		end if;
+	end if;
+end process INC_DATA_CTR_proc;
+
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+
+-- Split FIFO
+THE_SPLIT_FIFO: fifo_32kx16x8_mb2
+port map( 
+	-- Byte swapping for correct byte order on readout side of FIFO
+	Data(7 downto 0)  => sf_data(15 downto 8),
+	Data(8)           => '0',
+	Data(16 downto 9) => sf_data(7 downto 0),
+	Data(17)          => save_eod,
+	WrClock         => CLK,
+	RdClock         => CLK,
+	WrEn            => sf_wr_en,
+	RdEn            => sf_rd_en,
+	Reset           => RESET,
+	RPReset         => RESET,
+	AmEmptyThresh   => b"0000_0000_0000_0010", -- one byte ahead
+	AmFullThresh    =>  b"111_1111_1110_1111", -- 0x7fef = 32751
+	Q(7 downto 0)   => pc_data,
+	Q(8)            => load_eod,
+	WCNT            => sf_wcnt,
+	RCNT            => sf_rcnt,
+	Empty           => sf_empty,
+	AlmostEmpty     => sf_aempty,
+	Full            => sf_full,
+	AlmostFull      => sf_afull
+);
+
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+
+-- gk 25.07.10
+EVENT_WAITING_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			event_waiting <= '0';
+		elsif (loaded_events_ctr /= saved_events_ctr) then
+			event_waiting <= '1';
+		else
+			event_waiting <= '0';
+		end if;
+	end if;
+end process EVENT_WAITING_PROC;
+
+-- write signal for PC data
+pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or
+			(pad_phase = '1') or
+			((load_sub = '1') and (sf_rd_en = '1')) or
+			((drop_sub = '1') and (sf_rd_en = '1')) or
+			((drop_event = '1') and (sf_rd_en = '1'))
+			else '0';
+
+sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and  (remove_done = '0') ) or
+			--( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or
+			( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or  -- gk 26.07.10
+			( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10
+			( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or
+			( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') )
+			else '0';
+
+ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') )
+			else '0';
+
+-- FIFO data delay process (also forces padding bytes to known value)
+THE_DATA_DELAY_PROC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if( pad_data = '1' ) then
+			pc_data_q <= x"aa"; -- padding for 64bit
+		-- gk 21.07.10
+		-- set the error flag if a broken packet is sent
+		elsif (drop_sub = '1') and (load_sub_ctr = x"3") then
+			pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0);
+		else
+			pc_data_q   <= pc_data;
+		end if;
+	end if;
+end process THE_DATA_DELAY_PROC;
+
+-- Statemachine for reading the data payload from the SPLIT_FIFO and feeding
+-- it into the packet constructor
+loadMachineProc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			loadCurrentState <= LIDLE;
+			rst_rem_ctr      <= '0';
+			rem_phase        <= '0';
+			calc_pad         <= '0';
+			data_phase       <= '0';
+			pad_phase        <= '0';
+			pc_sos           <= '0';
+			pc_eod           <= '0';
+			rst_regs         <= '0';
+			pad_data         <= '0';
+			load_sub         <= '0'; -- gk 30.03.10
+			drop_sub         <= '0'; -- gk 25.07.10
+			drop_event       <= '0'; -- gk 25.07.10
+			drop_small       <= '0'; -- gk 25.07.10
+			drop_large       <= '0'; -- gk 25.07.10
+			drop_headers     <= '0'; -- gk 25.07.10
+			inc_trg_ctr      <= '0'; -- gk 26.07.10
+		else
+			loadCurrentState <= loadNextState;
+			rst_rem_ctr      <= rst_rem_ctr_comb;
+			rem_phase        <= rem_phase_comb;
+			calc_pad         <= calc_pad_comb;
+			data_phase       <= data_phase_comb;
+			pad_phase        <= pad_phase_comb;
+			pc_sos           <= pc_sos_comb;
+			pc_eod           <= pc_eod_comb;
+			rst_regs         <= rst_regs_comb;
+			pad_data         <= pad_data_comb;
+			load_sub         <= load_sub_comb; -- gk 30.03.1
+			drop_sub         <= drop_sub_comb;  -- gk 25.07.10
+			drop_event       <= drop_event_comb;  -- gk 25.07.10
+			drop_small       <= drop_small_comb;  -- gk 25.07.10
+			drop_large       <= drop_large_comb; -- gk 25.07.10
+			drop_headers     <= drop_headers_comb; -- gk 25.07.10
+			inc_trg_ctr      <= inc_trg_ctr_comb; -- gk 26.07.10
+		end if;
+	end if;
+end process loadMachineProc;
+
+loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting)
+begin
+	loadNextState    <= LIDLE;
+	rst_rem_ctr_comb <= '0';
+	rem_phase_comb   <= '0';
+	calc_pad_comb    <= '0';
+	data_phase_comb  <= '0';
+	pad_phase_comb   <= '0';
+	pc_sos_comb      <= '0';
+	pc_eod_comb      <= '0';
+	rst_regs_comb    <= '0';
+	pad_data_comb    <= '0';
+	load_sub_comb    <= '0';  -- gk 30.03.10
+	drop_sub_comb    <= '0';  -- gk 25.07.10
+	drop_event_comb  <= '0';  -- gk 25.07.10
+	drop_small_comb  <= '0';  -- gk 25.07.10
+	drop_large_comb  <= '0';  -- gk 25.07.10
+	drop_headers_comb <= '0'; -- gk 25.07.10
+	inc_trg_ctr_comb <= '0';  -- gk 26.07.10
+	case loadCurrentState is
+		when LIDLE =>
+			state2 <= x"0";
+			-- gk 23.07.10
+			if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') ) then
+				loadNextState <= INIT;
+				rst_rem_ctr_comb <= '1';
+				rst_regs_comb <= '1';
+			else
+				loadNextState <= LIDLE;
+			end if;
+		when INIT =>
+			state2 <= x"1";
+			loadNextState <= REMOVE;
+			rem_phase_comb <= '1';
+		when REMOVE =>
+			state2 <= x"2";
+			if( remove_done = '1' ) then
+				loadNextState <= WAIT_TO_REMOVE;
+				inc_trg_ctr_comb <= '1';
+			else
+				loadNextState <= REMOVE;
+				rem_phase_comb <= '1';
+			end if;
+		when WAIT_TO_REMOVE =>
+			if (rem_ctr = x"a") then
+				loadNextState <= DECIDE;
+			else
+				loadNextState <= WAIT_TO_REMOVE;
+			end if;
+		when DECIDE =>
+			if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
+				loadNextState <= PAUSE_BEFORE_DROP1;
+				drop_large_comb <= '1';
+			elsif (pc_sub_size <= MIN_MESSAGE_SIZE_IN) then
+				loadNextState <= PAUSE_BEFORE_DROP1;
+				drop_small_comb <= '1';
+			elsif (pc_trig_nr + x"1" /= first_run_trg) then
+				loadNextState <= PAUSE_BEFORE_DROP1;
+				drop_headers_comb <= '1';
+			elsif (endpoint_addr /= first_run_addr) then
+				loadNextState <= PAUSE_BEFORE_DROP1;
+				drop_headers_comb <= '1';
+			else
+				loadNextState <= CALCA;
+			end if;
+			calc_pad_comb <= '1';
+		when CALCA =>
+			state2 <= x"3";
+			loadNextState <= CALCB;
+			pc_sos_comb <= '1';
+		when CALCB =>
+			-- we need a branch in case of length "0"!!!!
+			state2 <= x"4";
+			loadNextState <= LOAD;
+			data_phase_comb <= '1';
+		when LOAD =>
+			state2 <= x"5";
+			-- gk 31.03.10 after loading subevent data read the subsubevent from sf
+			if (load_eod = '1') then
+				loadNextState <= LOAD_SUBSUB;
+			else
+				loadNextState <= LOAD;
+				data_phase_comb <= '1';
+			end if;
+		-- gk 31.03.10
+		when LOAD_SUBSUB =>
+			state2 <= x"d";
+			if( load_sub_done = '1' ) then
+				if( padding_needed = '0' ) then
+					loadNextState <= CALCC;
+				else
+					loadNextState <= PAD0;
+					pad_phase_comb <= '1';
+				end if;
+			else
+				loadNextState <= LOAD_SUBSUB;
+				load_sub_comb <= '1';
+			end if;
+		when PAD0 =>
+			state2 <= x"6";
+			loadNextState <= PAD1;
+			pad_phase_comb <= '1';
+			pad_data_comb <= '1';
+		when PAD1 =>
+			state2 <= x"7";
+			loadNextState <= PAD2;
+			pad_phase_comb <= '1';
+			pad_data_comb <= '1';
+		when PAD2 =>
+			state2 <= x"8";
+			loadNextState <= PAD3;
+			pad_phase_comb <= '1';
+			pad_data_comb <= '1';
+		when PAD3 =>
+			state2 <= x"9";
+			loadNextState <= CALCC;
+			pad_data_comb <= '1';
+		when CALCC =>
+			state2 <= x"a";
+			loadNextState <= CLOSE;
+			pc_eod_comb <= '1';
+		when CLOSE =>
+			state2 <= x"b";
+			loadNextState <= WAIT_PC;
+			rst_regs_comb <= '1';
+		when WAIT_PC =>
+			state2 <= x"c";
+			if( PC_READY_IN = '1' ) then
+				loadNextState <= LIDLE;
+			else
+				loadNextState <= WAIT_PC;
+			end if;
+		when PAUSE_BEFORE_DROP1 =>
+			loadNextState <= PAUSE_BEFORE_DROP2;
+			pc_sos_comb <= '1';
+		when PAUSE_BEFORE_DROP2 =>
+			loadNextState <= DROP;
+			drop_event_comb <= '1';
+		-- gk 23.07.10
+		when DROP =>
+			state2 <= x"e";
+			-- when data is dropped the eod marker stands as its end
+			if (load_eod = '1') then
+				loadNextState <= DROP_SUBSUB;
+			else
+				loadNextState <= DROP;
+				drop_event_comb <= '1';
+			end if;
+		-- gk 25.07.10
+		when DROP_SUBSUB =>
+			if (load_sub_done = '1') then
+				if( padding_needed = '0' ) then
+					loadNextState <= CALCC;
+				else
+					loadNextState <= PAD0;
+					pad_phase_comb <= '1';
+				end if;
+			else
+				loadNextState <= DROP_SUBSUB;
+				drop_sub_comb <= '1';
+			end if;
+		when others =>
+			state2 <= x"f";
+			loadNextState <= LIDLE;
+	end case;
+end process loadMachine;
+
+-- gk 25.07.10
+INVALID_STATS_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			dropped_lr_events_ctr <= (others => '0');
+			dropped_sm_events_ctr <= (others => '0');
+			headers_invalid_ctr   <= (others => '0');
+			dropped_ctr           <= (others => '0');
+			invalid_hsize_ctr     <= (others => '0');
+		elsif (rst_regs = '1') then
+			invalid_hsize_lock <= '0';
+		elsif (drop_small = '1') then
+			dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
+			dropped_ctr <= dropped_ctr + x"1";
+		elsif (drop_large = '1') then
+			dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
+			dropped_ctr <= dropped_ctr + x"1";
+		elsif (drop_headers = '1') then
+			headers_invalid_ctr   <= headers_invalid_ctr + x"1";
+			dropped_ctr <= dropped_ctr + x"1";
+		elsif (load_eod = '1') and (read_size /= x"3fffe") and (invalid_hsize_lock = '0') then
+			invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
+			invalid_hsize_lock <= '1';
+		end if;
+	end if;
+end process INVALID_STATS_PROC;
+
+-- gk 26.04.10
+READOUT_CTR_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
+			readout_ctr <= READOUT_CTR_IN;
+			readout_ctr_lock <= '0';
+		elsif (pc_sos = '1') then
+			readout_ctr <= readout_ctr + x"1";
+		end if;
+	end if;
+end process READOUT_CTR_PROC;
+
+--******
+-- SELECTION OF EVENT BUILDER
+--******
+
+-- gk 27.03.10
+bank_select_proc : process( CLK )
+begin
+	if rising_edge( CLK ) then
+		-- gk 29.03.10
+		if( (RESET = '1') or (rst_regs = '1') ) then
+			bank_select <= "0000";
+		-- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
+			bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
+		end if;
+	end if;
+end process bank_select_proc;
+
+-- gk 29.03.10
+start_config_proc : process( CLK )
+begin
+	if rising_edge( CLK ) then
+		if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then
+			start_config <= '0';
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then  -- gk 01.06.10
+			start_config <= '1';
+		end if;
+	end if;
+end process start_config_proc;
+
+
+--******
+-- LOAD SUBSUBEVENT
+--******
+
+-- gk 30.03.10
+load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') )
+				else '0';
+
+-- gk 30.03.10
+LOAD_SUB_CTR_PROC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_regs = '1') ) then  -- gk 08.04.10
+			load_sub_ctr <= (others => '0');
+		elsif( (load_sub_ctr_comb = '1') ) then
+			load_sub_ctr <= load_sub_ctr + 1;
+		end if;
+	end if;
+end process LOAD_SUB_CTR_PROC;
+
+-- gk 30.03.10
+-- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or
+-- 				((load_sub_ctr = x"4") and (drop_sub = '1'))
+-- 				else '0';
+load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0';
+
+-- gk 30.03.10
+LOAD_SUB_DONE_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if ( (RESET = '1') or (rst_regs = '1') ) then  -- gk 08.04.10
+			load_sub_done <= '0';
+		else
+			load_sub_done <= load_sub_done_comb;
+		end if;
+	end if;
+end process LOAD_SUB_DONE_PROC;
+
+--******
+-- EXTRACT EVENT HEADERS FROM SPLITFIFO
+--******
+
+-- Counter for stripping the unneeded parts of the data stream, and saving the important parts
+THE_REMOVE_CTR: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_rem_ctr = '1') ) then
+			rem_ctr <= (others => '0');
+		elsif( (ce_rem_ctr = '1') ) then
+			rem_ctr <= rem_ctr + 1;
+		end if;
+	end if;
+end process THE_REMOVE_CTR;
+
+remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0';  -- gk 29.03.10 two more for evt builder address
+
+THE_REM_DONE_SYNC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_rem_ctr = '1') ) then
+			remove_done <= '0';
+		else
+			remove_done <= remove_done_comb;
+		end if;
+	end if;
+end process THE_REM_DONE_SYNC;
+
+-- gk 26.04.10
+TRIG_RANDOM_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if ((RESET = '1') or (rst_regs = '1')) then
+			trig_random <= (others => '0');
+		elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then
+			trig_random <= pc_data;
+		end if;
+	end if;
+end process TRIG_RANDOM_PROC;
+
+-- extract the trigger number from splitfifo data
+THE_TRG_NR_PROC: process( CLK )
+begin
+	if rising_edge(CLK) then
+		if   ( (RESET = '1') or (rst_regs = '1') ) then
+			pc_trig_nr <= (others => '0');
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then  -- x"4" gk 29.03.10
+			pc_trig_nr(7 downto 0) <= pc_data;
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then  -- x"3" gk 29.03.10
+			pc_trig_nr(15 downto 8) <= pc_data;
+		end if;
+	end if;
+end process THE_TRG_NR_PROC;
+
+-- extract the subevent size from the splitfifo data, convert it from 32b to 8b units,
+-- and in case of padding needed increase it accordingly
+THE_SUB_SIZE_PROC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_regs = '1') ) then
+			pc_sub_size <= (others => '0');
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then  -- x"6" gk 29.03.10
+			pc_sub_size(9 downto 2) <= pc_data;
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then  -- x"5" gk 29.03.10
+			pc_sub_size(17 downto 10) <= pc_data;
+		-- gk 20.07.10
+		-- gk 30.03.10 bug fixed in the way that is written below
+		-- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
+		elsif( (calc_pad = '1') and (padding_needed = '1') ) then
+			pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
+		elsif( (calc_pad = '1') and (padding_needed = '0') ) then
+			pc_sub_size <= pc_sub_size + x"8";
+		end if;
+	end if;
+end process THE_SUB_SIZE_PROC;
+
+-- gk 25.07.10
+ENDP_ADDRESS_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') or (rst_regs = '1') then
+			endpoint_addr <= (others => '0');
+			endp_addr_lock <= '0';
+		elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then
+			endpoint_addr(7 downto 0) <= pc_data;
+			endp_addr_lock <= '1';
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then
+			endpoint_addr(15 downto 8) <= pc_data;
+			endp_addr_lock <= '0';
+		end if;
+	end if;
+end process ENDP_ADDRESS_PROC;
+
+
+
+-- check for padding
+THE_PADDING_NEEDED_PROC: process( CLK )
+begin
+	if rising_edge(CLK) then
+		if   ( (RESET = '1') or (rst_regs = '1') ) then
+			padding_needed <= '0';
+		elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then
+			padding_needed <= '1';
+		elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then
+			padding_needed <= '0';
+		end if;
+	end if;
+end process THE_PADDING_NEEDED_PROC;
+
+-- number of bytes to read from split fifo
+THE_READ_SIZE_PROC: process( CLK )
+begin
+	if( rising_edge(CLK) ) then
+		if   ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then
+			read_size   <= (others => '0');
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then  -- x"6" gk 29.03.10
+			read_size(9 downto 2) <= pc_data;
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then  -- x"5" gk 29.03.10
+			read_size(17 downto 10) <= pc_data;
+		elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then
+			read_size <= read_size - 1;
+		-- gk 25.07.10
+		elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then
+			read_size <= read_size - 1;
+		end if;
+	end if;
+end process THE_READ_SIZE_PROC;
+
+read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
+
+--******
+-- EVENTS COUNTERS
+--******
+
+-- gk 25.07.10
+LOADED_EVT_CTR_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			loaded_events_ctr <= (others => '0');
+		elsif (remove_done = '1') then
+			loaded_events_ctr <= loaded_events_ctr + x"1";
+		end if;
+	end if;
+end process LOADED_EVT_CTR_PROC;
+
+-- gk 25.07.10
+CONSTR_EVENTS_CTR_PROC : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			constr_events_ctr <= (others => '0');
+		elsif (pc_eod = '1') then
+			constr_events_ctr <= constr_events_ctr + x"1";
+		end if;
+	end if;
+end process CONSTR_EVENTS_CTR_PROC;
+
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+
+-- Debug signals
+debug(0)              <= sf_full;
+debug(1)              <= sf_empty;
+debug(2)              <= sf_afull;
+debug(3)              <= sf_aempty;
+
+debug(7 downto  4)    <= state2;
+
+debug(11 downto 8)    <= state;
+
+dbg_bs_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if RESET = '1' then
+			debug(15 downto 12) <= (others => '0');
+		elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
+			debug(15 downto 12) <= bank_select;
+		end if;
+	end if;
+end process dbg_bs_proc;
+
+debug(16)             <= config_done;
+debug(17)             <= remove_done;
+debug(18)             <= read_done;
+debug(19)             <= padding_needed;
+
+debug(20)             <= load_sub_done;
+
+dbg_cts_inf_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			debug(39 downto 32) <= (others => '0');
+		elsif ( save_addr = '1' ) then
+			debug(39 downto 32) <= CTS_INFORMATION_IN;
+		end if;
+	end if;
+end process dbg_cts_inf_proc;
+
+debug(47 downto 40) <= (others => '0');
+
+
+debug(63 downto 48)   <= actual_message_size(15 downto 0);
+
+dbg_pc_sub_size_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			debug(81 downto 64) <= (others => '0');
+		elsif (pc_sos = '1') then
+			debug(81 downto 64) <= pc_sub_size;
+		end if;
+	end if;
+end process dbg_pc_sub_size_proc;
+
+dbg_empty_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') or (rst_regs = '1') then
+			debug(84 downto 82) <= (others => '0');
+		elsif (read_size = 2) then
+			debug(82) <= sf_empty;
+		elsif (read_size = 1) then
+			debug(83) <= sf_empty;
+		elsif (read_size = 0) then
+			debug(84) <= sf_empty;
+		end if;
+	end if;
+end process dbg_empty_proc;
+
+debug(95 downto 85) <= (others => '0');
+
+dbg_inc_ctr_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			debug(127 downto 96) <= (others => '1');
+		elsif (saveCurrentState = SCLOSE) then
+			debug(127 downto 96) <= inc_data_ctr;
+		end if;
+	end if;
+end process dbg_inc_ctr_proc;
+
+debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
+debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
+
+debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
+debug(191 downto 176) <= (others => '0');
+
+dbg_cts_q_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (RESET = '1') then
+			cts_len_q <= (others => '0');
+			cts_rnd_q <= (others => '0');
+			cts_trg_q <= (others => '0');
+			cts_addr_q <= (others => '0');
+		elsif (cts_len_saved = '1') then
+			cts_len_q <= cts_len(16 downto 1);
+			cts_addr_q <= cts_addr;
+			cts_rnd_q <= cts_rnd;
+			cts_trg_q <= cts_trg;
+		end if;
+	end if;
+end process dbg_cts_q_proc;
+
+debug(207 downto 192) <= cts_trg_q;
+debug(223 downto 208) <= cts_rnd_q;
+debug(239 downto 224) <= cts_addr_q;
+debug(255 downto 240) <= cts_len_q;
+debug(271 downto 256) <= first_run_trg;
+debug(287 downto 272) <= first_run_addr;
+
+debug(303 downto 288) <= saved_events_ctr;
+debug(319 downto 304) <= loaded_events_ctr;
+
+debug(335 downto 320) <= constr_events_ctr(15 downto 0);
+debug(351 downto 336) <= dropped_ctr(15 downto 0);
+
+debug(367 downto 352) <= invalid_hsize_ctr;
+debug(383 downto 368) <= (others => '0');
+
+MONITOR_OUT(31 downto 0)    <= constr_events_ctr;
+MONITOR_OUT(63 downto 32)   <= dropped_ctr;
+MONITOR_OUT(95 downto 64)   <= headers_invalid_ctr;
+MONITOR_OUT(127 downto 96)  <= dropped_sm_events_ctr;
+MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
+MONITOR_OUT(191 downto 160) <= (others => '0');
+
+-- Outputs
+FEE_READ_OUT             <= fee_read;
+CTS_ERROR_PATTERN_OUT    <= cts_error_pattern;
+CTS_DATA_OUT             <= cts_data;
+CTS_DATAREADY_OUT        <= cts_dataready;
+CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
+CTS_LENGTH_OUT           <= cts_length;
+
+PC_SOS_OUT               <= pc_sos;
+PC_EOD_OUT               <= pc_eod; -- gk 26.07.10 --pc_eod_q;
+PC_DATA_OUT              <= pc_data_q;
+PC_WR_EN_OUT             <= pc_wr_en_qq;
+
+PC_TRIG_NR_OUT           <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random;
+
+PC_SUB_SIZE_OUT          <= b"0000_0000_0000_00" & pc_sub_size;
+PC_PADDING_OUT           <= padding_needed;
+
+DEBUG_OUT                <= debug;
+
 end architecture;
\ No newline at end of file
diff --git a/gbe_ecp2m/trb_net_gbe_components.vhd b/gbe_ecp2m/trb_net_gbe_components.vhd
index 0557e71..4d50070 100644
--- a/gbe_ecp2m/trb_net_gbe_components.vhd
+++ b/gbe_ecp2m/trb_net_gbe_components.vhd
@@ -51,24 +51,8 @@ port(
 	PC_SUB_SIZE_OUT             : out   std_logic_vector(31 downto 0);
 	PC_TRIG_NR_OUT              : out   std_logic_vector(31 downto 0);
 	PC_PADDING_OUT              : out   std_logic;
-	PC_SKIP_HEADERS_OUT         : out   std_logic;
-	PC_SKIP_TERM_OUT            : out   std_logic;
-	PC_DROP_EVENT_OUT           : out   std_logic;
-	-- Debug
-	BSM_SAVE_OUT                : out   std_logic_vector(3 downto 0);
-	BSM_LOAD_OUT                : out   std_logic_vector(3 downto 0);
-	DBG_REM_CTR_OUT             : out   std_logic_vector(3 downto 0);
-	DBG_CTS_CTR_OUT             : out   std_logic_vector(2 downto 0);
-	DBG_SF_WCNT_OUT             : out   std_logic_vector(15 downto 0);
-	DBG_SF_RCNT_OUT             : out   std_logic_vector(16 downto 0);
-	DBG_SF_DATA_OUT             : out   std_logic_vector(15 downto 0);
-	DBG_SF_RD_EN_OUT            : out   std_logic;
-	DBG_SF_WR_EN_OUT            : out   std_logic;
-	DBG_SF_EMPTY_OUT            : out   std_logic;
-	DBG_SF_AEMPTY_OUT           : out   std_logic;
-	DBG_SF_FULL_OUT             : out   std_logic;
-	DBG_SF_AFULL_OUT            : out   std_logic;
-	DEBUG_OUT                   : out   std_logic_vector(351 downto 0)
+	MONITOR_OUT                 : out   std_logic_vector(191 downto 0);
+	DEBUG_OUT                   : out   std_logic_vector(383 downto 0)
 );
 end component;
 
@@ -83,8 +67,6 @@ port(
 	PC_START_OF_SUB_IN      : in    std_logic;
 	PC_END_OF_DATA_IN       : in    std_logic;
 	-- queue and subevent layer headers
-	PC_SKIP_HEADERS_IN      : in    std_logic;
-	PC_SKIP_TERM_IN         : in    std_logic;
 	PC_SUB_SIZE_IN          : in    std_logic_vector(31 downto 0); -- store and swap
 	PC_PADDING_IN           : in std_logic;  -- gk 29.03.10
 	PC_DECODING_IN          : in    std_logic_vector(31 downto 0); -- swap
@@ -104,30 +86,6 @@ port(
 	FC_FLAGS_OFFSET_OUT     : out   std_logic_vector(15 downto 0);
 	FC_SOD_OUT              : out   std_logic;
 	FC_EOD_OUT              : out   std_logic;
-	-- debug ports
-	BSM_CONSTR_OUT          : out   std_logic_vector(3 downto 0);
-	BSM_LOAD_OUT            : out   std_logic_vector(3 downto 0);
-	BSM_SAVE_OUT            : out   std_logic_vector(3 downto 0);
-	DBG_SHF_EMPTY           : out   std_logic;
-	DBG_SHF_FULL            : out   std_logic;
-	DBG_SHF_WR_EN           : out   std_logic;
-	DBG_SHF_RD_EN           : out   std_logic;
-	DBG_SHF_Q               : out   std_logic_vector(7 downto 0);
-	DBG_DF_EMPTY            : out   std_logic;
-	DBG_DF_FULL             : out   std_logic;
-	DBG_DF_WR_EN            : out   std_logic;
-	DBG_DF_RD_EN            : out   std_logic;
-	DBG_DF_Q                : out   std_logic_vector(7 downto 0);
-	DBG_ALL_CTR             : out   std_logic_vector(4 downto 0);
-	DBG_SUB_CTR             : out   std_logic_vector(4 downto 0);
-	DBG_MY_CTR              : out   std_logic_vector(1 downto 0);
-	DBG_BYTES_LOADED        : out   std_logic_vector(15 downto 0);
-	DBG_SIZE_LEFT           : out   std_logic_vector(31 downto 0);
-	DBG_SUB_SIZE_TO_SAVE    : out   std_logic_vector(31 downto 0);
-	DBG_SUB_SIZE_LOADED     : out   std_logic_vector(31 downto 0);
-	DBG_SUB_BYTES_LOADED    : out   std_logic_vector(31 downto 0);
-	DBG_QUEUE_SIZE          : out   std_logic_vector(31 downto 0);
-	DBG_ACT_QUEUE_SIZE      : out   std_logic_vector(31 downto 0);
 	DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
@@ -281,6 +239,13 @@ port(
 	GBE_READOUT_CTR_VALID_OUT : out std_logic;  -- gk 26.04.10
 	GBE_DELAY_OUT             : out std_logic_vector(31 downto 0);
 	GBE_ALLOW_LARGE_OUT       : out std_logic;
+	-- gk 28.07.10
+	MONITOR_BYTES_IN          : in std_logic_vector(31 downto 0);
+	MONITOR_SENT_IN           : in std_logic_vector(31 downto 0);
+	MONITOR_DROPPED_IN        : in std_logic_vector(31 downto 0);
+	MONITOR_SM_IN             : in std_logic_vector(31 downto 0);
+	MONITOR_LR_IN             : in std_logic_vector(31 downto 0);
+	MONITOR_HDR_IN            : in std_logic_vector(31 downto 0);
 	-- gk 01.06.10
 	DBG_IPU2GBE1_IN          : in std_logic_vector(31 downto 0);
 	DBG_IPU2GBE2_IN          : in std_logic_vector(31 downto 0);
@@ -293,6 +258,7 @@ port(
 	DBG_IPU2GBE9_IN          : in std_logic_vector(31 downto 0);
 	DBG_IPU2GBE10_IN         : in std_logic_vector(31 downto 0);
 	DBG_IPU2GBE11_IN         : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE12_IN         : in std_logic_vector(31 downto 0);
 	DBG_PC1_IN               : in std_logic_vector(31 downto 0);
 	DBG_PC2_IN               : in std_logic_vector(31 downto 0);
 	DBG_FC1_IN               : in std_logic_vector(31 downto 0);
-- 
2.43.0