From ddd43ba8edd80fca718094162eb5a554133040f8 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 22 Jun 2010 16:22:17 +0000 Subject: [PATCH] *** empty log message *** --- compile1_frankfurt.pl | 2 +- compile2_frankfurt.pl | 154 ++++++++++++++++++++++++++++++++++++++ constraints_cts_fpga1.lpf | 15 ++++ constraints_cts_fpga2.lpf | 13 ++++ cts_fpga1.vhd | 1 + cts_fpga2.p2t | 21 ++++++ cts_fpga2.prj | 151 +++++++++++++++++++++++++++++++++++++ cts_fpga2.vhd | 116 ++++++++++++++++++++++++++++ 8 files changed, 472 insertions(+), 1 deletion(-) create mode 100644 compile2_frankfurt.pl create mode 100644 constraints_cts_fpga1.lpf create mode 100644 constraints_cts_fpga2.lpf create mode 100644 cts_fpga2.p2t create mode 100644 cts_fpga2.prj create mode 100644 cts_fpga2.vhd diff --git a/compile1_frankfurt.pl b/compile1_frankfurt.pl index 83c8ecf..dd3c91c 100755 --- a/compile1_frankfurt.pl +++ b/compile1_frankfurt.pl @@ -15,7 +15,7 @@ use strict; my $lattice_path = '/d/sugar/lattice/ispLEVER8.0/isptools/'; #my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; -my $synplify_path = '/d/sugar/lattice/synplify/fpga_c200906sp1'; +my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; use FileHandle; diff --git a/compile2_frankfurt.pl b/compile2_frankfurt.pl new file mode 100644 index 0000000..700d516 --- /dev/null +++ b/compile2_frankfurt.pl @@ -0,0 +1,154 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +# +########################################### +# +# Command line for synplify_pro +# + + +use Data::Dumper; + +use warnings; +use strict; + +my $lattice_path = '/d/sugar/lattice/ispLEVER8.0/isptools/'; +#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; +my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; + + +my $TOPNAME="cts_fpga2"; + +my $FAMILYNAME="LATTICEECP2M"; +my $DEVICENAME="LFE2M100E"; +my $PACKAGE="FPBGA900"; +my $SPEEDGRADE="5"; + + +#create full lpf file +system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +#my $c=$synplify_path."synplify_pro_oem -batch $TOPNAME".".prj"; +#my $c="$synplify_path/bin/synplify_pro -Pro -prj $TOPNAME".".prj"; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +#my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +#if ($r) { +#$c="cat $TOPNAME.srr"; +#system($c); +#exit 129; +#} + +foreach (@a) +{ + if(/\@E:/) + { + $c="cat $TOPNAME.srr"; + system($c); + print "bdabdhsadbhjasdhasldhbas"; + exit 129; + } +} +#if (0){ + +$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + + +system("rm $TOPNAME.ncd"); + +#$c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +# IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/constraints_cts_fpga1.lpf b/constraints_cts_fpga1.lpf new file mode 100644 index 0000000..e74b804 --- /dev/null +++ b/constraints_cts_fpga1.lpf @@ -0,0 +1,15 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +######################################### +# Clock Constraints +######################################### + FREQUENCY PORT CLK_200_IN 200.000000 MHz HOLD_MARGIN 0.100000 nS ; + + + + + + diff --git a/constraints_cts_fpga2.lpf b/constraints_cts_fpga2.lpf new file mode 100644 index 0000000..94f9d41 --- /dev/null +++ b/constraints_cts_fpga2.lpf @@ -0,0 +1,13 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +######################################### +# Clock Constraints +######################################### + FREQUENCY PORT CLK_100_IN 100.000000 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY PORT CLK_125_IN 125.000000 MHz HOLD_MARGIN 0.100000 nS ; + + + diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd index 43a0682..4cd4e28 100644 --- a/cts_fpga1.vhd +++ b/cts_fpga1.vhd @@ -70,6 +70,7 @@ entity cts_fpga1 is ); attribute syn_useioff : boolean; + attribute syn_useioff of FFC : signal is true; attribute syn_useioff of SPI_CLK_OUT : signal is true; attribute syn_useioff of SPI_CS_OUT : signal is true; attribute syn_useioff of SPI_SO_IN : signal is true; diff --git a/cts_fpga2.p2t b/cts_fpga2.p2t new file mode 100644 index 0000000..9ce01fc --- /dev/null +++ b/cts_fpga2.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 1 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: + diff --git a/cts_fpga2.prj b/cts_fpga2.prj new file mode 100644 index 0000000..13686f5 --- /dev/null +++ b/cts_fpga2.prj @@ -0,0 +1,151 @@ +#-- Synplicity, Inc. +#-- Version 9.0 +#-- Project file ../ctsaddon/cts_fpga1.prj + + + +#add_file options +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd" +add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" + + +add_file -vhdl -lib work "../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd" + + + +#Lattice SCM files +add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in200_out100.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd" +#Wrong filename, but hard to change now... + + +add_file -vhdl -lib work "cts_fpga2.vhd" + +#Some of these files have to be regenerated +# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd" +# add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd" +# add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd" +# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_clock_generator.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" + + + + + + + +#implementation: "workdir" +impl -add workdir -type fpga + +#device options +set_option -technology LATTICE-SCM +set_option -part LFSCM3GA40EP1 +set_option -package FF1020C +set_option -speed_grade -5 +set_option -part_companion "" + +#compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +#set_option -resource_sharing 0 +set_option -top_module "cts_fpga2" + +#map options +set_option -frequency auto +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +set_option -force_gsr auto +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 + + + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +#set result format/file last +project -result_format "edif" +project -result_file "workdir/cts_fpga2.edf" + + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" diff --git a/cts_fpga2.vhd b/cts_fpga2.vhd new file mode 100644 index 0000000..0bf3635 --- /dev/null +++ b/cts_fpga2.vhd @@ -0,0 +1,116 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +-- use work.trb_net16_hub_func.all; +use work.version.all; + +entity cts_fpga2 is + generic( + NUM_STAT_REGS : integer range 0 to 6 := 2; + NUM_CTRL_REGS : integer range 0 to 6 := 2; + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FF02"; + REGIO_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0002" + ); + port( + --Clocks + CLK_100_IN : in std_logic; + CLK_125_IN : in std_logic; + --Resets + RESET_FPGA_2 : in std_logic; + ADDON_RESET : in std_logic; + --To Other FPGAs + ADO_LV : inout std_logic_vector(61 downto 0); + FFC : inout std_logic_vector(22 downto 0); + --LED + LED_GBE_OK : out std_logic; + LED_GBE_RX : out std_logic; + LED_GBE_TX : out std_logic; + LED_TRB_OK : out std_logic; + LED_TRB_RX : out std_logic; + LED_TRB_TX : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + --SFP + GBE_LOS : out std_logic; + GBE_MOD : inout std_logic_vector(2 downto 0); + GBE_TX_DIS : out std_logic; + TRB_LOS : out std_logic; + TRB_MOD : inout std_logic_vector(2 downto 0); + TRB_TX_DIS : out std_logic; + --Flash + SPI_CLK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SI_OUT : out std_logic; + SPI_SO_IN : in std_logic; + PROGRAMN_OUT : out std_logic; + --RAM + RAM_ADSCB : out std_logic; + RAM_ADSPB : out std_logic; + RAM_ADVB : out std_logic; + RAM_CE_2 : out std_logic; + RAM_CEB : out std_logic; + RAM_CLK : out std_logic; + RAM_GWB : out std_logic; + RAM_OEB : out std_logic; + RAM_A : out std_logic_vector(19 downto 0); + RAM_DQ : inout std_logic_vector(18 downto 1); + --Others + ONEWIRE_MONITOR_OUT : out std_logic; + TEMPSENS : inout std_logic; + --Debug + TEST_LINE : out std_logic_vector(31 downto 0) + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FFC : signal is true; + attribute syn_useioff of SPI_CLK_OUT : signal is true; + attribute syn_useioff of SPI_CS_OUT : signal is true; + attribute syn_useioff of SPI_SO_IN : signal is true; + attribute syn_useioff of SPI_SI_OUT : signal is true; + attribute syn_useioff of ADO_LV : signal is true; + attribute syn_useioff of RAM_A : signal is true; + attribute syn_useioff of RAM_DQ : signal is true; + attribute syn_useioff of RAM_ADSCB : signal is true; + attribute syn_useioff of RAM_ADSPB : signal is true; + attribute syn_useioff of RAM_ADVB : signal is true; + attribute syn_useioff of RAM_CE_2 : signal is true; + attribute syn_useioff of RAM_CEB : signal is true; + attribute syn_useioff of RAM_CLK : signal is true; + attribute syn_useioff of RAM_GWB : signal is true; + attribute syn_useioff of RAM_OEB : signal is true; + + attribute syn_useioff of PROGRAMN_OUT : signal is false; + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TRB_OK_LED : signal is false; + attribute syn_useioff of TRB_RX_LED : signal is false; + attribute syn_useioff of TRB_TX_LED : signal is false; + attribute syn_useioff of GBE_OK_LED : signal is false; + attribute syn_useioff of GBE_RX_LED : signal is false; + attribute syn_useioff of GBE_TX_LED : signal is false; + attribute syn_useioff of TRB2_LOS : signal is false; + attribute syn_useioff of TRB2_MOD : signal is false; + attribute syn_useioff of TRB2_TX_DIS : signal is false; + attribute syn_useioff of GBE_LOS : signal is false; + attribute syn_useioff of GBE_MOD : signal is false; + attribute syn_useioff of GBE_TX_DIS : signal is false; + attribute syn_useioff of ONEWIRE_MONITOR_OUT : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + + +end entity; + + +architecture cts_fpga2_arch of cts_fpga2 is + +begin + +end architecture; \ No newline at end of file -- 2.43.0