From deed618a0019b2be7f3f3cbe772899b5ab62237e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 9 Dec 2019 15:34:27 +0100 Subject: [PATCH] Project for MDC TDC FPGA created --- .gitignore | 35 ++++ DBO/compile.pl | 1 + DBO/config.vhd | 104 ++++++++++ DBO/config_compile_frankfurt.pl | 25 +++ DBO/mdctdc.lpf | 155 +++++++++++++++ DBO/mdctdc.prj | 199 +++++++++++++++++++ DBO/mdctdc.vhd | 335 ++++++++++++++++++++++++++++++++ DBO/par.p2t | 69 +++++++ pinout/dbo.lpf | 113 +++++++++++ pinout/oep.lpf | 74 +++++++ 10 files changed, 1110 insertions(+) create mode 100644 .gitignore create mode 120000 DBO/compile.pl create mode 100644 DBO/config.vhd create mode 100644 DBO/config_compile_frankfurt.pl create mode 100644 DBO/mdctdc.lpf create mode 100644 DBO/mdctdc.prj create mode 100644 DBO/mdctdc.vhd create mode 100644 DBO/par.p2t create mode 100644 pinout/dbo.lpf create mode 100644 pinout/oep.lpf diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b23dea2 --- /dev/null +++ b/.gitignore @@ -0,0 +1,35 @@ +*~ +*.tcl +*.log +*.rpt +netlists +version.vhd +*.jhd +*.naf +*.sort +*.srp +*.sym +*tmpl.vhd +*.log +workdir +workdir_* +*.bit +*.kate-swp* +*.kate-swap* +.run_manager.ini +reportview.xml +.kateproject.d +*/project/ +*/project2/ +modelsim.ini +*.mti +*.bak +work +*.wlf +*stacktrace.txt +*edn +licbug.txt +old +config_compile.pl +._Real_._Math_.vhd +diamond diff --git a/DBO/compile.pl b/DBO/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/DBO/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/DBO/config.vhd b/DBO/config.vhd new file mode 100644 index 0000000..7e82d70 --- /dev/null +++ b/DBO/config.vhd @@ -0,0 +1,104 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant FPGA_SIZE : string := "25KUM"; + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 400; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + constant USE_120_MHZ : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F6DC"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"91"; + + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A6100000"; + + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := 100; + constant MEDIA_FREQUENCY : integer := 200; + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); +-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); +-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := "00"; + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/DBO/config_compile_frankfurt.pl b/DBO/config_compile_frankfurt.pl new file mode 100644 index 0000000..db689d3 --- /dev/null +++ b/DBO/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-25F', +Package => 'CABGA381', +Speedgrade => '8', + + +TOPNAME => "mdctdc", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'dbo', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/DBO/mdctdc.lpf b/DBO/mdctdc.lpf new file mode 100644 index 0000000..74c50ea --- /dev/null +++ b/DBO/mdctdc.lpf @@ -0,0 +1,155 @@ +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK 200 MHz; +FREQUENCY PORT CLK_TDC 156.25 MHz; +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "med2int_0.clk_full" 200 MHz; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + +# +# # UGROUP "INPGATE0" BBOX 1 1 +# # BLKNAME THE_TDC/gen_channels.0.inpgate[0] +# # ; +# # LOCATE UGROUP "INPGATE0" SITE "R14C4D"; +# +# UGROUP "ffarr0groupA" BBOX 3 3 +# BLKNAME THE_TDC/ffarr_0_0 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[8] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[9] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[10] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[11] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[12] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[13] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[14] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[15] +# ; +# LOCATE UGROUP "ffarr0groupA" SITE "R13C2D"; +# UGROUP "ffarr0groupA1" BBOX 1 1 +# BLKNAME THE_TDC/ffarr_0_0 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] +# ; +# LOCATE UGROUP "ffarr0groupA1" SITE "R13C2D"; +# +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[8] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[9] +# +# +# +# UGROUP "ffarr0groupA2" BBOX 1 1 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] +# ; +# LOCATE UGROUP "ffarr0groupA2" SITE "R13C3D"; +# +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[10] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[11] +# +# +# UGROUP "ffarr0groupA3" BBOX 1 1 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] +# ; +# LOCATE UGROUP "ffarr0groupA3" SITE "R14C2D"; +# +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[12] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[13] +# +# +# UGROUP "ffarr0groupA4" BBOX 1 1 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] +# ; +# LOCATE UGROUP "ffarr0groupA4" SITE "R14C3D"; +# +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[14] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[15] + + +# UGROUP "ffarr0groupB" BBOX 3 2 +# BLKNAME THE_TDC/ffarr_1_0 +# BLKNAME THE_TDC/ffarr_2_0 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[7] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[7] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[8] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[8] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[9] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[9] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[10] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[10] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[11] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[11] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[12] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[12] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[13] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[13] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[14] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[14] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[15] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[15] +# ; +# +# +# LOCATE UGROUP "ffarr0groupB" SITE "R14C5D"; + +# +# UGROUP "ffarr0groupAD" BBOX 2 2 +# BLKNAME THE_TDC/ffarr_0_0[0] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] +# ; +# +# UGROUP "ffarr0groupBD" BBOX 2 2 +# BLKNAME THE_TDC/ffarr_1_0[0] +# BLKNAME THE_TDC/ffarr_2_0[0] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[7] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[7] +# ; +# +# LOCATE UGROUP "ffarr0groupAD" SITE "R13C2D"; +# LOCATE UGROUP "ffarr0groupBD" SITE "R13C4D"; diff --git a/DBO/mdctdc.prj b/DBO/mdctdc.prj new file mode 100644 index 0000000..0958775 --- /dev/null +++ b/DBO/mdctdc.prj @@ -0,0 +1,199 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_25F +set_option -package BG381C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "mdctdc" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/mdctdc.edf" +set_option log_file "workdir/mdctdc.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + +add_file -vhdl -lib work "../../dirich/cores/pcs.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + + +add_file -vhdl -lib work "./mdctdc.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/DBO/mdctdc.vhd b/DBO/mdctdc.vhd new file mode 100644 index 0000000..c765f89 --- /dev/null +++ b/DBO/mdctdc.vhd @@ -0,0 +1,335 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity mdctdc is + port( + CLK : in std_logic; + CLK_TDC : in std_logic; + TRG : in std_logic; --Reference Time + + GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + LVDS : in std_logic_vector(1 downto 0); + + OUTP : in std_logic_vector(31 downto 0); + TEST : out std_logic_vector(3 downto 0); + + RSTN : out std_logic_vector(2 downto 1); + MISO : in std_logic_vector(2 downto 1); + MOSI : out std_logic_vector(2 downto 1); + SCK : out std_logic_vector(2 downto 1); + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + FLASH_SELECT : in std_logic; + FLASH_OVERRIDE : out std_logic; + PROGRAMN : out std_logic; + + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + + --LED + LED : out std_logic_vector(2 downto 0) + + --Other Connectors + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of mdctdc is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal bus_master_active : std_logic; + + signal timer : TIMERS; + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1); + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0); + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => GPIO(1), + SD_LOS_IN => GPIO(1), + SD_TXDIS_OUT => GPIO(0), + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRG, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustdc_rx, --Clock switch + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustdc_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT(1 downto 0) => RSTN, + SPI_MOSI_OUT(1 downto 0) => MOSI, + SPI_MISO_IN(1 downto 0) => MISO, + SPI_CLK_OUT(1 downto 0) => SCK, + --Header + HEADER_IO => open, + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => open, + ADC_MOSI => open, + ADC_MISO => open, + ADC_CLK => open, + --Trigger & Monitor + MONITOR_INPUTS => monitor_inputs_i, + TRIG_GEN_INPUTS => trigger_inputs_i, + TRIG_GEN_OUTPUTS(1 downto 0) => GPIO(3 downto 2), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + monitor_inputs_i <= OUTP(MONITOR_INPUT_NUM-1 downto 0); + trigger_inputs_i <= OUTP(TRIG_GEN_INPUT_NUM-1 downto 0); + hit_in_i <= OUTP(NUM_TDC_CHANNELS-2 downto 0); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED(0) <= (med2int(0).stat_op(10) or med2int(0).stat_op(11)) and not led_off; + LED(1) <= med2int(0).stat_op(9) and not led_off; + LED(2) <= FLASH_SELECT and not led_off; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- +-- THE_TDC : entity work.TDC_FF +-- generic map( +-- CHANNELS => 17 +-- ) +-- port map( +-- CLK => CLK_125, +-- SYSCLK => clk_sys, +-- RESET_IN => reset_i, +-- SIGNAL_IN => INP(16 downto 0), +-- +-- BUS_RX => bustdc_rx, +-- BUS_TX => bustdc_tx, +-- +-- READOUT_RX => readout_rx, +-- READOUT_TX => readout_tx +-- +-- ); +-- +-- + + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +readout_tx(0).data_finished <= '1'; +readout_tx(0).data_write <= '0'; +readout_tx(0).busy_release <= '1'; + +end architecture; + + + diff --git a/DBO/par.p2t b/DBO/par.p2t new file mode 100644 index 0000000..9e4ef4d --- /dev/null +++ b/DBO/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 2 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/pinout/dbo.lpf b/pinout/dbo.lpf new file mode 100644 index 0000000..852a60b --- /dev/null +++ b/pinout/dbo.lpf @@ -0,0 +1,113 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=2.5 ; #BACKGROUND_RECONFIG=ON + + +LOCATE COMP "CLK" SITE "G3"; +IOBUF PORT "CLK" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "CLK_TDC" SITE "L20"; +IOBUF PORT "CLK_TDC" IO_TYPE=LVDS DIFFRESISTOR=100 ; + +LOCATE COMP "FLASH_CS" SITE "R2"; +LOCATE COMP "FLASH_HOLD" SITE "W1"; +LOCATE COMP "FLASH_MISO" SITE "V2"; +LOCATE COMP "FLASH_MOSI" SITE "W2"; +LOCATE COMP "FLASH_OVERRIDE" SITE "U1"; +LOCATE COMP "FLASH_SCLK" SITE "U2"; +LOCATE COMP "FLASH_SELECT" SITE "T3"; +LOCATE COMP "FLASH_WP" SITE "Y2"; +DEFINE PORT GROUP "FLASH_group" "FLASH*"; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "PROGRAMN" SITE "V1"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "GPIO_0" SITE "B15"; +LOCATE COMP "GPIO_1" SITE "C15"; +LOCATE COMP "GPIO_2" SITE "A16"; +LOCATE COMP "GPIO_3" SITE "B16"; +DEFINE PORT GROUP "GPIO_group" "GPIO*"; +IOBUF GROUP "GPIO_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "I2C_SCL" SITE "A17"; +LOCATE COMP "I2C_SDA" SITE "A18"; +IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ; +IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_0" SITE "P19"; +LOCATE COMP "LED_1" SITE "T17"; +LOCATE COMP "LED_2" SITE "U16"; +DEFINE PORT GROUP "LED_group" "LED*"; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LVDS_0" SITE "C18"; +LOCATE COMP "LVDS_1" SITE "D18"; +IOBUF PORT "LVDS_0" IO_TYPE=LVDS DIFFRESISTOR=100; +IOBUF PORT "LVDS_1" IO_TYPE=LVDS DIFFRESISTOR=100; + +LOCATE COMP "RSTN_2" SITE "A6"; +LOCATE COMP "SCK_2" SITE "A7"; +LOCATE COMP "MOSI_2" SITE "A9"; +LOCATE COMP "SCK_1" SITE "A10"; +LOCATE COMP "RSTN_1" SITE "A12"; +LOCATE COMP "MOSI_1" SITE "A14"; +LOCATE COMP "MISO_1" SITE "U19"; +LOCATE COMP "MISO_2" SITE "H1"; +IOBUF PORT "RSTN_2" IO_TYPE=LVDS25E; +IOBUF PORT "SCK_2" IO_TYPE=LVDS25E; +IOBUF PORT "MOSI_2" IO_TYPE=LVDS25E; +IOBUF PORT "RSTN_1" IO_TYPE=LVDS25E; +IOBUF PORT "MOSI_1" IO_TYPE=LVDS25E; +IOBUF PORT "SCK_1" IO_TYPE=LVDS25E; +IOBUF PORT "MISO_1" IO_TYPE=LVDS DIFFRESISTOR=100; +IOBUF PORT "MISO_2" IO_TYPE=LVDS DIFFRESISTOR=100; + + + +LOCATE COMP "OUTP_0" SITE "N19"; +LOCATE COMP "OUTP_1" SITE "P20"; +LOCATE COMP "OUTP_2" SITE "T20"; +LOCATE COMP "OUTP_3" SITE "L18"; +LOCATE COMP "OUTP_4" SITE "N18"; +LOCATE COMP "OUTP_5" SITE "U18"; +LOCATE COMP "OUTP_6" SITE "T19"; +LOCATE COMP "OUTP_7" SITE "R16"; +LOCATE COMP "OUTP_8" SITE "G19"; +LOCATE COMP "OUTP_9" SITE "F20"; +LOCATE COMP "OUTP_10" SITE "J20"; +LOCATE COMP "OUTP_11" SITE "E20"; +LOCATE COMP "OUTP_12" SITE "J19"; +LOCATE COMP "OUTP_13" SITE "C20"; +LOCATE COMP "OUTP_14" SITE "L19"; +LOCATE COMP "OUTP_15" SITE "E18"; +LOCATE COMP "OUTP_16" SITE "N3"; +LOCATE COMP "OUTP_17" SITE "N2"; +LOCATE COMP "OUTP_18" SITE "K2"; +LOCATE COMP "OUTP_19" SITE "P1"; +LOCATE COMP "OUTP_20" SITE "L3"; +LOCATE COMP "OUTP_21" SITE "J4"; +LOCATE COMP "OUTP_22" SITE "H2"; +LOCATE COMP "OUTP_23" SITE "G2"; +LOCATE COMP "OUTP_24" SITE "B5"; +LOCATE COMP "OUTP_25" SITE "A4"; +LOCATE COMP "OUTP_26" SITE "F2"; +LOCATE COMP "OUTP_27" SITE "C4"; +LOCATE COMP "OUTP_28" SITE "C1"; +LOCATE COMP "OUTP_29" SITE "A3"; +LOCATE COMP "OUTP_30" SITE "C3"; +LOCATE COMP "OUTP_31" SITE "A2"; +DEFINE PORT GROUP "OUTP_group" "OUTP*"; +IOBUF GROUP "OUTP_group" IO_TYPE=LVDS; + +LOCATE COMP "TRG" SITE "E16"; +IOBUF PORT "TRG" IO_TYPE=LVDS DIFFRESISTOR=100; + + +LOCATE COMP "TEST_0" SITE "B20"; +LOCATE COMP "TEST_1" SITE "B19"; +LOCATE COMP "TEST_2" SITE "D9"; +LOCATE COMP "TEST_3" SITE "C8"; +DEFINE PORT GROUP "Test_group" "TEST*"; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 ; diff --git a/pinout/oep.lpf b/pinout/oep.lpf new file mode 100644 index 0000000..9dad896 --- /dev/null +++ b/pinout/oep.lpf @@ -0,0 +1,74 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=2.5 ; #BACKGROUND_RECONFIG=ON +FREQUENCY PORT CLK 200 MHz; +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; + + +LOCATE COMP "CLK" SITE "A4"; +LOCATE COMP "TRG" SITE "B5"; +IOBUF PORT "CLK" IO_TYPE=LVDS25 DIFFRESISTOR=100; +IOBUF PORT "TRG" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +LOCATE COMP "GPIO_0" SITE "L2"; +LOCATE COMP "GPIO_1" SITE "L3"; +LOCATE COMP "GPIO_2" SITE "M3"; +LOCATE COMP "GPIO_3" SITE "N3"; +LOCATE COMP "GPIO_4" SITE "H1"; +LOCATE COMP "GPIO_5" SITE "G1"; +LOCATE COMP "GPIO_6" SITE "K4"; +LOCATE COMP "GPIO_7" SITE "K1"; +LOCATE COMP "GPIO_8" SITE "D3"; +LOCATE COMP "GPIO_9" SITE "C3"; +LOCATE COMP "GPIO_10" SITE "E3"; +LOCATE COMP "GPIO_11" SITE "F4"; +DEFINE PORT GROUP "GPIO_group" "GPIO*"; +IOBUF GROUP "GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +LOCATE COMP "LVDS_0" SITE "P1"; +LOCATE COMP "LVDS_1" SITE "N2"; +LOCATE COMP "LVDS_2" SITE "K2"; +LOCATE COMP "LVDS_3" SITE "G2"; +LOCATE COMP "LVDS_4" SITE "C1"; +LOCATE COMP "LVDS_5" SITE "A2"; +DEFINE PORT GROUP "LVDS_group" "LVDS*"; +IOBUF GROUP "LVDS_group" IO_TYPE=LVDS DIFFRESISTOR=100; + +LOCATE COMP "FLASH_CS" SITE "R2"; +LOCATE COMP "FLASH_HOLD" SITE "W1"; +LOCATE COMP "FLASH_MISO" SITE "V2"; +LOCATE COMP "FLASH_MOSI" SITE "W2"; +LOCATE COMP "FLASH_OVERRIDE" SITE "U1"; +LOCATE COMP "FLASH_SCLK" SITE "U3"; +LOCATE COMP "FLASH_SELECT" SITE "T1"; +LOCATE COMP "FLASH_WP" SITE "Y2"; +DEFINE PORT GROUP "FLASH_group" "FLASH*"; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "FPGA_REPROGRAM" SITE "V1"; +IOBUF PORT "FPGA_REPROGRAM" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "I2C_SCL" SITE "A14"; +LOCATE COMP "I2C_SDA" SITE "A13"; +IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ; +IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_0" SITE "C20"; +LOCATE COMP "LED_1" SITE "D20"; +LOCATE COMP "LED_2" SITE "E20"; +LOCATE COMP "LED_3" SITE "F20"; +LOCATE COMP "LED_4" SITE "G20"; +LOCATE COMP "LED_5" SITE "H20"; +LOCATE COMP "LED_6" SITE "J20"; +LOCATE COMP "LED_7" SITE "K20"; +DEFINE PORT GROUP "LED_group" "LED*"; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "TMP_ALERT" SITE "A12"; +IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 PULLMODE=UP; + + -- 2.43.0