From df7870ea9900f1055095a697884d07ce2c14e6a1 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 5 Dec 2011 22:13:20 +0000 Subject: [PATCH] update --- trb3_gbe/trb3_central.lpf | 505 ++++++++++++++++++++++ trb3_gbe/trb3_central.prj | 202 +++++++++ trb3_gbe/trb3_central.vhd | 886 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 1593 insertions(+) create mode 100644 trb3_gbe/trb3_central.lpf create mode 100644 trb3_gbe/trb3_central.prj create mode 100644 trb3_gbe/trb3_central.vhd diff --git a/trb3_gbe/trb3_central.lpf b/trb3_gbe/trb3_central.lpf new file mode 100644 index 0000000..2e34a50 --- /dev/null +++ b/trb3_gbe/trb3_central.lpf @@ -0,0 +1,505 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + + SYSCONFIG MCCLK_FREQ = 20; + + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; + FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; + FREQUENCY PORT CLK_EXT_3 10 MHz; + FREQUENCY PORT CLK_EXT_4 10 MHz; + + +################################################################# +# Clock I/O +################################################################# + +#Additional signals from Clock-RJ-45 +LOCATE COMP "CLK_EXT_3" SITE "U9"; #was SPARE_LINE_2 +LOCATE COMP "CLK_EXT_4" SITE "Y34"; #was SPARE_LINE_4 +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AH22"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AH12"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "Y28"; +LOCATE COMP "CLK_GPLL_LEFT" SITE "Y9"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "V9"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U28"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25; + +LOCATE COMP "ENPIRION_CLOCK" SITE "G18"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4; + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_RIGHT" SITE "W30"; +IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; +LOCATE COMP "TRIGGER_LEFT" SITE "Y2"; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; + +#To fan-out to all FPGA +LOCATE COMP "TRIGGER_OUT" SITE "V7"; +IOBUF PORT "TRIGGER_OUT" IO_TYPE=LVDS25 ; + +#Additional lines on Trigger-RJ-45 +LOCATE COMP "TRIGGER_EXT_2" SITE "W2"; +LOCATE COMP "TRIGGER_EXT_3" SITE "W8"; #was EXT_TRIG_2 +LOCATE COMP "TRIGGER_EXT_4" SITE "W4"; #was EXT_TRIG_4 +DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ; +IOBUF GROUP "TRIGGER_EXT_group" IO_TYPE=LVDS25; + + +################################################################# +# Clock and Trigger Select +################################################################# +#Trigger select for fan-out. 0: external trigger. 1: TRIGGER_OUT +LOCATE COMP "TRIGGER_SELECT" SITE "AA31"; +IOBUF PORT "TRIGGER_SELECT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4 ; + +LOCATE COMP "CLK_MNGR1_USER_0" SITE "AA28"; +LOCATE COMP "CLK_MNGR1_USER_1" SITE "AA27"; +LOCATE COMP "CLK_MNGR1_USER_2" SITE "AB32"; +LOCATE COMP "CLK_MNGR1_USER_3" SITE "AB31"; +LOCATE COMP "CLK_MNGR2_USER_0" SITE "AE34"; +LOCATE COMP "CLK_MNGR2_USER_1" SITE "AE33"; +LOCATE COMP "CLK_MNGR2_USER_2" SITE "AB26"; +LOCATE COMP "CLK_MNGR2_USER_3" SITE "AB25"; +DEFINE PORT GROUP "CLK_MNGR_group" "CLK_MNGR*" ; +IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + +LOCATE COMP "CLOCK_SELECT" SITE "AA30"; +IOBUF PORT "CLOCK_SELECT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4 ; + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "A17"; +LOCATE COMP "LED_ORANGE" SITE "B17"; +LOCATE COMP "LED_RED" SITE "E19"; +LOCATE COMP "LED_YELLOW" SITE "E20"; +IOBUF PORT "LED_GREEN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_ORANGE" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_RED" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_YELLOW" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8; + +LOCATE COMP "LED_TRIGGER_GREEN" SITE "AP5"; +LOCATE COMP "LED_TRIGGER_RED" SITE "AP6"; +LOCATE COMP "LED_CLOCK_GREEN" SITE "AL4"; +LOCATE COMP "LED_CLOCK_RED" SITE "AM4"; +IOBUF PORT "LED_TRIGGER_GREEN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_TRIGGER_RED" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_CLOCK_GREEN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_CLOCK_RED" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; + +################################################################# +# Inter-FPGA Connection +################################################################# +LOCATE COMP "FPGA1_COMM_0" SITE "AC9"; +LOCATE COMP "FPGA1_COMM_10" SITE "AJ1"; +LOCATE COMP "FPGA1_COMM_11" SITE "AK1"; +LOCATE COMP "FPGA1_COMM_1" SITE "AC8"; +LOCATE COMP "FPGA1_COMM_2" SITE "AE2"; +LOCATE COMP "FPGA1_COMM_3" SITE "AE1"; +LOCATE COMP "FPGA1_COMM_4" SITE "AE4"; +LOCATE COMP "FPGA1_COMM_5" SITE "AE3"; +LOCATE COMP "FPGA1_COMM_6" SITE "AB10"; +LOCATE COMP "FPGA1_COMM_7" SITE "AC10"; +LOCATE COMP "FPGA1_COMM_8" SITE "AD4"; +LOCATE COMP "FPGA1_COMM_9" SITE "AD3"; + +LOCATE COMP "FPGA2_COMM_0" SITE "P5"; +LOCATE COMP "FPGA2_COMM_10" SITE "M10"; +LOCATE COMP "FPGA2_COMM_11" SITE "N10"; +LOCATE COMP "FPGA2_COMM_1" SITE "P4"; +LOCATE COMP "FPGA2_COMM_2" SITE "N8"; +LOCATE COMP "FPGA2_COMM_3" SITE "P8"; +LOCATE COMP "FPGA2_COMM_4" SITE "M5"; +LOCATE COMP "FPGA2_COMM_5" SITE "N5"; +LOCATE COMP "FPGA2_COMM_6" SITE "R7"; +LOCATE COMP "FPGA2_COMM_7" SITE "R5"; +LOCATE COMP "FPGA2_COMM_8" SITE "N2"; +LOCATE COMP "FPGA2_COMM_9" SITE "N1"; + +LOCATE COMP "FPGA3_COMM_0" SITE "AC28"; +LOCATE COMP "FPGA3_COMM_10" SITE "AF32"; +LOCATE COMP "FPGA3_COMM_11" SITE "AF31"; +LOCATE COMP "FPGA3_COMM_1" SITE "AB27"; +LOCATE COMP "FPGA3_COMM_2" SITE "AE32"; +LOCATE COMP "FPGA3_COMM_3" SITE "AE31"; +LOCATE COMP "FPGA3_COMM_4" SITE "AE30"; +LOCATE COMP "FPGA3_COMM_5" SITE "AE29"; +LOCATE COMP "FPGA3_COMM_6" SITE "AC25"; +LOCATE COMP "FPGA3_COMM_7" SITE "AC26"; +LOCATE COMP "FPGA3_COMM_8" SITE "AD26"; +LOCATE COMP "FPGA3_COMM_9" SITE "AD25"; + +LOCATE COMP "FPGA4_COMM_0" SITE "AN32"; +LOCATE COMP "FPGA4_COMM_10" SITE "AM29"; +LOCATE COMP "FPGA4_COMM_11" SITE "AN29"; +LOCATE COMP "FPGA4_COMM_1" SITE "AM32"; +LOCATE COMP "FPGA4_COMM_2" SITE "AP29"; +LOCATE COMP "FPGA4_COMM_3" SITE "AP30"; +LOCATE COMP "FPGA4_COMM_4" SITE "AL30"; +LOCATE COMP "FPGA4_COMM_5" SITE "AM30"; +LOCATE COMP "FPGA4_COMM_6" SITE "AL31"; +LOCATE COMP "FPGA4_COMM_7" SITE "AM31"; +LOCATE COMP "FPGA4_COMM_8" SITE "AP31"; +LOCATE COMP "FPGA4_COMM_9" SITE "AN31"; + + +################################################################# +# Connection to small AddOns +################################################################# +LOCATE COMP "FPGA1_CONNECTOR_0" SITE "AN1"; +LOCATE COMP "FPGA1_CONNECTOR_1" SITE "AN2"; +LOCATE COMP "FPGA1_CONNECTOR_2" SITE "AD9"; +LOCATE COMP "FPGA1_CONNECTOR_3" SITE "AD8"; +LOCATE COMP "FPGA1_CONNECTOR_4" SITE "AP2"; +LOCATE COMP "FPGA1_CONNECTOR_5" SITE "AP3"; +LOCATE COMP "FPGA1_CONNECTOR_6" SITE "AJ2"; +LOCATE COMP "FPGA1_CONNECTOR_7" SITE "AJ3"; + +LOCATE COMP "FPGA2_CONNECTOR_0" SITE "P9"; +LOCATE COMP "FPGA2_CONNECTOR_1" SITE "P10"; +LOCATE COMP "FPGA2_CONNECTOR_2" SITE "R2"; +LOCATE COMP "FPGA2_CONNECTOR_3" SITE "R1"; +LOCATE COMP "FPGA2_CONNECTOR_4" SITE "P7"; +LOCATE COMP "FPGA2_CONNECTOR_5" SITE "P6"; +LOCATE COMP "FPGA2_CONNECTOR_6" SITE "R4"; +LOCATE COMP "FPGA2_CONNECTOR_7" SITE "R3"; + +LOCATE COMP "FPGA3_CONNECTOR_0" SITE "AN34"; +LOCATE COMP "FPGA3_CONNECTOR_1" SITE "AN33"; +LOCATE COMP "FPGA3_CONNECTOR_2" SITE "AH33"; +LOCATE COMP "FPGA3_CONNECTOR_3" SITE "AJ33"; +LOCATE COMP "FPGA3_CONNECTOR_4" SITE "AP33"; +LOCATE COMP "FPGA3_CONNECTOR_5" SITE "AP32"; +LOCATE COMP "FPGA3_CONNECTOR_6" SITE "AL34"; +LOCATE COMP "FPGA3_CONNECTOR_7" SITE "AL33"; + +LOCATE COMP "FPGA4_CONNECTOR_0" SITE "AK27"; +LOCATE COMP "FPGA4_CONNECTOR_1" SITE "AJ27"; +LOCATE COMP "FPGA4_CONNECTOR_2" SITE "AK28"; +LOCATE COMP "FPGA4_CONNECTOR_3" SITE "AJ28"; +LOCATE COMP "FPGA4_CONNECTOR_4" SITE "AH27"; +LOCATE COMP "FPGA4_CONNECTOR_5" SITE "AH28"; +LOCATE COMP "FPGA4_CONNECTOR_6" SITE "AL29"; +LOCATE COMP "FPGA4_CONNECTOR_7" SITE "AK29"; + +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +LOCATE COMP "FPGA1_TTL_0" SITE "J21"; #202 #was F1_3V3_LINE etc. +LOCATE COMP "FPGA1_TTL_1" SITE "H22"; #204 +LOCATE COMP "FPGA1_TTL_2" SITE "A23"; #206 +LOCATE COMP "FPGA1_TTL_3" SITE "B23"; #208 +LOCATE COMP "FPGA2_TTL_0" SITE "E22"; #202 +LOCATE COMP "FPGA2_TTL_1" SITE "E23"; #204 +LOCATE COMP "FPGA2_TTL_2" SITE "C23"; #206 +LOCATE COMP "FPGA2_TTL_3" SITE "D23"; #208 +LOCATE COMP "FPGA3_TTL_0" SITE "K22"; #202 +LOCATE COMP "FPGA3_TTL_1" SITE "K21"; #204 +LOCATE COMP "FPGA3_TTL_2" SITE "A24"; #206 +LOCATE COMP "FPGA3_TTL_3" SITE "B24"; #208 +LOCATE COMP "FPGA4_TTL_0" SITE "G23"; #202 +LOCATE COMP "FPGA4_TTL_1" SITE "H23"; #204 +LOCATE COMP "FPGA4_TTL_2" SITE "D24"; #206 +LOCATE COMP "FPGA4_TTL_3" SITE "E24"; #208 +DEFINE PORT GROUP "FPGATTL_group" "*TTL*" ; +IOBUF GROUP "FPGATTL_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=8; + +################################################################# +# SFP Control / Status +################################################################# +LOCATE COMP "SFP_TX_FAULT_1" SITE "K23"; +LOCATE COMP "SFP_TX_FAULT_2" SITE "D21"; +LOCATE COMP "SFP_TX_FAULT_3" SITE "H19"; +LOCATE COMP "SFP_TX_FAULT_4" SITE "A18"; +LOCATE COMP "SFP_TX_FAULT_5" SITE "D25"; +LOCATE COMP "SFP_TX_FAULT_6" SITE "D27"; +LOCATE COMP "SFP_TX_FAULT_7" SITE "D20"; +LOCATE COMP "SFP_TX_FAULT_8" SITE "J19"; +LOCATE COMP "SFP_RATE_SEL_1" SITE "C25"; +LOCATE COMP "SFP_RATE_SEL_2" SITE "J22"; +LOCATE COMP "SFP_RATE_SEL_3" SITE "D19"; +LOCATE COMP "SFP_RATE_SEL_4" SITE "G19"; +LOCATE COMP "SFP_RATE_SEL_5" SITE "C27"; +LOCATE COMP "SFP_RATE_SEL_6" SITE "A29"; +LOCATE COMP "SFP_RATE_SEL_7" SITE "E16"; +LOCATE COMP "SFP_RATE_SEL_8" SITE "C20"; +LOCATE COMP "SFP_LOS_1" SITE "K24"; +LOCATE COMP "SFP_LOS_2" SITE "E21"; +LOCATE COMP "SFP_LOS_3" SITE "A19"; +LOCATE COMP "SFP_LOS_4" SITE "B18"; +LOCATE COMP "SFP_LOS_5" SITE "G26"; +LOCATE COMP "SFP_LOS_6" SITE "E27"; +LOCATE COMP "SFP_LOS_7" SITE "F21"; +LOCATE COMP "SFP_LOS_8" SITE "K19"; +LOCATE COMP "SFP_TXDIS_1" SITE "A25"; +LOCATE COMP "SFP_TXDIS_2" SITE "H20"; +LOCATE COMP "SFP_TXDIS_3" SITE "B19"; +LOCATE COMP "SFP_TXDIS_4" SITE "J18"; +LOCATE COMP "SFP_TXDIS_5" SITE "G25"; +LOCATE COMP "SFP_TXDIS_6" SITE "B28"; +LOCATE COMP "SFP_TXDIS_7" SITE "F22"; +LOCATE COMP "SFP_TXDIS_8" SITE "A20"; +LOCATE COMP "SFP_MOD0_1" SITE "B25"; +LOCATE COMP "SFP_MOD0_2" SITE "J20"; +LOCATE COMP "SFP_MOD0_3" SITE "K20"; +LOCATE COMP "SFP_MOD0_4" SITE "H18"; +LOCATE COMP "SFP_MOD0_5" SITE "C26"; +LOCATE COMP "SFP_MOD0_6" SITE "A28"; +LOCATE COMP "SFP_MOD0_7" SITE "A21"; +LOCATE COMP "SFP_MOD0_8" SITE "B20"; +LOCATE COMP "SFP_MOD1_1" SITE "C28"; +LOCATE COMP "SFP_MOD1_2" SITE "A22"; +LOCATE COMP "SFP_MOD1_3" SITE "L19"; +LOCATE COMP "SFP_MOD1_4" SITE "D18"; +LOCATE COMP "SFP_MOD1_5" SITE "D26"; +LOCATE COMP "SFP_MOD1_6" SITE "A26"; +LOCATE COMP "SFP_MOD1_7" SITE "B21"; +LOCATE COMP "SFP_MOD1_8" SITE "G20"; +LOCATE COMP "SFP_MOD2_1" SITE "D28"; +LOCATE COMP "SFP_MOD2_2" SITE "B22"; +LOCATE COMP "SFP_MOD2_3" SITE "C19"; +LOCATE COMP "SFP_MOD2_4" SITE "E18"; +LOCATE COMP "SFP_MOD2_5" SITE "B27"; +LOCATE COMP "SFP_MOD2_6" SITE "A27"; +LOCATE COMP "SFP_MOD2_7" SITE "F16"; +LOCATE COMP "SFP_MOD2_8" SITE "G21"; + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 PULLMODE=UP; + +################################################################# +# Main AddOn Connector +################################################################# + +LOCATE COMP "ADDON_RESET" SITE "J23"; +IOBUF PORT "ADDON_RESET" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; + +LOCATE COMP "ADDON_TO_TRB_CLK" SITE "J17"; +IOBUF PORT "ADDON_TO_TRB_CLK" IO_TYPE=LVDS25 ; + +LOCATE COMP "TRB_TO_ADDON_CLK" SITE "K16"; +IOBUF PORT "TRB_TO_ADDON_CLK" IO_TYPE=LVCMOS25 ; +LOCATE COMP "TRB_TO_ADDON_CLKb" SITE "L16"; +IOBUF PORT "TRB_TO_ADDON_CLKb" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "ADO_LV_0" SITE "D5"; +LOCATE COMP "ADO_LV_1" SITE "C6"; +LOCATE COMP "ADO_LV_2" SITE "A4"; +LOCATE COMP "ADO_LV_3" SITE "A5"; +LOCATE COMP "ADO_LV_4" SITE "B4"; +LOCATE COMP "ADO_LV_5" SITE "A3"; +LOCATE COMP "ADO_LV_6" SITE "B3"; +LOCATE COMP "ADO_LV_7" SITE "A2"; +LOCATE COMP "ADO_LV_8" SITE "B1"; +LOCATE COMP "ADO_LV_9" SITE "B2"; +LOCATE COMP "ADO_LV_10" SITE "C3"; +LOCATE COMP "ADO_LV_11" SITE "C4"; +LOCATE COMP "ADO_LV_12" SITE "D3"; +LOCATE COMP "ADO_LV_13" SITE "C2"; +LOCATE COMP "ADO_LV_14" SITE "E4"; +LOCATE COMP "ADO_LV_15" SITE "D4"; +LOCATE COMP "ADO_LV_16" SITE "D6"; +LOCATE COMP "ADO_LV_17" SITE "C5"; +LOCATE COMP "ADO_LV_18" SITE "B6"; +LOCATE COMP "ADO_LV_19" SITE "A6"; +LOCATE COMP "ADO_LV_20" SITE "B7"; +LOCATE COMP "ADO_LV_21" SITE "A7"; +LOCATE COMP "ADO_LV_22" SITE "B8"; +LOCATE COMP "ADO_LV_23" SITE "C8"; +LOCATE COMP "ADO_LV_24" SITE "A8"; +LOCATE COMP "ADO_LV_25" SITE "A9"; +LOCATE COMP "ADO_LV_26" SITE "K11"; +LOCATE COMP "ADO_LV_27" SITE "J11"; +LOCATE COMP "ADO_LV_28" SITE "D12"; +LOCATE COMP "ADO_LV_29" SITE "E12"; +LOCATE COMP "ADO_LV_30" SITE "A12"; +LOCATE COMP "ADO_LV_31" SITE "B12"; +LOCATE COMP "ADO_LV_32" SITE "A11"; +LOCATE COMP "ADO_LV_33" SITE "B11"; +LOCATE COMP "ADO_LV_34" SITE "A10"; +LOCATE COMP "ADO_LV_35" SITE "B10"; +LOCATE COMP "ADO_LV_36" SITE "C11"; +LOCATE COMP "ADO_LV_37" SITE "D11"; +LOCATE COMP "ADO_LV_38" SITE "D9"; +LOCATE COMP "ADO_LV_39" SITE "C9"; +LOCATE COMP "ADO_LV_40" SITE "E11"; +LOCATE COMP "ADO_LV_41" SITE "F12"; +LOCATE COMP "ADO_LV_42" SITE "F10"; +LOCATE COMP "ADO_LV_43" SITE "E10"; +LOCATE COMP "ADO_LV_44" SITE "G11"; +LOCATE COMP "ADO_LV_45" SITE "G12"; +LOCATE COMP "ADO_LV_46" SITE "H11"; +LOCATE COMP "ADO_LV_47" SITE "H12"; +LOCATE COMP "ADO_LV_48" SITE "J14"; +LOCATE COMP "ADO_LV_49" SITE "H13"; +LOCATE COMP "ADO_LV_50" SITE "J12"; +LOCATE COMP "ADO_LV_51" SITE "K12"; +LOCATE COMP "ADO_LV_52" SITE "K13"; +LOCATE COMP "ADO_LV_53" SITE "J13"; +LOCATE COMP "ADO_LV_54" SITE "K14"; +LOCATE COMP "ADO_LV_55" SITE "K15"; +LOCATE COMP "ADO_LV_56" SITE "E13"; +LOCATE COMP "ADO_LV_57" SITE "F13"; +LOCATE COMP "ADO_LV_58" SITE "G13"; +LOCATE COMP "ADO_LV_59" SITE "H14"; +LOCATE COMP "ADO_LV_60" SITE "A13"; +LOCATE COMP "ADO_LV_61" SITE "B13"; + +DEFINE PORT GROUP "ADO_LV_group" "ADO_LV*" ; +IOBUF GROUP "ADO_LV_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8; + + +LOCATE COMP "ADO_TTL_0" SITE "R26"; +LOCATE COMP "ADO_TTL_1" SITE "R25"; +LOCATE COMP "ADO_TTL_2" SITE "P26"; +LOCATE COMP "ADO_TTL_3" SITE "N26"; +LOCATE COMP "ADO_TTL_4" SITE "M25"; +LOCATE COMP "ADO_TTL_5" SITE "M26"; +LOCATE COMP "ADO_TTL_6" SITE "L26"; +LOCATE COMP "ADO_TTL_7" SITE "P28"; +LOCATE COMP "ADO_TTL_8" SITE "P27"; +LOCATE COMP "ADO_TTL_9" SITE "N27"; +LOCATE COMP "ADO_TTL_10" SITE "M27"; +LOCATE COMP "ADO_TTL_11" SITE "L28"; +LOCATE COMP "ADO_TTL_12" SITE "K29"; +LOCATE COMP "ADO_TTL_13" SITE "K30"; +LOCATE COMP "ADO_TTL_14" SITE "M28"; +LOCATE COMP "ADO_TTL_15" SITE "M29"; +LOCATE COMP "ADO_TTL_16" SITE "L33"; +LOCATE COMP "ADO_TTL_17" SITE "L32"; +LOCATE COMP "ADO_TTL_18" SITE "M30"; +LOCATE COMP "ADO_TTL_19" SITE "N32"; +LOCATE COMP "ADO_TTL_20" SITE "R27"; +LOCATE COMP "ADO_TTL_21" SITE "R28"; +LOCATE COMP "ADO_TTL_22" SITE "N28"; +LOCATE COMP "ADO_TTL_23" SITE "R29"; +LOCATE COMP "ADO_TTL_24" SITE "R30"; +LOCATE COMP "ADO_TTL_25" SITE "R31"; +LOCATE COMP "ADO_TTL_26" SITE "P32"; +LOCATE COMP "ADO_TTL_27" SITE "R34"; +LOCATE COMP "ADO_TTL_28" SITE "P33"; +LOCATE COMP "ADO_TTL_29" SITE "P34"; +LOCATE COMP "ADO_TTL_30" SITE "P30"; +LOCATE COMP "ADO_TTL_31" SITE "N34"; +LOCATE COMP "ADO_TTL_32" SITE "M34"; +LOCATE COMP "ADO_TTL_33" SITE "M31"; +LOCATE COMP "ADO_TTL_34" SITE "M33"; +LOCATE COMP "ADO_TTL_35" SITE "L34"; +LOCATE COMP "ADO_TTL_36" SITE "L31"; +LOCATE COMP "ADO_TTL_37" SITE "K34"; +LOCATE COMP "ADO_TTL_38" SITE "K33"; +LOCATE COMP "ADO_TTL_39" SITE "K32"; +LOCATE COMP "ADO_TTL_40" SITE "K31"; +LOCATE COMP "ADO_TTL_41" SITE "L30"; +LOCATE COMP "ADO_TTL_42" SITE "N33"; +LOCATE COMP "ADO_TTL_43" SITE "N30"; +LOCATE COMP "ADO_TTL_44" SITE "N29"; +LOCATE COMP "ADO_TTL_45" SITE "N31"; +LOCATE COMP "ADO_TTL_46" SITE "P31"; + +DEFINE PORT GROUP "ADO_TTL_group" "ADO_TTL*" ; +IOBUF GROUP "ADO_TTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8; + +LOCATE COMP "FS_PE_0" SITE "T26"; +LOCATE COMP "FS_PE_1" SITE "U26"; +LOCATE COMP "FS_PE_2" SITE "U27"; +LOCATE COMP "FS_PE_3" SITE "U31"; +LOCATE COMP "FS_PE_4" SITE "V33"; +LOCATE COMP "FS_PE_5" SITE "V34"; +LOCATE COMP "FS_PE_6" SITE "U32"; +LOCATE COMP "FS_PE_7" SITE "U34"; +LOCATE COMP "FS_PE_8" SITE "U33"; +LOCATE COMP "FS_PE_9" SITE "T34"; +LOCATE COMP "FS_PE_10" SITE "T33"; +LOCATE COMP "FS_PE_11" SITE "T32"; +LOCATE COMP "FS_PE_12" SITE "T31"; +LOCATE COMP "FS_PE_13" SITE "T30"; +LOCATE COMP "FS_PE_14" SITE "U30"; +LOCATE COMP "FS_PE_15" SITE "T29"; +LOCATE COMP "FS_PE_16" SITE "T28"; +LOCATE COMP "FS_PE_17" SITE "T27"; + +DEFINE PORT GROUP "FS_PE_group" "FS_PE*" ; +IOBUF GROUP "FS_PE_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8; + + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "C30"; +LOCATE COMP "FLASH_CS" SITE "A31"; +LOCATE COMP "FLASH_DIN" SITE "B31"; +LOCATE COMP "FLASH_DOUT" SITE "C29"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "H25"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Test Connector (Order corrected to match pin-out of connector!) +################################################################# +LOCATE COMP "TEST_LINE_4" SITE "G4"; # "TEST_LINE_0" +LOCATE COMP "TEST_LINE_5" SITE "G5"; # "TEST_LINE_1" +LOCATE COMP "TEST_LINE_2" SITE "H5"; # "TEST_LINE_2" +LOCATE COMP "TEST_LINE_3" SITE "H4"; # "TEST_LINE_3" +LOCATE COMP "TEST_LINE_10" SITE "F2"; # "TEST_LINE_4" +LOCATE COMP "TEST_LINE_11" SITE "F1"; # "TEST_LINE_5" +LOCATE COMP "TEST_LINE_6" SITE "F3"; # "TEST_LINE_6" +LOCATE COMP "TEST_LINE_7" SITE "E3"; # "TEST_LINE_7" +LOCATE COMP "TEST_LINE_12" SITE "G2"; # "TEST_LINE_8" +LOCATE COMP "TEST_LINE_13" SITE "G1"; # "TEST_LINE_9" +LOCATE COMP "TEST_LINE_8" SITE "G3"; # "TEST_LINE_10" +LOCATE COMP "TEST_LINE_9" SITE "H3"; # "TEST_LINE_11" +LOCATE COMP "TEST_LINE_14" SITE "H1"; # "TEST_LINE_12" +LOCATE COMP "TEST_LINE_15" SITE "J1"; # "TEST_LINE_13" +LOCATE COMP "TEST_LINE_0" SITE "J3"; # "TEST_LINE_14" +LOCATE COMP "TEST_LINE_1" SITE "H2"; # "TEST_LINE_15" + +LOCATE COMP "TEST_LINE_20" SITE "K4"; # "TEST_LINE_16" +LOCATE COMP "TEST_LINE_21" SITE "K3"; # "TEST_LINE_17" +LOCATE COMP "TEST_LINE_26" SITE "K7"; # "TEST_LINE_18" +LOCATE COMP "TEST_LINE_27" SITE "J6"; # "TEST_LINE_19" +LOCATE COMP "TEST_LINE_16" SITE "K2"; # "TEST_LINE_20" +LOCATE COMP "TEST_LINE_17" SITE "K1"; # "TEST_LINE_21" +LOCATE COMP "TEST_LINE_30" SITE "L10"; # "TEST_LINE_22" +LOCATE COMP "TEST_LINE_31" SITE "L9"; # "TEST_LINE_23" +LOCATE COMP "TEST_LINE_18" SITE "L2"; # "TEST_LINE_24" +LOCATE COMP "TEST_LINE_19" SITE "L1"; # "TEST_LINE_25" +LOCATE COMP "TEST_LINE_28" SITE "M8"; # "TEST_LINE_26" +LOCATE COMP "TEST_LINE_29" SITE "L7"; # "TEST_LINE_27" +LOCATE COMP "TEST_LINE_22" SITE "L5"; # "TEST_LINE_28" +LOCATE COMP "TEST_LINE_23" SITE "L4"; # "TEST_LINE_29" +LOCATE COMP "TEST_LINE_24" SITE "K6"; # "TEST_LINE_30" +LOCATE COMP "TEST_LINE_25" SITE "K5"; # "TEST_LINE_31" + +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "D22"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + + + + + diff --git a/trb3_gbe/trb3_central.prj b/trb3_gbe/trb3_central.prj new file mode 100644 index 0000000..0033dd1 --- /dev/null +++ b/trb3_gbe/trb3_central.prj @@ -0,0 +1,202 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_central" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_central.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" + +#gbe files +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" + + +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd" + +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/mb_mac_sim.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_mac_memory.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd" + +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd" + +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd" + +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.vhd" + +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd" + +add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v" +add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v" +add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v" +add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v" +add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v" + + +#trbnet and base files + +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" + + +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf4.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf3.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" + + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo_dualclock_width_16_reg.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd" + +add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "./trb3_central.vhd" + + + + diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd new file mode 100644 index 0000000..15cfd0f --- /dev/null +++ b/trb3_gbe/trb3_central.vhd @@ -0,0 +1,886 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; +use work.trb_net_gbe_components.all; + + + +entity trb3_central is + generic ( + USE_ETHERNET : integer range c_NO to c_YES := c_YES + ); + port( + --Clocks + CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45 + CLK_GPLL_LEFT : in std_logic; --Clock Manager 2/9, 200 MHz <-- MAIN CLOCK + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 1/9, 125 MHz <-- for GbE + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz + + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45 + TRIGGER_OUT : out std_logic; --trigger to second input of fan-out + + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible + + --SFP + SFP_RX_P : in std_logic_vector(16 downto 1); + SFP_RX_N : in std_logic_vector(16 downto 1); + SFP_TX_P : out std_logic_vector(16 downto 1); + SFP_TX_N : out std_logic_vector(16 downto 1); + SFP_TX_FAULT : in std_logic_vector(8 downto 1); --TX broken + SFP_RATE_SEL : out std_logic_vector(8 downto 1); --not supported by our SFP + SFP_LOS : in std_logic_vector(8 downto 1); --Loss of signal + SFP_MOD0 : in std_logic_vector(8 downto 1); --SFP present + SFP_MOD1 : in std_logic_vector(8 downto 1); --I2C interface + SFP_MOD2 : in std_logic_vector(8 downto 1); --I2C interface + SFP_TXDIS : out std_logic_vector(8 downto 1); --disable TX + + --Clock and Trigger Control + TRIGGER_SELECT : out std_logic; --trigger select for fan-out. 0: external, 1: signal from FPGA5 + CLOCK_SELECT : out std_logic; --clock select for fan-out. 0: 200MHz, 1: external from RJ45 + CLK_MNGR1_USER : inout std_logic_vector(3 downto 0); --I/O lines to clock manager 1 + CLK_MNGR2_USER : inout std_logic_vector(3 downto 0); --I/O lines to clock manager 1 + + --Inter-FPGA Communication + FPGA1_COMM : inout std_logic_vector(11 downto 0); + FPGA2_COMM : inout std_logic_vector(11 downto 0); + FPGA3_COMM : inout std_logic_vector(11 downto 0); + FPGA4_COMM : inout std_logic_vector(11 downto 0); + -- on all FPGAn_COMM: --Bit 0/1 output, serial link TX active + --Bit 2/3 input, serial link RX active + --others yet undefined + FPGA1_TTL : inout std_logic_vector(3 downto 0); + FPGA2_TTL : inout std_logic_vector(3 downto 0); + FPGA3_TTL : inout std_logic_vector(3 downto 0); + FPGA4_TTL : inout std_logic_vector(3 downto 0); + --only for not timing-sensitive signals + + --Communication to small addons + FPGA1_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 2-3: LED for SFP3/4 + FPGA2_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 2-3: LED for SFP7/8 + FPGA3_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 0-1: LED for SFP5/6 + FPGA4_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 0-1: LED for SFP1/2 + --Bit 0-3 connected to LED by default, two on each side + + --Big AddOn connector + ADDON_RESET : out std_logic; --reset signal to AddOn + ADDON_TO_TRB_CLK : in std_logic; --Clock from AddOn, connected to PCLK input + TRB_TO_ADDON_CLK : out std_logic; --Clock sent to AddOn + ADO_LV : inout std_logic_vector(61 downto 0); + ADO_TTL : inout std_logic_vector(46 downto 0); + FS_PE : inout std_logic_vector(17 downto 0); + + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_CIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic := '1'; --reboot FPGA + + --Misc + ENPIRION_CLOCK : out std_logic; --Clock for power supply, not necessary, floating + TEMPSENS : inout std_logic; --Temperature Sensor + LED_CLOCK_GREEN : out std_logic; + LED_CLOCK_RED : out std_logic; + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_TRIGGER_GREEN : out std_logic; + LED_TRIGGER_RED : out std_logic; + LED_YELLOW : out std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(31 downto 0) + ); + + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_CLOCK_GREEN : signal is false; + attribute syn_useioff of LED_CLOCK_RED : signal is false; + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_TRIGGER_GREEN : signal is false; + attribute syn_useioff of LED_TRIGGER_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of FPGA1_TTL : signal is false; + attribute syn_useioff of FPGA2_TTL : signal is false; + attribute syn_useioff of FPGA3_TTL : signal is false; + attribute syn_useioff of FPGA4_TTL : signal is false; + attribute syn_useioff of SFP_TXDIS : signal is false; + + --important signals _with_ IO-FF + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_CIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA1_COMM : signal is true; + attribute syn_useioff of FPGA2_COMM : signal is true; + attribute syn_useioff of FPGA3_COMM : signal is true; + attribute syn_useioff of FPGA4_COMM : signal is true; + + +end entity; + +architecture trb3_central_arch of trb3_central is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --FPGA Test + signal time_counter, time_counter2 : unsigned(31 downto 0); + + --Media Interface + signal med_stat_op : std_logic_vector (5*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (5*16-1 downto 0); + signal med_stat_debug : std_logic_vector (5*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (5*64-1 downto 0); + signal med_data_out : std_logic_vector (5*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (5*3-1 downto 0); + signal med_dataready_out : std_logic_vector (5*1-1 downto 0); + signal med_read_out : std_logic_vector (5*1-1 downto 0); + signal med_data_in : std_logic_vector (5*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (5*3-1 downto 0); + signal med_dataready_in : std_logic_vector (5*1-1 downto 0); + signal med_read_in : std_logic_vector (5*1-1 downto 0); + + --Hub + signal common_stat_regs : std_logic_vector (std_COMSTATREG*32-1 downto 0); + signal common_ctrl_regs : std_logic_vector (std_COMCTRLREG*32-1 downto 0); + signal my_address : std_logic_vector (16-1 downto 0); + signal regio_addr_out : std_logic_vector (16-1 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (32-1 downto 0); + signal regio_data_in : std_logic_vector (32-1 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + signal cts_number : std_logic_vector(15 downto 0); + signal cts_code : std_logic_vector(7 downto 0); + signal cts_information : std_logic_vector(7 downto 0); + signal cts_start_readout : std_logic; + signal cts_readout_type : std_logic_vector(3 downto 0); + signal cts_data : std_logic_vector(31 downto 0); + signal cts_dataready : std_logic; + signal cts_readout_finished : std_logic; + signal cts_read : std_logic; + signal cts_length : std_logic_vector(15 downto 0); + signal cts_status_bits : std_logic_vector(31 downto 0); + signal fee_data : std_logic_vector(15 downto 0); + signal fee_dataready : std_logic; + signal fee_read : std_logic; + signal fee_status_bits : std_logic_vector(31 downto 0); + signal fee_busy : std_logic; + +signal stage_stat_regs : std_logic_vector (31 downto 0); +signal stage_ctrl_regs : std_logic_vector (31 downto 0); + +signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0); +signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0); +signal mb_stat_reg_read : std_logic; +signal mb_stat_reg_write : std_logic; +signal mb_stat_reg_ack : std_logic; +signal mb_ip_mem_addr : std_logic_vector(15 downto 0); -- only [7:0] in used +signal mb_ip_mem_data_wr : std_logic_vector(31 downto 0); +signal mb_ip_mem_data_rd : std_logic_vector(31 downto 0); +signal mb_ip_mem_read : std_logic; +signal mb_ip_mem_write : std_logic; +signal mb_ip_mem_ack : std_logic; +signal ip_cfg_mem_clk : std_logic; +signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); +signal ip_cfg_mem_data : std_logic_vector(31 downto 0); +signal ctrl_reg_addr : std_logic_vector(15 downto 0); +signal gbe_stp_reg_addr : std_logic_vector(15 downto 0); +signal gbe_stp_data : std_logic_vector(31 downto 0); +signal gbe_stp_reg_ack : std_logic; +signal gbe_stp_reg_data_wr : std_logic_vector(31 downto 0); +signal gbe_stp_reg_read : std_logic; +signal gbe_stp_reg_write : std_logic; +signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0); + +signal debug : std_logic_vector(63 downto 0); + +signal next_reset, make_reset_via_network_q : std_logic; +signal reset_counter : std_logic_vector(11 downto 0); +signal link_ok : std_logic; + +signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); +signal gsc_init_read, gsc_reply_read : std_logic; +signal gsc_init_dataready, gsc_reply_dataready : std_logic; +signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); +signal mc_unique_id : std_logic_vector(63 downto 0); + + +begin + +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + +GSR_N <= pll_lock; + +THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(4*16+13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- +THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_LEFT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + +--------------------------------------------------------------------------- +-- The TrbNet media interface (Uplink) +--------------------------------------------------------------------------- +THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 0, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES --run on 200 MHz clock + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out(79 downto 64), + MED_PACKET_NUM_IN => med_packet_num_out(14 downto 12), + MED_DATAREADY_IN => med_dataready_out(4), + MED_READ_OUT => med_read_in(4), + MED_DATA_OUT => med_data_in(79 downto 64), + MED_PACKET_NUM_OUT => med_packet_num_in(14 downto 12), + MED_DATAREADY_OUT => med_dataready_in(4), + MED_READ_IN => med_read_out(4), + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SFP_RX_P(1), + SD_RXD_N_IN => SFP_RX_N(1), + SD_TXD_P_OUT => SFP_TX_P(1), + SD_TXD_N_OUT => SFP_TX_N(1), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => SFP_MOD0(1), + SD_LOS_IN => SFP_LOS(1), + SD_TXDIS_OUT => SFP_TXDIS(1), + -- Status and control port + STAT_OP => med_stat_op(79 downto 64), + CTRL_OP => med_ctrl_op(79 downto 64), + STAT_DEBUG => med_stat_debug(4*64+63 downto 4*64), + CTRL_DEBUG => (others => '0') + ); + + +SFP_TXDIS(4 downto 2) <= (others => '1'); +SFP_TXDIS(8 downto 6) <= (others => '1'); + + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- +THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out(63 downto 0), + MED_PACKET_NUM_IN => med_packet_num_out(11 downto 0), + MED_DATAREADY_IN => med_dataready_out(3 downto 0), + MED_READ_OUT => med_read_in(3 downto 0), + MED_DATA_OUT => med_data_in(63 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_in(11 downto 0), + MED_DATAREADY_OUT => med_dataready_in(3 downto 0), + MED_READ_IN => med_read_out(3 downto 0), + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SFP_RX_P(12 downto 9), + SD_RXD_N_IN => SFP_RX_N(12 downto 9), + SD_TXD_P_OUT => SFP_TX_P(12 downto 9), + SD_TXD_N_OUT => SFP_TX_N(12 downto 9), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN(0) => FPGA1_COMM(2), + SD_PRSNT_N_IN(1) => FPGA2_COMM(2), + SD_PRSNT_N_IN(2) => FPGA3_COMM(2), + SD_PRSNT_N_IN(3) => FPGA4_COMM(2), + SD_LOS_IN(0) => FPGA1_COMM(2), + SD_LOS_IN(1) => FPGA2_COMM(2), + SD_LOS_IN(2) => FPGA3_COMM(2), + SD_LOS_IN(3) => FPGA4_COMM(2), + SD_TXDIS_OUT(0) => FPGA1_COMM(0), + SD_TXDIS_OUT(1) => FPGA2_COMM(0), + SD_TXDIS_OUT(2) => FPGA3_COMM(0), + SD_TXDIS_OUT(3) => FPGA4_COMM(0), + -- Status and control port + STAT_OP => med_stat_op(63 downto 0), + CTRL_OP => med_ctrl_op(63 downto 0), + STAT_DEBUG => med_stat_debug(3*64+63 downto 0*64), + CTRL_DEBUG => (others => '0') + ); + + + +--------------------------------------------------------------------------- +-- The TrbNet Hub +--------------------------------------------------------------------------- +gen_normal_hub : if USE_ETHERNET = c_NO generate + + THE_HUB : trb_net16_hub_base + generic map ( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + MII_NUMBER => 5, + MII_IS_UPLINK => (4 => 1, others => 0), + MII_IS_DOWNLINK => (4 => 0, others => 1), + MII_IS_UPLINK_ONLY=> (4 => 1, others => 0), + INT_NUMBER => 0, + INT_CHANNELS => (0,1,3,3,3,3,3,3), + USE_ONEWIRE => c_YES, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + HARDWARE_VERSION => x"90000000", + INIT_ENDPOINT_ID => x"0005", + INIT_ADDRESS => x"F305", + BROADCAST_SPECIAL_ADDR => x"40" + ) + port map ( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + + --Media interfacces + MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out, + MED_DATA_OUT(5*16-1 downto 0) => med_data_out, + MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out, + MED_READ_IN(5*1-1 downto 0) => med_read_in, + MED_DATAREADY_IN(5*1-1 downto 0) => med_dataready_in, + MED_DATA_IN(5*16-1 downto 0) => med_data_in, + MED_PACKET_NUM_IN(5*3-1 downto 0) => med_packet_num_in, + MED_READ_OUT(5*1-1 downto 0) => med_read_out, + MED_STAT_OP(5*16-1 downto 0) => med_stat_op, + MED_CTRL_OP(5*16-1 downto 0) => med_ctrl_op, + + COMMON_STAT_REGS => common_stat_regs, + COMMON_CTRL_REGS => common_ctrl_regs, + MY_ADDRESS_OUT => my_address, + --REGIO INTERFACE + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + + ONEWIRE => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => open + ); +end generate; + +gen_ethernet_hub : if USE_ETHERNET = c_YES generate + + THE_HUB: trb_net16_hub_streaming_port_sctrl + generic map( + --HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + --IBUF_SECURE_MODE => c_YES, + INIT_ADDRESS => x"F305", + MII_NUMBER => 5, + MII_IS_UPLINK => (4 => 1, others => 1), + MII_IS_DOWNLINK => (4 => 0, others => 1), + MII_IS_UPLINK_ONLY => (4 => 1, others => 0), + USE_ONEWIRE => c_YES, + HARDWARE_VERSION => x"90000000", + INIT_ENDPOINT_ID => x"0005", + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + + --Media interfacces +-- MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), +-- MED_DATA_OUT => med_data_out(mii*16-1 downto 0), +-- MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0), +-- MED_READ_IN => med_read_in(mii-1 downto 0), +-- MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), +-- MED_DATA_IN => med_data_in(mii*16-1 downto 0), +-- MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), +-- MED_READ_OUT => med_read_out(mii-1 downto 0), +-- MED_STAT_OP => med_stat_op(mii*16-1 downto 0), +-- MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0), + + MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out, + MED_DATA_OUT(5*16-1 downto 0) => med_data_out, + MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out, + MED_READ_IN(5*1-1 downto 0) => med_read_in, + MED_DATAREADY_IN(5*1-1 downto 0) => med_dataready_in, + MED_DATA_IN(5*16-1 downto 0) => med_data_in, + MED_PACKET_NUM_IN(5*3-1 downto 0) => med_packet_num_in, + MED_READ_OUT(5*1-1 downto 0) => med_read_out, + MED_STAT_OP(5*16-1 downto 0) => med_stat_op, + MED_CTRL_OP(5*16-1 downto 0) => med_ctrl_op, + + --Event information coming from CTSCTS_READOUT_TYPE_OUT + CTS_NUMBER_OUT => cts_number, + CTS_CODE_OUT => cts_code, + CTS_INFORMATION_OUT => cts_information, + CTS_READOUT_TYPE_OUT => cts_readout_type, + CTS_START_READOUT_OUT => cts_start_readout, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_IN => cts_data, + CTS_DATAREADY_IN => cts_dataready, + CTS_READOUT_FINISHED_IN => cts_readout_finished, + CTS_READ_OUT => cts_read, + CTS_LENGTH_IN => cts_length, + CTS_STATUS_BITS_IN => cts_status_bits, + -- Data from Frontends + FEE_DATA_OUT => fee_data, + FEE_DATAREADY_OUT => fee_dataready, + FEE_READ_IN => fee_read, + FEE_STATUS_BITS_OUT => fee_status_bits, + FEE_BUSY_OUT => fee_busy, + MY_ADDRESS_IN => my_address, + COMMON_STAT_REGS => common_stat_regs, --open, + COMMON_CTRL_REGS => common_ctrl_regs, --open, + ONEWIRE => TEMPSENS, + ONEWIRE_MONITOR_IN => open, + MY_ADDRESS_OUT => my_address, + + UNIQUE_ID_OUT => mc_unique_id, + + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + --------------------------------------------------------------------- + -- The GbE machine for blasting out data from TRBnet + --------------------------------------------------------------------- + + GBE: trb_net16_gbe_buf + generic map( + DO_SIMULATION => c_NO, + USE_125MHZ_EXTCLK => c_NO + ) + port map( + CLK => clk_100_i, + TEST_CLK => '0', + CLK_125_IN => CLK_GPLL_RIGHT, + RESET => reset_i, + GSR_N => gsr_n, + --Debug + STAGE_STAT_REGS_OUT => open, --stage_stat_regs, -- should be come STATUS or similar + STAGE_CTRL_REGS_IN => stage_ctrl_regs, -- OBSELETE! + ----gk 22.04.10 not used any more, ip_configurator moved inside + ---configuration interface + IP_CFG_START_IN => stage_ctrl_regs(15), + IP_CFG_BANK_SEL_IN => stage_ctrl_regs(11 downto 8), + IP_CFG_DONE_OUT => open, + IP_CFG_MEM_ADDR_OUT => ip_cfg_mem_addr, + IP_CFG_MEM_DATA_IN => ip_cfg_mem_data, + IP_CFG_MEM_CLK_OUT => ip_cfg_mem_clk, + MR_RESET_IN => stage_ctrl_regs(3), + MR_MODE_IN => stage_ctrl_regs(1), + MR_RESTART_IN => stage_ctrl_regs(0), + ---gk 29.03.10 + --interface to ip_configurator memory + SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0), + SLV_READ_IN => mb_ip_mem_read, + SLV_WRITE_IN => mb_ip_mem_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_ip_mem_ack, + SLV_DATA_IN => mb_ip_mem_data_wr, + SLV_DATA_OUT => mb_ip_mem_data_rd, + --gk 26.04.10 + ---gk 22.04.10 + ---registers setup interface + BUS_ADDR_IN => gbe_stp_reg_addr(7 downto 0), --ctrl_reg_addr(7 downto 0), + BUS_DATA_IN => gbe_stp_reg_data_wr, --stage_ctrl_regs, + BUS_DATA_OUT => gbe_stp_reg_data_rd, + BUS_WRITE_EN_IN => gbe_stp_reg_write, + BUS_READ_EN_IN => gbe_stp_reg_read, + BUS_ACK_OUT => gbe_stp_reg_ack, + --gk 23.04.10 + LED_PACKET_SENT_OUT => open, --buf_SFP_LED_ORANGE(17), + LED_AN_DONE_N_OUT => link_ok, --buf_SFP_LED_GREEN(17), + --CTS interface + CTS_NUMBER_IN => cts_number, + CTS_CODE_IN => cts_code, + CTS_INFORMATION_IN => cts_information, + CTS_READOUT_TYPE_IN => cts_readout_type, + CTS_START_READOUT_IN => cts_start_readout, + CTS_DATA_OUT => cts_data, + CTS_DATAREADY_OUT => cts_dataready, + CTS_READOUT_FINISHED_OUT => cts_readout_finished, + CTS_READ_IN => cts_read, + CTS_LENGTH_OUT => cts_length, + CTS_ERROR_PATTERN_OUT => cts_status_bits, + --Data payload interface + FEE_DATA_IN => fee_data, + FEE_DATAREADY_IN => fee_dataready, + FEE_READ_OUT => fee_read, + FEE_STATUS_BITS_IN => fee_status_bits, + FEE_BUSY_IN => fee_busy, + --SFP Connection + SFP_RXD_P_IN => SFP_RX_P(5), + SFP_RXD_N_IN => SFP_RX_N(5), + SFP_TXD_P_OUT => SFP_TX_P(5), + SFP_TXD_N_OUT => SFP_TX_N(5), + SFP_REFCLK_P_IN => open, --SFP_REFCLKP(2), + SFP_REFCLK_N_IN => open, --SFP_REFCLKN(2), + SFP_PRSNT_N_IN => SFP_MOD0(5), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN => SFP_LOS(5), -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT => SFP_TXDIS(5), -- SFP disable + + -- interface between main_controller and hub logic + MC_UNIQUE_ID_IN => mc_unique_id, + GSC_CLK_IN => clk_100_i, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + + --for simulation of receiving part only + MAC_RX_EOF_IN => '0', + MAC_RXD_IN => "00000000", + MAC_RX_EN_IN => '0', + + ANALYZER_DEBUG_OUT => debug + ); + +end generate; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- +THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + + -- third one - IP config memory + BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr, + BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr, + BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read, + BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd, + BUS_DATAREADY_IN(2) => mb_ip_mem_ack, + BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack, + BUS_NO_MORE_DATA_IN(2) => '0', + BUS_UNKNOWN_ADDR_IN(2) => '0', + + -- gk 22.04.10 + -- gbe setup + BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr, + BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr, + BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read, + BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd, + BUS_DATAREADY_IN(3) => gbe_stp_reg_ack, + BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack, + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => '0', + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + +THE_SPI_MASTER: spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_CIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + +-- data memory for SPI accesses +THE_SPI_MEMORY: spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- +THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_regs(15), + PROGRAMN => PROGRAMN + ); + + +--------------------------------------------------------------------------- +-- Clock and Trigger Configuration +--------------------------------------------------------------------------- + TRIGGER_SELECT <= '0'; --always external trigger source + CLOCK_SELECT <= '0'; --use on-board oscillator + CLK_MNGR1_USER <= (others => '0'); + CLK_MNGR2_USER <= (others => '0'); + + TRIGGER_OUT <= '0'; + +--------------------------------------------------------------------------- +-- FPGA communication +--------------------------------------------------------------------------- +-- FPGA1_COMM <= (others => 'Z'); +-- FPGA2_COMM <= (others => 'Z'); +-- FPGA3_COMM <= (others => 'Z'); +-- FPGA4_COMM <= (others => 'Z'); + + FPGA1_TTL <= (others => 'Z'); + FPGA2_TTL <= (others => 'Z'); + FPGA3_TTL <= (others => 'Z'); + FPGA4_TTL <= (others => 'Z'); + + FPGA1_CONNECTOR <= (others => 'Z'); + FPGA2_CONNECTOR <= (others => 'Z'); + FPGA3_CONNECTOR <= (others => 'Z'); + FPGA4_CONNECTOR <= (others => 'Z'); + + +--------------------------------------------------------------------------- +-- Big AddOn Connector +--------------------------------------------------------------------------- + ADDON_RESET <= '1'; + TRB_TO_ADDON_CLK <= '0'; + ADO_LV <= (others => 'Z'); + ADO_TTL <= (others => 'Z'); + FS_PE <= (others => 'Z'); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_CLOCK_GREEN <= '0'; + LED_CLOCK_RED <= '1'; +-- LED_GREEN <= not med_stat_op(9); +-- LED_YELLOW <= not med_stat_op(10); +-- LED_ORANGE <= not med_stat_op(11); +-- LED_RED <= '1'; + LED_TRIGGER_GREEN <= not med_stat_op(4*16+9); + LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10)); + + +--LED_GREEN <= time_counter(27); +--LED_ORANGE <= time_counter2(27); +--LED_RED <= debug(2); +--LED_YELLOW <= debug(3); + +LED_GREEN <= debug(0); +LED_ORANGE <= debug(1); +LED_RED <= debug(2); +LED_YELLOW <= link_ok; --debug(3); + + +--------------------------------------------------------------------------- +-- Test Connector +--------------------------------------------------------------------------- + + TEST_LINE(7 downto 0) <= med_data_in(7 downto 0); + TEST_LINE(8) <= med_dataready_in(0); + TEST_LINE(9) <= med_dataready_out(0); + + + TEST_LINE(31 downto 10) <= (others => '0'); + + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process + begin + wait until rising_edge(clk_100_i); + time_counter <= time_counter + 1; + end process; + + +end architecture; \ No newline at end of file -- 2.43.0