From e032162523a6265ec63a467a14a1b12f2f3ff134 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 8 Jul 2022 15:15:17 +0200 Subject: [PATCH] typos --- gbe_hub/trb3sc_gbe_hub.vhd | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index dd8407a..cde1294 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -174,6 +174,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal fw_link_active_int : std_logic; signal fw_mac_tx_done_int : std_logic; signal fw_mac_rx_fifofull_int : std_logic; + signal fw_frame_start_int : std_logic; signal bw_mac_rx_data_int : std_logic_vector(7 downto 0); signal bw_mac_rx_wr_int : std_logic; @@ -196,6 +197,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal bw_link_active_int : std_logic; signal bw_mac_tx_done_int : std_logic; signal bw_mac_rx_fifofull_int : std_logic; + signal bw_frame_start_int : std_logic; begin @@ -623,8 +625,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler DBG(21) <= bw_mac_rx_eof_int; DBG(22) <= fw_mac_fifoeof_int; DBG(23) <= bw_mac_fifoeof_int; - DBG(24) <= fw_mac_ready_conf_int; - DBG(25) <= bw_mac_ready_conf_int; + DBG(24) <= fw_frame_start_int; + DBG(25) <= bw_frame_start_int; DBG(26) <= fw_mac_fifoempty_int; DBG(27) <= bw_mac_fifoempty_int; DBG(28) <= fw_mac_rx_fifofull_int; @@ -680,7 +682,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler MAC_RX_WR_IN => fw_mac_rx_wr_int, MAC_RX_EOF_IN => fw_mac_rx_eof_int, MAC_RX_ERROR_IN => fw_mac_rx_err_int, - MAC_RX_FIFOFULL_OUT => fw_mac_rx_fifofull_int, -- BUG + MAC_RX_FIFOFULL_OUT => fw_mac_rx_fifofull_int, -- FIFO interface (TX) FIFO_FULL_IN => fw_fifo_full_int, FIFO_WR_OUT => fw_fifo_wr_int, @@ -688,6 +690,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler FRAME_REQ_IN => fw_frame_req_int, FRAME_ACK_OUT => fw_frame_ack_int, FRAME_AVAIL_OUT => fw_frame_avail_int, + FRAME_START_OUT => fw_frame_start_int, -- DEBUG => open ); @@ -708,6 +711,9 @@ THE_CLOCK_RESET : entity work.clock_reset_handler FIFO_FULL_OUT => fw_fifo_full_int, FIFO_WR_IN => fw_fifo_wr_int, FIFO_D_IN => fw_fifo_data_int, + -- Link stuff + FRAME_START_IN => fw_frame_start_int, + LINK_ACTIVE_IN => fw_mac_an_ready_int, -- DEBUG => open ); @@ -751,7 +757,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler MAC_RX_WR_IN => bw_mac_rx_wr_int, MAC_RX_EOF_IN => bw_mac_rx_eof_int, MAC_RX_ERROR_IN => bw_mac_rx_err_int, - MAC_RX_FIFOFULL_OUT => bw_mac_rx_fifofull_int, -- BUG + MAC_RX_FIFOFULL_OUT => bw_mac_rx_fifofull_int, -- FIFO interface (TX) FIFO_FULL_IN => bw_fifo_full_int, FIFO_WR_OUT => bw_fifo_wr_int, @@ -759,6 +765,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler FRAME_REQ_IN => bw_frame_req_int, FRAME_ACK_OUT => bw_frame_ack_int, FRAME_AVAIL_OUT => bw_frame_avail_int, + FRAME_START_OUT => bw_frame_start_int, -- DEBUG => open ); @@ -779,11 +786,12 @@ THE_CLOCK_RESET : entity work.clock_reset_handler FIFO_FULL_OUT => bw_fifo_full_int, FIFO_WR_IN => bw_fifo_wr_int, FIFO_D_IN => bw_fifo_data_int, + -- Link stuff + FRAME_START_IN => bw_frame_start_int, + LINK_ACTIVE_IN => bw_mac_an_ready_int, -- DEBUG => open ); - --- -- - -- THE_BW_FORWARDER: entity forwarder port map( -- 2.43.0