From e04e804796fe45dcee5504439aeca68305244fdf Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 12 Nov 2008 15:17:25 +0000 Subject: [PATCH] *** empty log message *** --- special/trb_net_bridge_acromag_apl.vhd | 357 +++++++++++ special/trb_net_bridge_acromag_endpoint.vhd | 626 ++++++++++++++++++++ special/trb_net_bridge_etrax_apl.vhd | 342 +++++++++++ special/trb_net_bridge_etrax_endpoint.vhd | 580 ++++++++++++++++++ 4 files changed, 1905 insertions(+) create mode 100644 special/trb_net_bridge_acromag_apl.vhd create mode 100644 special/trb_net_bridge_acromag_endpoint.vhd create mode 100644 special/trb_net_bridge_etrax_apl.vhd create mode 100644 special/trb_net_bridge_etrax_endpoint.vhd diff --git a/special/trb_net_bridge_acromag_apl.vhd b/special/trb_net_bridge_acromag_apl.vhd new file mode 100644 index 0000000..108058c --- /dev/null +++ b/special/trb_net_bridge_acromag_apl.vhd @@ -0,0 +1,357 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + + +entity trb_net_bridge_acromag_apl is + generic( + CHANNELS : integer := 2**(c_MUX_WIDTH) + ); + port( + CLK : in std_logic; + CLK_TRB : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); + APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + CPU_RD : in STD_LOGIC; + CPU_WR : in STD_LOGIC; + CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); + CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0); + CPU_ADDRESS : in STD_LOGIC_VECTOR (11 downto 0); + CPU_INTERRUPT_OUT : out STD_LOGIC_VECTOR ( 7 downto 0); + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); +end entity; + +--address range is 000 to FFF +-- (c is channel number * 2 + 1 if active part) + +--sending data. sending is released when 1c0 is written +--1c0 wr (3..0) Dtype (8) short transfer sender_control 9bit used +--1c1 wr target address sender_target 16bit used +--1c2 wr Errorbits sender_error 32bit used +--1c3 w sender data fifo sender_data 16bit used +--1cF r status (0)transfer running sender_status 1bit used + + +--received data +--2c3 r receiver data fifo, (20..18)type receiver_data 16bit used +--2c4 r number of received 32bit words receiver_counter 10bit used + + +--3c0 (7..0) seq_num api_status + + + +architecture trb_net_bridge_acromag_apl_arch of trb_net_bridge_acromag_apl is + signal fifo_net_to_pci_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_din : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_net_to_pci_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_net_to_pci_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + + signal sender_control : std_logic_vector(32*CHANNELS-1 downto 0); + signal sender_target : std_logic_vector(32*CHANNELS-1 downto 0); + signal sender_error : std_logic_vector(32*CHANNELS-1 downto 0); + signal sender_status : std_logic_vector(32*CHANNELS-1 downto 0); + signal receiver_counter : std_logic_vector(32*CHANNELS-1 downto 0); + signal current_receiver_data : std_logic_vector(31 downto 0); + signal api_status : std_logic_vector(32*CHANNELS-1 downto 0); + + signal channel_address : integer range 0 to 7; + signal comb_channel_address : integer range 0 to 7; + signal last_CPU_ADDRESS : std_logic_vector(11 downto 0); + + signal reg_CPU_ADDRESS : std_logic_vector(11 downto 0); + signal reg_CPU_DATA_IN : std_logic_vector(31 downto 0); + signal next_CPU_DATA_OUT: std_logic_vector(31 downto 0); + signal buf_CPU_DATA_OUT : std_logic_vector(31 downto 0); + signal reg_CPU_RD : std_logic; + signal reg_CPU_WR : std_logic; + signal last_CLK, CLK_SLOW_EN : std_logic; + signal last_CLK_SLOW_EN: std_logic; + signal comb_CLK_SLOW_EN : std_logic; + signal last2_CLK_SLOW_EN : std_logic; + signal last_reg_CPU_ADDRESS : std_logic_vector(11 downto 0); + signal tmp : std_logic_vector(11 downto 0); + + component trb_net_fifo_16bit_bram_dualport_fallthrough is + port ( + rd_clk: IN std_logic; + wr_clk: IN std_logic; + rd_en: IN std_logic; + wr_en: IN std_logic; + rst: IN std_logic; + din: IN std_logic_vector(17 downto 0); + dout: OUT std_logic_vector(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic; + valid: OUT std_logic + ); + end component; + + component trb_net_fifo_16bit_bram_dualport is + port ( + read_clock_in: IN std_logic; + write_clock_in: IN std_logic; + read_enable_in: IN std_logic; + write_enable_in: IN std_logic; + fifo_gsr_in: IN std_logic; + write_data_in: IN std_logic_vector(17 downto 0); + read_data_out: OUT std_logic_vector(17 downto 0); + full_out: OUT std_logic; + empty_out: OUT std_logic; + valid_read_out: OUT std_logic + ); + end component; + +begin + + STAT(11) <= reg_CPU_WR; + STAT(10) <= reg_CPU_RD; + + STAT(9 downto 0) <= reg_CPU_ADDRESS(9 downto 0); + STAT(15 downto 14) <= reg_CPU_DATA_IN(1 downto 0); + + +-------------------------------- +-- r/w registers +-------------------------------- + channel_address <= conv_integer(reg_CPU_ADDRESS(6 downto 4)); + comb_channel_address <= conv_integer(CPU_ADDRESS(6 downto 4)); + + read_regs : process(sender_control, sender_target, sender_error, sender_status, + receiver_counter, reg_CPU_ADDRESS, reg_CPU_RD, reg_CPU_WR, api_status, + buf_CPU_DATA_OUT, reg_CPU_DATA_IN, channel_address,current_receiver_data) + begin + next_CPU_DATA_OUT <= (others => '0'); + -- if reg_CPU_RD = '1' then + case reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) is + --middle nibble is dont care + when x"10" => + next_CPU_DATA_OUT <= sender_control(channel_address*32+31 downto channel_address*32); + when x"11" => + next_CPU_DATA_OUT <= sender_target(channel_address*32+31 downto channel_address*32); + when x"12" => + next_CPU_DATA_OUT <= sender_error(channel_address*32+31 downto channel_address*32); + when x"1F" => + next_CPU_DATA_OUT <= sender_status(channel_address*32+31 downto channel_address*32); + when x"24" => + next_CPU_DATA_OUT <= receiver_counter(channel_address*32+31 downto channel_address*32); + when x"30" => + next_CPU_DATA_OUT <= api_status(channel_address*32+31 downto channel_address*32); + when others => + next_CPU_DATA_OUT <= "0001000000000000000" & CTRL(31 downto 19); + end case; + -- end if; + end process; + + + write_regs : process(CLK_TRB) + begin + if rising_edge(CLK_TRB) then + if RESET = '1' then + sender_control <= (others => '0'); + sender_target <= (others => '0'); + sender_error <= (others => '0'); + else + if reg_CPU_WR = '1' then + case reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) is + --middle nibble is dont care + when x"10" => + sender_control(channel_address*32+8 downto channel_address*32) <= reg_CPU_DATA_IN(8 downto 0); + when x"11" => + sender_target(channel_address*32+15 downto channel_address*32) <= reg_CPU_DATA_IN(15 downto 0); + when x"12" => + sender_error(channel_address*32+31 downto channel_address*32) <= reg_CPU_DATA_IN; + when others => + end case; + end if; + end if; + end if; + end process; + +-------------------------------- +-- connection to API +-------------------------------- + + gen_api_connect : for i in 0 to CHANNELS-1 generate + APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32); + api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8); +-- APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) +-- <= fifo_pci_to_net_dout((c_DATA_WIDTH+c_NUM_WIDTH)*i+c_DATA_WIDTH-1 downto (c_DATA_WIDTH+c_NUM_WIDTH)*i); +-- APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= fifo_pci_to_net_dout; + sender_status(i*32) <= APL_RUN_IN(i); + --api_status(i*32+10 downto i*32+8) <= APL_TYP_IN; + next_APL_SEND_OUT(i) <= '1' when reg_CPU_ADDRESS(11 downto 8) = "0001" + and reg_CPU_ADDRESS(7 downto 4) = i + and reg_CPU_ADDRESS(3 downto 0) = "0000" + and reg_CPU_WR = '1' else '0'; + APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i); + fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost + APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8); + APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32); + APL_TARGET_ADDRESS_OUT(i*16+15 downto i*16) <= sender_target(i*32+15 downto i*32); + APL_READ_OUT(i) <= not fifo_net_to_pci_full(i); + fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i); + end generate; + + process(CLK_TRB) + begin + if rising_edge(CLK_TRB) then + APL_SEND_OUT <= next_APL_SEND_OUT; + end if; + end process; + +-------------------------------- +-- fifo as bridge to pci +-------------------------------- + + gen_incoming_fifos : for i in 0 to CHANNELS-1 generate + + fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0'); + fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); + fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); + fifo_net_to_pci_din(32*i+c_DATA_WIDTH+c_NUM_WIDTH-1 downto 32*i) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2) & APL_PACKET_NUM_IN(c_NUM_WIDTH*i) & APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); + APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= fifo_pci_to_net_dout(i*32+c_DATA_WIDTH-1 downto i*32); + APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*32+c_DATA_WIDTH+1 downto i*32+c_DATA_WIDTH); + APL_PACKET_NUM_OUT(i*3+2) <= '0'; + + STAT(24) <= fifo_net_to_pci_empty(1); + STAT(25) <= fifo_net_to_pci_read(1); + STAT(26) <= fifo_net_to_pci_write(1); +-- FIFO_NET_TO_PCI: trb_net_fifo_16bit_bram_dualport_fallthrough +-- port map( +-- rd_clk => CLK, +-- wr_clk => CLK_TRB, +-- rd_en => fifo_net_to_pci_read(i), +-- wr_en => fifo_net_to_pci_write(i), +-- rst => RESET, +-- din => fifo_net_to_pci_din(32*i+17 downto 32*i), +-- dout => fifo_net_to_pci_dout(32*i+17 downto 32*i), +-- full => fifo_net_to_pci_full(i), +-- empty => fifo_net_to_pci_empty(i), +-- valid => fifo_net_to_pci_valid_read(i) +-- ); + FIFO_NET_TO_PCI: trb_net_fifo_16bit_bram_dualport + port map( + read_clock_in => CLK, + write_clock_in => CLK_TRB, + read_enable_in => fifo_net_to_pci_read(i), + write_enable_in => fifo_net_to_pci_write(i), + fifo_gsr_in => RESET, + write_data_in => fifo_net_to_pci_din(32*i+17 downto 32*i), + read_data_out => fifo_net_to_pci_dout(32*i+17 downto 32*i), + full_out => fifo_net_to_pci_full(i), + empty_out => fifo_net_to_pci_empty(i), + valid_read_out => fifo_net_to_pci_valid_read(i) + ); + FIFO_PCI_TO_NET: trb_net_fifo_16bit_bram_dualport + port map( + read_clock_in => CLK_TRB, + write_clock_in => CLK, + read_enable_in => fifo_pci_to_net_read(i), + write_enable_in => fifo_pci_to_net_write(i), + fifo_gsr_in => RESET, + write_data_in => reg_CPU_DATA_IN(17 downto 0), + read_data_out => fifo_pci_to_net_dout(32*i+17 downto 32*i), + full_out => fifo_pci_to_net_full(i), + empty_out => fifo_pci_to_net_empty(i), + valid_read_out => fifo_pci_to_net_valid_read(i) + ); + + end generate; + + +--write/read flags for fifo + + process(CPU_ADDRESS, CPU_RD, CPU_WR, comb_channel_address,reg_CPU_ADDRESS, channel_address) + begin + fifo_net_to_pci_read <= (others => '0'); + fifo_pci_to_net_write <= (others => '0'); --using now registered address + if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = "00100011" then + fifo_net_to_pci_read(channel_address) <= CPU_RD; + end if; + if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = "00010011" then + fifo_pci_to_net_write(channel_address) <= CPU_WR; + end if; + end process; + +-------------------------------- +-- synchronize to slow PCI clock +-------------------------------- + + register_slow_output : process(CLK_TRB) + begin + if rising_edge(CLK_TRB) then + if last_CLK_SLOW_EN = '1' then + buf_CPU_DATA_OUT <= next_CPU_DATA_OUT; + end if; + end if; + end process; + + process(CPU_ADDRESS, buf_CPU_DATA_OUT, fifo_net_to_pci_dout,reg_CPU_ADDRESS) + begin + last_CPU_ADDRESS <= CPU_ADDRESS; + if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = x"23" then + CPU_DATA_OUT <= fifo_net_to_pci_dout((conv_integer(reg_CPU_ADDRESS(6 downto 4))+1)*32-1 downto conv_integer(reg_CPU_ADDRESS(6 downto 4))*32); + else + CPU_DATA_OUT <= buf_CPU_DATA_OUT; + end if; + end process; + + + register_slow_dat_addr_input : process(CLK_TRB) + begin + if rising_edge(CLK_TRB) then + reg_CPU_RD <= '0'; + reg_CPU_WR <= '0'; + if CLK_SLOW_EN = '1' then + reg_CPU_ADDRESS <= CPU_ADDRESS; + reg_CPU_DATA_IN <= CPU_DATA_IN; + reg_CPU_RD <= CPU_RD; + reg_CPU_WR <= CPU_WR; + end if; + end if; + end process; + +comb_CLK_SLOW_EN <= CLK and not last_CLK; + generate_slow_clk_en : process(CLK_TRB) + begin + if rising_edge(CLK_TRB) then + last_CLK <= CLK; + CLK_SLOW_EN <= CLK and not last_CLK; + last_CLK_SLOW_EN <= CLK_SLOW_EN; + last2_CLK_SLOW_EN <= last_CLK_SLOW_EN; + end if; + end process; +end architecture; \ No newline at end of file diff --git a/special/trb_net_bridge_acromag_endpoint.vhd b/special/trb_net_bridge_acromag_endpoint.vhd new file mode 100644 index 0000000..b745e7b --- /dev/null +++ b/special/trb_net_bridge_acromag_endpoint.vhd @@ -0,0 +1,626 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity trb_net_bridge_acromag_endpoint is + port( + RESET : in std_logic; + + clk: in std_logic; + RD: in STD_LOGIC; -- Read strobe + WR: in STD_LOGIC; -- Write strobe + DATA_OUT: out STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus + DATA_IN : in STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus + ADDRESS: in STD_LOGIC_VECTOR (11 downto 0); -- Adress lines for the given space + TRB_INTERRUPT_OUT : out STD_LOGIC_VECTOR(7 downto 0); + + clk_trb: in std_logic; + LVDS_OUT: out STD_LOGIC_VECTOR (31 downto 0); + LVDS_IN: in STD_LOGIC_VECTOR (31 downto 0) + ); +end entity; + + +architecture trb_net_bridge_acromag_endpoint_arch of trb_net_bridge_acromag_endpoint is + + component trb_net_med_8bit_slow + generic( + TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 4 --even values only! + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media + INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT:out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in STD_LOGIC; + INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits + INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media + INT_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out STD_LOGIC; -- offered word is read + MED_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word + --(incl. debugging errorbits) + MED_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word + STAT: out STD_LOGIC_VECTOR (31 downto 0); + CTRL: in STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + +component trb_net16_io_multiplexer is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + + -- Internal direction port + INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + + -- Status and control port + CTRL : in STD_LOGIC_VECTOR (31 downto 0); + STAT : out STD_LOGIC_VECTOR (31 downto 0) + ); +end component; + + + component trb_net_bridge_acromag_apl is + generic( + CHANNELS : integer := 2**(c_MUX_WIDTH) + ); + port( + CLK : in std_logic; + CLK_TRB : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); + APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + CPU_RD : in STD_LOGIC; + CPU_WR : in STD_LOGIC; + CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); + CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0); + CPU_ADDRESS : in STD_LOGIC_VECTOR (11 downto 0); + CPU_INTERRUPT_OUT : out STD_LOGIC_VECTOR ( 7 downto 0); + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); + end component; + +component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + + -- Internal direction port + + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN : in std_logic; + + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT : out std_logic; + + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN : in std_logic; + + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT : out std_logic; + + -- Status and control port + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0) + ); +end component; + +component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN : in std_logic; + + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); +end component; + + + signal MED_DATAREADY_IN, MED_DATAREADY_OUT : std_logic; + signal MED_DATA_IN, MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal MED_PACKET_NUM_IN, MED_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal MED_ERROR_IN : std_logic_vector(2 downto 0); + signal MED_READ_IN, MED_READ_OUT : std_logic; + signal LVDS_STAT, LVDS_CTRL : std_logic_vector(31 downto 0); + signal buf_LVDS_OUT : std_logic_vector(15 downto 0); + signal buf_LVDS_IN : std_logic_vector(15 downto 0); + signal APL_STAT : std_logic_vector(31 downto 0); + + signal APL_DATA_IN : std_logic_vector(2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); + signal APL_PACKET_NUM_IN : std_logic_vector(2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); + signal APL_DATAREADY_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_READ_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_SHORT_TRANSFER_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_DTYPE_IN : std_logic_vector(2**(c_MUX_WIDTH)*4-1 downto 0); + signal APL_SEND_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_DATA_OUT : std_logic_vector(2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); + signal APL_PACKET_NUM_OUT : std_logic_vector(2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); + signal APL_TYP_OUT : std_logic_vector(2**(c_MUX_WIDTH)*3-1 downto 0); + signal APL_DATAREADY_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_READ_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_RUN_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_SEQNR_OUT : std_logic_vector(2**(c_MUX_WIDTH)*8-1 downto 0); + signal APL_TARGET_ADDRESS_OUT : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0); + signal APL_ERROR_PATTERN_IN : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + signal APL_TARGET_ADDRESS_IN : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0); + signal APL_MY_ADDRESS_IN : std_logic_vector(15 downto 0); + + signal buf_api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + signal buf_api_stat_fifo_to_apl : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + + signal buf_DATA_OUT : std_logic_vector(31 downto 0); + signal CLK_EN : std_logic; + + signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0); + signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0); + signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + signal m_DATAREADY_IN : std_logic_vector (c_MUX_WIDTH-1 downto 0); + signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); + signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); + signal m_READ_OUT : std_logic_vector (c_MUX_WIDTH-1 downto 0); + signal MPLEX_CTRL : std_logic_vector (31 downto 0); + + signal apl_to_buf_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal apl_to_buf_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal apl_to_buf_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal buf_to_apl_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal buf_to_apl_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal buf_to_apl_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal apl_to_buf_REPLY_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal apl_to_buf_REPLY_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal buf_to_apl_REPLY_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal buf_to_apl_REPLY_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + + signal STAT_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_LOCKED : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_INIT_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_REPLY_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal CTRL_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal CTRL_LOCKED : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_CTRL_INIT_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_CTRL_REPLY_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal RESET_i : std_logic; + signal RESET_CNT : std_logic_vector(1 downto 0); + signal counter : std_logic_vector(12 downto 0); +begin + CLK_EN <= '1'; + APL_MY_ADDRESS_IN <= x"FF09"; + + process(CLK_TRB) + begin + if rising_edge(CLK_TRB) then + if RESET = '1' then + RESET_i <= '1'; + RESET_CNT <= "00"; + else + counter <= counter + 1; + RESET_CNT <= RESET_CNT + 1; + RESET_i <= '1'; + if RESET_CNT = "11" then + RESET_i <= '0'; + RESET_CNT <= "11"; + end if; + end if; + end if; + end process; + + LVDS : trb_net_med_8bit_slow + generic map( + TRANSMISSION_CLOCK_DIVIDER => 4 + ) + port map( + CLK => CLK_TRB, + RESET => RESET_i, + CLK_EN => CLK_EN, + INT_DATAREADY_OUT => MED_DATAREADY_IN, + INT_DATA_OUT => MED_DATA_IN, + INT_PACKET_NUM_OUT=> MED_PACKET_NUM_IN, + INT_READ_IN => MED_READ_OUT, + INT_ERROR_OUT => MED_ERROR_IN, + INT_DATAREADY_IN => MED_DATAREADY_OUT, + INT_DATA_IN => MED_DATA_OUT, + INT_PACKET_NUM_IN => MED_PACKET_NUM_OUT, + INT_READ_OUT => MED_READ_IN, + MED_DATA_OUT => buf_LVDS_OUT, + MED_DATA_IN => buf_LVDS_IN, + STAT => LVDS_STAT, + CTRL => LVDS_CTRL + ); + + LVDS_OUT(12 downto 8) <= buf_LVDS_OUT(15 downto 11); + LVDS_OUT(7 downto 0) <= buf_LVDS_OUT(7 downto 0); +--LVDS_OUT(12 downto 0) <= counter; + + buf_LVDS_IN(7 downto 0) <= LVDS_IN(21) & LVDS_IN(19 downto 13); + buf_LVDS_IN(10 downto 8) <= "000"; + buf_LVDS_IN(15 downto 11) <= LVDS_IN(26 downto 22); + +-- LVDS_OUT(12 downto 0) <= LVDS_STAT(31 downto 19); + + MPLEX: trb_net16_io_multiplexer + port map ( + CLK => clk_trb, + RESET => RESET_i, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => m_DATAREADY_IN, + INT_DATA_OUT => m_DATA_IN, + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, + INT_READ_IN => m_READ_OUT, + INT_DATAREADY_IN => m_DATAREADY_OUT, + INT_DATA_IN => m_DATA_OUT, + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, + INT_READ_OUT => m_READ_IN, + CTRL => MPLEX_CTRL + ); + + gen_iobufs : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + IOBUF: trb_net16_iobuf + port map ( + -- Misc + CLK => clk_trb , + RESET => RESET_i, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN(c_DATA_WIDTH-1 downto 0), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), + MED_READ_OUT => m_READ_OUT(i), + MED_ERROR_IN => MED_ERROR_IN, + -- Internal direction port + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), + -- Status and control port + STAT_GEN => STAT_GEN((i+1)*32-1 downto i*32), + STAT_IBUF_BUFFER => STAT_INIT_BUFFER((i+1)*32-1 downto i*32), + CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32), + STAT_CTRL_IBUF_BUFFER => STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32) + ); + end generate; + + + gen_pas_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + DAT_PASSIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_PASSIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => clk_trb, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i), + APL_READ_OUT => APL_READ_OUT(2*i), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+1)*4-1 downto 2*i*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+1)*32-1 downto 2*i*32), + APL_SEND_IN => APL_SEND_IN(2*i), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+1)*16-1 downto 2*i*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+1)*3-1 downto 2*i*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i), + APL_READ_IN => APL_READ_IN(2*i), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+1)*8-1 downto 2*i*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+1)*32-1 downto 2*i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+1)*32-1 downto 2*i*32) + ); + end generate; + gen_act_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + DAT_ACTIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_ACTIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => clk_trb, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1), + APL_READ_OUT => APL_READ_OUT(2*i+1), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32), + APL_SEND_IN => APL_SEND_IN(2*i+1), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1), + APL_READ_IN => APL_READ_IN(2*i+1), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i+1), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) + ); + end generate; + + APL : trb_net_bridge_acromag_apl + port map( + CLK => CLK, + CLK_TRB => CLK_TRB, + RESET => RESET_i, + CLK_EN => CLK_EN, + APL_DATA_OUT => APL_DATA_IN, + APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN, + APL_DATAREADY_OUT => APL_DATAREADY_IN, + APL_READ_IN => APL_READ_OUT, + APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN, + APL_DTYPE_OUT => APL_DTYPE_IN, + APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_IN, + APL_SEND_OUT => APL_SEND_IN, + APL_DATA_IN => APL_DATA_OUT, + APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT, + APL_TYP_IN => APL_TYP_OUT, + APL_DATAREADY_IN => APL_DATAREADY_OUT, + APL_READ_OUT => APL_READ_IN, + APL_RUN_IN => APL_RUN_OUT, + APL_SEQNR_IN => APL_SEQNR_OUT, + APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN, + CPU_RD => RD, + CPU_WR => WR, + CPU_DATA_OUT => buf_DATA_OUT, + CPU_DATA_IN => DATA_IN, + CPU_ADDRESS => ADDRESS, + CPU_INTERRUPT_OUT => TRB_INTERRUPT_OUT, + STAT => APL_STAT, + CTRL(12 downto 0) => LVDS_STAT(31 downto 19), + CTRL(31 downto 13) => "1111000000000000000" + ); + DATA_OUT <= buf_DATA_OUT; + +end architecture; \ No newline at end of file diff --git a/special/trb_net_bridge_etrax_apl.vhd b/special/trb_net_bridge_etrax_apl.vhd new file mode 100644 index 0000000..07571e8 --- /dev/null +++ b/special/trb_net_bridge_etrax_apl.vhd @@ -0,0 +1,342 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + + +entity trb_net_bridge_etrax_apl is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); + APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + CPU_READ : in STD_LOGIC; + CPU_WRITE : in STD_LOGIC; + CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); + CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0); + CPU_DATAREADY_OUT : out std_logic; + CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0); + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); +end entity; + +--address range is 000 to FFF +-- (c is channel number * 2 + 1 if active part) + +--sending data. sending is released when 1c0 is written +--1c0 wr (3..0) Dtype (8) short transfer sender_control 9bit used +--1c1 wr target address sender_target 16bit used +--1c2 wr Errorbits sender_error 32bit used +--1c3 w sender data fifo sender_data 16bit used +--1cF r status (0)transfer running sender_status 1bit used + + +--received data +--2c3 r receiver data fifo, (20..18)type receiver_data 16bit used +--2c4 r number of received 32bit words receiver_counter 10bit used + + +--3c0 (7..0) seq_num api_status + + + +architecture trb_net_bridge_etrax_apl_arch of trb_net_bridge_etrax_apl is + signal fifo_net_to_pci_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_din : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_net_to_pci_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_net_to_pci_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + + signal sender_control : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal sender_target : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal sender_error : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal sender_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal receiver_counter : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal current_receiver_data : std_logic_vector(31 downto 0); + signal api_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + + signal channel_address : integer range 0 to 7; + signal comb_channel_address : integer range 0 to 7; + signal last_CPU_ADDRESS : std_logic_vector(15 downto 0); + + signal reg_CPU_ADDRESS : std_logic_vector(15 downto 0); + signal reg_CPU_DATA_IN : std_logic_vector(31 downto 0); + signal next_CPU_DATA_OUT: std_logic_vector(31 downto 0); + signal buf_CPU_DATA_OUT : std_logic_vector(31 downto 0); + signal reg_CPU_READ : std_logic; + signal reg_CPU_WRITE : std_logic; + + signal last_reg_CPU_ADDRESS : std_logic_vector(11 downto 0); + signal tmp : std_logic_vector(11 downto 0); + + signal last_fifo_read : std_logic; + signal buf_CPU_DATAREADY_OUT : std_logic; + signal b_CPU_DATAREADY_OUT : std_logic; + + + +component trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + DEPTH : integer := 6 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic + ); +end component; + +begin + + CPU_DATAREADY_OUT <= b_CPU_DATAREADY_OUT; + + STAT(11) <= CPU_WRITE; + STAT(10) <= CPU_READ; + STAT(12) <= b_CPU_DATAREADY_OUT; + STAT(13) <= fifo_net_to_pci_read(1); + STAT(9 downto 0) <= reg_CPU_ADDRESS(9 downto 0); + STAT(15 downto 14) <= reg_CPU_DATA_IN(1 downto 0); + STAT(16) <= fifo_pci_to_net_read(1); + STAT(17) <= fifo_pci_to_net_valid_read(1); + STAT(18) <= fifo_pci_to_net_empty(1); + STAT(19) <= fifo_pci_to_net_write(1); + STAT(20) <= APL_READ_IN(1); + STAT(21) <= fifo_pci_to_net_full(1); + STAT(22) <= RESET; + +-------------------------------- +-- r/w registers +-------------------------------- + channel_address <= conv_integer(reg_CPU_ADDRESS(6 downto 4)); + comb_channel_address <= conv_integer(CPU_ADDRESS(6 downto 4)); + + read_regs : process(sender_control, sender_target, sender_error, sender_status, + receiver_counter, reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, api_status, + buf_CPU_DATA_OUT, reg_CPU_DATA_IN, channel_address,current_receiver_data, CTRL) + begin + next_CPU_DATA_OUT <= (others => '0'); + -- if reg_CPU_RD = '1' then + case reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) is + --middle nibble is dont care + when x"10" => + next_CPU_DATA_OUT <= sender_control(channel_address*32+31 downto channel_address*32); + when x"11" => + next_CPU_DATA_OUT <= sender_target(channel_address*32+31 downto channel_address*32); + when x"12" => + next_CPU_DATA_OUT <= sender_error(channel_address*32+31 downto channel_address*32); + when x"1F" => + next_CPU_DATA_OUT <= sender_status(channel_address*32+31 downto channel_address*32); + when x"24" => + next_CPU_DATA_OUT <= receiver_counter(channel_address*32+31 downto channel_address*32); + when x"30" => + next_CPU_DATA_OUT <= api_status(channel_address*32+31 downto channel_address*32); + when others => + next_CPU_DATA_OUT <= "1000000000000000000" & CTRL(31 downto 19); + end case; + -- end if; + end process; + + + write_regs : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + sender_control <= (others => '0'); + sender_target <= (others => '0'); + sender_error <= (others => '0'); + else + if reg_CPU_WRITE = '1' then + case reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) is + --middle nibble is dont care + when x"10" => + sender_control(channel_address*32+8 downto channel_address*32) <= reg_CPU_DATA_IN(8 downto 0); + when x"11" => + sender_target(channel_address*32+15 downto channel_address*32) <= reg_CPU_DATA_IN(15 downto 0); + when x"12" => + sender_error(channel_address*32+31 downto channel_address*32) <= reg_CPU_DATA_IN; + when others => + end case; + end if; + end if; + end if; + end process; + +-------------------------------- +-- connection to API +-------------------------------- + fifo_pci_to_net_read <= (others => '1'); --APL_READ_IN(i); --NOT CORRECT - last packet may be lost + + gen_api_connect : for i in 0 to 2**(c_MUX_WIDTH)-1 generate + APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32); + api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8); +-- APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) +-- <= fifo_pci_to_net_dout((c_DATA_WIDTH+c_NUM_WIDTH)*i+c_DATA_WIDTH-1 downto (c_DATA_WIDTH+c_NUM_WIDTH)*i); +-- APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= fifo_pci_to_net_dout; + sender_status(i*32) <= APL_RUN_IN(i); + --api_status(i*32+10 downto i*32+8) <= APL_TYP_IN; + next_APL_SEND_OUT(i) <= '1' when reg_CPU_ADDRESS(11 downto 8) = "0001" + and reg_CPU_ADDRESS(7 downto 4) = i + and reg_CPU_ADDRESS(3 downto 0) = "0000" + and reg_CPU_WRITE = '1' else '0'; + APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i); + APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8); + APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32); + APL_TARGET_ADDRESS_OUT(i*16+15 downto i*16) <= sender_target(i*32+15 downto i*32); + APL_READ_OUT(i) <= not fifo_net_to_pci_full(i); + fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i); + end generate; + + process(CLK) + begin + if rising_edge(CLK) then + APL_SEND_OUT <= next_APL_SEND_OUT; + end if; + end process; + +-------------------------------- +-- fifo as bridge to pci +-------------------------------- + + gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate + + fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0'); + fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); + fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); + fifo_net_to_pci_din(32*i+c_DATA_WIDTH+c_NUM_WIDTH-1 downto 32*i) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2) & APL_PACKET_NUM_IN(c_NUM_WIDTH*i) & APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); + APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= fifo_pci_to_net_dout(i*32+c_DATA_WIDTH-1 downto i*32); + APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*32+c_DATA_WIDTH+1 downto i*32+c_DATA_WIDTH); + APL_PACKET_NUM_OUT(i*3+2) <= '0'; + + STAT(24) <= fifo_net_to_pci_empty(1); + STAT(25) <= fifo_net_to_pci_read(1); + STAT(26) <= fifo_net_to_pci_write(1); + + FIFO_NET_TO_PCI: trb_net16_fifo + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => '1', + READ_ENABLE_IN => fifo_net_to_pci_read(i), + WRITE_ENABLE_IN => fifo_net_to_pci_write(i), + DATA_IN => fifo_net_to_pci_din(32*i+15 downto 32*i), + PACKET_NUM_IN => fifo_net_to_pci_din(32*i+17 downto 32*i+16), + DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i), + PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16), + full_out => fifo_net_to_pci_full(i), + empty_out => fifo_net_to_pci_empty(i) + ); + + FIFO_PCI_TO_NET: trb_net16_fifo + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => '1', + READ_ENABLE_IN => fifo_pci_to_net_read(i), + WRITE_ENABLE_IN => fifo_pci_to_net_write(i), + DATA_IN => reg_CPU_DATA_IN(15 downto 0), + PACKET_NUM_IN => reg_CPU_DATA_IN(17 downto 16), + DATA_OUT => fifo_pci_to_net_dout(32*i+15 downto 32*i), + PACKET_NUM_OUT => fifo_pci_to_net_dout(32*i+17 downto 32*i+16), + full_out => fifo_pci_to_net_full(i), + empty_out => fifo_pci_to_net_empty(i) + ); + + end generate; + +process(CLK) + begin + if rising_edge(CLK) then + fifo_pci_to_net_valid_read <= fifo_pci_to_net_read and not fifo_pci_to_net_empty; + fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and not fifo_net_to_pci_empty; + end if; + end process; + +--write/read flags for fifo + + process(reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, comb_channel_address, channel_address) + begin + fifo_net_to_pci_read <= (others => '0'); + fifo_pci_to_net_write <= (others => '0'); + if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = x"23" then + fifo_net_to_pci_read(channel_address) <= reg_CPU_READ; + end if; + if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = x"13" then + fifo_pci_to_net_write(channel_address) <= reg_CPU_WRITE; + end if; + end process; + +-------------------------------- +-- synchronize to slow PCI clock +-------------------------------- + + register_slow_output : process(CLK) + begin + if rising_edge(CLK) then + buf_CPU_DATA_OUT <= next_CPU_DATA_OUT; + buf_CPU_DATAREADY_OUT <= reg_CPU_READ; + last_fifo_read <= or_all(fifo_net_to_pci_read); + end if; + end process; + + process(CPU_ADDRESS, buf_CPU_DATA_OUT, fifo_net_to_pci_dout,reg_CPU_ADDRESS) + begin + last_CPU_ADDRESS <= CPU_ADDRESS; + if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = x"23" then + CPU_DATA_OUT <= fifo_net_to_pci_dout((conv_integer(reg_CPU_ADDRESS(6 downto 4))+1)*32-1 downto conv_integer(reg_CPU_ADDRESS(6 downto 4))*32); + b_CPU_DATAREADY_OUT <= last_fifo_read; + else + CPU_DATA_OUT <= buf_CPU_DATA_OUT; + b_CPU_DATAREADY_OUT <= buf_CPU_DATAREADY_OUT; + end if; + end process; + + + register_slow_dat_addr_input : process(CLK) + begin + if rising_edge(CLK) then + reg_CPU_ADDRESS <= CPU_ADDRESS; + reg_CPU_DATA_IN <= CPU_DATA_IN; + reg_CPU_READ <= CPU_READ; + reg_CPU_WRITE <= CPU_WRITE; + end if; + end process; + + +end architecture; \ No newline at end of file diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/special/trb_net_bridge_etrax_endpoint.vhd new file mode 100644 index 0000000..7983b0c --- /dev/null +++ b/special/trb_net_bridge_etrax_endpoint.vhd @@ -0,0 +1,580 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity trb_net_bridge_etrax_endpoint is + port( + RESET : in std_logic; + CLK: in std_logic; + + CPU_READ: in STD_LOGIC; -- Read strobe + CPU_WRITE: in STD_LOGIC; -- Write strobe + CPU_DATA_OUT: out STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus + CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus + CPU_DATAREADY_OUT : out std_logic; + CPU_ADDRESS: in STD_LOGIC_VECTOR (15 downto 0); -- Adress lines for the given space + + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + + MED_ERROR_IN : in std_logic_vector(2 downto 0); + STAT : out std_logic_vector(31 downto 0); + STAT_ENDP : out std_logic_vector(31 downto 0); + STAT_API1 : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture trb_net_bridge_etrax_endpoint_arch of trb_net_bridge_etrax_endpoint is + + component trb_net16_io_multiplexer is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + + -- Internal direction port + INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + + -- Status and control port + CTRL : in STD_LOGIC_VECTOR (31 downto 0); + STAT : out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + + + component trb_net_bridge_etrax_apl is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); + APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + CPU_READ : in STD_LOGIC; + CPU_WRITE : in STD_LOGIC; + CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); + CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0); + CPU_DATAREADY_OUT : out std_logic; + CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0); + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + + -- Internal direction port + + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN : in std_logic; + + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT : out std_logic; + + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN : in std_logic; + + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT : out std_logic; + + -- Status and control port + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN : in std_logic; + + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + + signal APL_STAT : std_logic_vector(31 downto 0); + + signal APL_DATA_IN : std_logic_vector(2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); + signal APL_PACKET_NUM_IN : std_logic_vector(2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); + signal APL_DATAREADY_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_READ_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_SHORT_TRANSFER_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_DTYPE_IN : std_logic_vector(2**(c_MUX_WIDTH)*4-1 downto 0); + signal APL_SEND_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_DATA_OUT : std_logic_vector(2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); + signal APL_PACKET_NUM_OUT : std_logic_vector(2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); + signal APL_TYP_OUT : std_logic_vector(2**(c_MUX_WIDTH)*3-1 downto 0); + signal APL_DATAREADY_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_READ_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_RUN_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_SEQNR_OUT : std_logic_vector(2**(c_MUX_WIDTH)*8-1 downto 0); + signal APL_TARGET_ADDRESS_OUT : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0); + signal APL_ERROR_PATTERN_IN : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + signal APL_TARGET_ADDRESS_IN : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0); + signal APL_MY_ADDRESS_IN : std_logic_vector(15 downto 0); + + signal buf_api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + signal buf_api_stat_fifo_to_apl : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + + signal buf_DATA_OUT : std_logic_vector(31 downto 0); + signal CLK_EN : std_logic; + + signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0); + signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0); + signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + signal m_DATAREADY_IN : std_logic_vector (c_MUX_WIDTH-1 downto 0); + signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); + signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); + signal m_READ_OUT : std_logic_vector (c_MUX_WIDTH-1 downto 0); + signal MPLEX_CTRL : std_logic_vector (31 downto 0); + + signal apl_to_buf_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal apl_to_buf_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal apl_to_buf_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal buf_to_apl_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal buf_to_apl_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal buf_to_apl_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal apl_to_buf_REPLY_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal apl_to_buf_REPLY_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal buf_to_apl_REPLY_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal buf_to_apl_REPLY_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + + signal STAT_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_LOCKED : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_INIT_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_REPLY_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal CTRL_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal CTRL_LOCKED : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_CTRL_INIT_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_CTRL_REPLY_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal RESET_i : std_logic; + signal RESET_CNT : std_logic_vector(1 downto 0); + signal counter : std_logic_vector(12 downto 0); + signal buf_MED_DATAREADY_OUT : std_logic; +begin + CLK_EN <= '1'; + APL_MY_ADDRESS_IN <= x"F00C"; + RESET_i <= RESET; +-- process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if RESET = '1' then +-- RESET_i <= '1'; +-- RESET_CNT <= "00"; +-- else +-- counter <= counter + 1; +-- RESET_CNT <= RESET_CNT + 1; +-- RESET_i <= '1'; +-- if RESET_CNT = "11" then +-- RESET_i <= '0'; +-- RESET_CNT <= "11"; +-- end if; +-- end if; +-- end if; +-- end process; + + + MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; + + + MPLEX: trb_net16_io_multiplexer + port map ( + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => buf_MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => m_DATAREADY_IN, + INT_DATA_OUT => m_DATA_IN, + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, + INT_READ_IN => m_READ_OUT, + INT_DATAREADY_IN => m_DATAREADY_OUT, + INT_DATA_IN => m_DATA_OUT, + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, + INT_READ_OUT => m_READ_IN, + CTRL => MPLEX_CTRL + ); + + gen_iobufs : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + IOBUF: trb_net16_iobuf + port map ( + -- Misc + CLK => CLK , + RESET => RESET_i, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN(c_DATA_WIDTH-1 downto 0), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), + MED_READ_OUT => m_READ_OUT(i), + MED_ERROR_IN => MED_ERROR_IN, + -- Internal direction port + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), + -- Status and control port + STAT_GEN => STAT_GEN((i+1)*32-1 downto i*32), + STAT_IBUF_BUFFER => STAT_INIT_BUFFER((i+1)*32-1 downto i*32), + CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32), + STAT_CTRL_IBUF_BUFFER => STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32) + ); + end generate; + + + gen_pas_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + DAT_PASSIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_PASSIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i), + APL_READ_OUT => APL_READ_OUT(2*i), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+1)*4-1 downto 2*i*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+1)*32-1 downto 2*i*32), + APL_SEND_IN => APL_SEND_IN(2*i), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+1)*16-1 downto 2*i*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+1)*3-1 downto 2*i*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i), + APL_READ_IN => APL_READ_IN(2*i), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+1)*8-1 downto 2*i*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+1)*32-1 downto 2*i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+1)*32-1 downto 2*i*32) + ); + end generate; + gen_act_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + DAT_ACTIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_ACTIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1), + APL_READ_OUT => APL_READ_OUT(2*i+1), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32), + APL_SEND_IN => APL_SEND_IN(2*i+1), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1), + APL_READ_IN => APL_READ_IN(2*i+1), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i+1), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) + ); + end generate; + + APL : trb_net_bridge_etrax_apl + port map( + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + APL_DATA_OUT => APL_DATA_IN, + APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN, + APL_DATAREADY_OUT => APL_DATAREADY_IN, + APL_READ_IN => APL_READ_OUT, + APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN, + APL_DTYPE_OUT => APL_DTYPE_IN, + APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_IN, + APL_SEND_OUT => APL_SEND_IN, + APL_DATA_IN => APL_DATA_OUT, + APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT, + APL_TYP_IN => APL_TYP_OUT, + APL_DATAREADY_IN => APL_DATAREADY_OUT, + APL_READ_OUT => APL_READ_IN, + APL_RUN_IN => APL_RUN_OUT, + APL_SEQNR_IN => APL_SEQNR_OUT, + APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN, + CPU_READ => CPU_READ, + CPU_WRITE => CPU_WRITE, + CPU_DATA_OUT => CPU_DATA_OUT, + CPU_DATA_IN => CPU_DATA_IN, + CPU_DATAREADY_OUT => CPU_DATAREADY_OUT, + CPU_ADDRESS => CPU_ADDRESS, + STAT => STAT, + CTRL => (others => '0') + ); + +STAT_ENDP(0) <= APL_SEND_IN(1); +STAT_ENDP(4 downto 1) <= CPU_ADDRESS(3 downto 0); +STAT_ENDP(5) <= CPU_READ; +STAT_ENDP(6) <= APL_READ_OUT(1); +STAT_ENDP(7) <= buf_MED_DATAREADY_OUT; +STAT_ENDP(11 downto 8) <= APL_DATA_IN(3 downto 0); +STAT_ENDP(13 downto 12) <= APL_PACKET_NUM_IN(4 downto 3); +STAT_ENDP(14) <= APL_DATAREADY_IN(1); +STAT_ENDP(15) <= buf_to_apl_REPLY_DATAREADY(0); +STAT_API1 <= buf_api_stat_fifo_to_int((2)*32-1 downto (1)*32); + +end architecture; \ No newline at end of file -- 2.43.0