From e1162a8da916379a18a16f1cb22bc418acb66b12 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 28 Jun 2023 11:06:57 +0200 Subject: [PATCH] add option to generate reset signal in ECP5 with falling edge to compensate for hold time violations --- trb_net16_endpoint_hades_full.vhd | 12 ++++++++++-- trb_net16_endpoint_hades_full_gbe.vhd | 10 +++++++++- trb_net16_hub_base.vhd | 10 +++++++++- 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 6bf80e7..bcfb3b3 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -8,6 +8,7 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; use work.trb_net_components.all; +use work.config.all; entity trb_net16_endpoint_hades_full is @@ -237,6 +238,7 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); signal buf_IDRAM_WR_IN : std_logic; signal reset_no_link : std_logic; + signal reset_no_link_tmp : std_logic; signal ONEWIRE_DATA : std_logic_vector(15 downto 0); signal ONEWIRE_ADDR : std_logic_vector(2 downto 0); signal ONEWIRE_WRITE : std_logic; @@ -314,10 +316,16 @@ begin process(CLK) begin if rising_edge(CLK) then - reset_no_link <= MED_STAT_OP_IN(14) or RESET; - reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1); + reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1); + reset_no_link_tmp <= MED_STAT_OP_IN(14) or RESET; end if; end process; + + gen_resetedge : if FPGA_TYPE = 5 generate + reset_no_link <= reset_no_link_tmp when falling_edge(CLK); + else generate + reset_no_link <= reset_no_link_tmp when rising_edge(CLK); + end generate; MED_CTRL_OP_OUT(7 downto 0) <= (others => '0'); MED_CTRL_OP_OUT(8) <= buf_REGIO_COMMON_CTRL_REG_OUT(64+27); diff --git a/trb_net16_endpoint_hades_full_gbe.vhd b/trb_net16_endpoint_hades_full_gbe.vhd index ebb099d..70ee8b2 100644 --- a/trb_net16_endpoint_hades_full_gbe.vhd +++ b/trb_net16_endpoint_hades_full_gbe.vhd @@ -254,6 +254,7 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); signal buf_IDRAM_WR_IN : std_logic; signal reset_no_link : std_logic; + signal reset_no_link_tmp : std_logic; signal ONEWIRE_DATA : std_logic_vector(15 downto 0); signal ONEWIRE_ADDR : std_logic_vector(2 downto 0); signal ONEWIRE_WRITE : std_logic; @@ -340,11 +341,18 @@ begin process(CLK) begin if rising_edge(CLK) then - reset_no_link <= MED_STAT_OP_IN(14) or RESET; + reset_no_link_tmp <= MED_STAT_OP_IN(14) or RESET; reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1); end if; end process; + gen_resetedge : if FPGA_TYPE = 5 generate + reset_no_link <= reset_no_link_tmp when falling_edge(CLK); + else generate + reset_no_link <= reset_no_link_tmp when rising_edge(CLK); + end generate; + + MED_CTRL_OP_OUT(7 downto 0) <= (others => '0'); MED_CTRL_OP_OUT(8) <= buf_REGIO_COMMON_CTRL_REG_OUT(64+27); MED_CTRL_OP_OUT(15 downto 9) <= (others => '0'); diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index ef5519d..67b0438 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -6,6 +6,7 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb_net16_hub_func.all; +use work.config.all; --take care of USE_INPUT_SBUF for multiplexer! @@ -240,6 +241,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal resync : std_logic_vector(MII_NUMBER-1 downto 0); signal reset_i : std_logic; signal reset_i_mux_io : std_logic_vector((MII_NUMBER*2**(c_MUX_WIDTH-1))-1 downto 0); + signal reset_i_tmp : std_logic; signal combined_resync : std_logic; @@ -412,11 +414,17 @@ begin proc_SYNC_RESET : process(CLK) begin if rising_edge(CLK) then - reset_i <= RESET; + reset_i_tmp <= RESET; last_STAT_TIMEOUT <= STAT_TIMEOUT; end if; end process; + gen_resetedge : if FPGA_TYPE = 5 generate --timing via primary clock net gives hold violations for BRAM + reset_i <= reset_i_tmp when falling_edge(CLK); + else generate + reset_i <= reset_i_tmp when rising_edge(CLK); + end generate; + -- STAT_TIMEOUT gen_iobuf_noreset : if RESET_IOBUF_AT_TIMEOUT = c_NO generate -- 2.43.0