From e19686f968f19fe7ae2fce0050d91ab57b0e6b90 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 7 Jul 2015 10:45:31 +0200 Subject: [PATCH] a running pulser --- pulser/code/pulser.vhd | 26 ++++++++++++--------- pulser/code/single_channel_pulser.vhd | 33 ++++++++++++++++++--------- pulser/trb3sc_pulser.lpf | 12 +++++++--- 3 files changed, 46 insertions(+), 25 deletions(-) diff --git a/pulser/code/pulser.vhd b/pulser/code/pulser.vhd index e179e09..d111623 100644 --- a/pulser/code/pulser.vhd +++ b/pulser/code/pulser.vhd @@ -82,6 +82,7 @@ signal control_strobes : std_logic_vector(31 downto 0); signal pulser_enable : std_logic_vector(31 downto 0); signal pulser_invert : std_logic_vector(31 downto 0); signal pulser_reset : std_logic; +signal next_pulser_reset : std_logic; -- type pulse_ddr_t is array(0 to 31) of std_logic_vector(3 downto 0); -- signal pulse : pulse_ddr_t; @@ -106,6 +107,7 @@ multi_ch_pulser_left : for n in 0 to 19 generate PULSE_WIDTH => length(n)(23 downto 0), OFFSET => offset(n)(23 downto 0), INVERT => pulser_invert(n), + ENABLE => pulser_enable(n), PULSE(0) => data_left(0)(n), PULSE(1) => data_left(1)(n), PULSE(2) => data_left(2)(n), @@ -123,6 +125,7 @@ multi_ch_pulser_right : for n in 0 to 9 generate PULSE_WIDTH => length(n+20)(23 downto 0), OFFSET => offset(n+20)(23 downto 0), INVERT => pulser_invert(n+20), + ENABLE => pulser_enable(n+20), PULSE(0) => data_right(0)(n), PULSE(1) => data_right(1)(n), PULSE(2) => data_right(2)(n), @@ -152,8 +155,8 @@ THE_LEFT_DDR : entity work.ddr_20 reset => '0', sclk => clk_slow_left, da0 => data_left(0), - da1 => data_left(1), - db0 => data_left(2), + da1 => data_left(2), + db0 => data_left(1), db1 => data_left(3), q(15 downto 0) => OUTP(16 downto 1), q(19 downto 16) => OUTP_FAN(3 downto 0) @@ -168,8 +171,8 @@ THE_RIGHT_DDR : entity work.ddr_10 reset => '0', sclk => clk_slow_right, da0 => data_right(0), - da1 => data_right(1), - db0 => data_right(2), + da1 => data_right(2), + db0 => data_right(1), db1 => data_right(3), q => OUTP_ANA ); @@ -185,8 +188,9 @@ THE_RIGHT_DDR : entity work.ddr_10 proc_ctrlbus : process begin wait until rising_edge(SYSCLK); BUS_TX.ack <= '0'; BUS_TX.nack <= '0'; BUS_TX.unknown <= '0'; - control_strobes <= (others => '0'); - pulser_reset <= RESET; + control_strobes <= (others => '0'); + next_pulser_reset <= '0'; + pulser_reset <= RESET or next_pulser_reset; if BUS_RX.read = '1' then BUS_TX.ack <= '1'; @@ -201,10 +205,10 @@ THE_RIGHT_DDR : entity work.ddr_10 elsif BUS_RX.addr(7 downto 0) = x"01" then BUS_TX.data <= pulser_invert; elsif BUS_RX.addr(7 downto 0) = x"40" then - BUS_TX.data(3 downto 0) <= ana1_in_select ; + BUS_TX.data(3 downto 0) <= ana1_in_select; BUS_TX.data(9 downto 8) <= ana1_out_select; elsif BUS_RX.addr(7 downto 0) = x"41" then - BUS_TX.data(3 downto 0) <= ana2_in_select ; + BUS_TX.data(3 downto 0) <= ana2_in_select; BUS_TX.data(9 downto 8) <= ana2_out_select; else BUS_TX.ack <= '0'; @@ -215,13 +219,13 @@ THE_RIGHT_DDR : entity work.ddr_10 BUS_TX.ack <= '1'; if BUS_RX.addr(7 downto 5) = "100" then period(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data); - pulser_reset <= '1'; + next_pulser_reset <= '1'; elsif BUS_RX.addr(7 downto 5) = "101" then length(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data); - pulser_reset <= '1'; + next_pulser_reset <= '1'; elsif BUS_RX.addr(7 downto 5) = "110" then offset(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data); - pulser_reset <= '1'; + next_pulser_reset <= '1'; elsif BUS_RX.addr(7 downto 0) = x"00" then pulser_enable <= BUS_RX.data; elsif BUS_RX.addr(7 downto 0) = x"01" then diff --git a/pulser/code/single_channel_pulser.vhd b/pulser/code/single_channel_pulser.vhd index fce6bde..85f565f 100644 --- a/pulser/code/single_channel_pulser.vhd +++ b/pulser/code/single_channel_pulser.vhd @@ -17,6 +17,7 @@ entity single_channel_pulser is PULSE_WIDTH : in unsigned(23 downto 0); OFFSET : in unsigned(23 downto 0); INVERT : in std_logic; + ENABLE : in std_logic; PULSE : out std_logic_vector(3 downto 0) ); @@ -27,8 +28,10 @@ architecture single_channel_pulser_arch of single_channel_pulser is signal timer : unsigned(23 downto 0) := (others => '0'); signal last_timer : unsigned(23 downto 0) := (others => '0'); signal reset_counter : std_logic; +signal frequency_in : unsigned(23 downto 0); signal frequency_i : unsigned(23 downto 0); signal reset_delay : std_logic; +signal pulse_width_in : unsigned(23 downto 0); signal pulse_width_i : unsigned(23 downto 0); type state_type is (idle, generate_pulse, finish); @@ -37,13 +40,21 @@ signal state : state_type; begin +PROC_REGS : process begin + wait until rising_edge(CLK); + if RESET = '1' then + pulse_width_in <= PULSE_WIDTH; + frequency_in <= FREQUENCY; + end if; +end process; + PROC_TIMER : process (CLK) --it counts begin if rising_edge(CLK) then if reset_counter = '1' then - timer <= (others => '0') after 1 ns; + timer <= (others => '0'); else - timer <= timer+1 after 1 ns; + timer <= timer+1; end if; end if; end process; @@ -51,8 +62,8 @@ begin PROC_FREQUENCY : process (CLK) --It eliminates the offset of -2 for the frequency begin if rising_edge(CLK) then - if FREQUENCY >= x"000002" then - frequency_i <= FREQUENCY-2 after 1 ns; + if frequency_in >= x"000002" then + frequency_i <= frequency_in-2; end if; reset_delay <= RESET; --I want the timer to start again after the operations with the frequency end if; @@ -63,9 +74,9 @@ begin begin if rising_edge(CLK) then if reset_delay = '1' or last_timer = frequency_i or RESET = '1' then --was FREQUENCY - reset_counter <= '1' after 1 ns; + reset_counter <= '1'; else - reset_counter <= '0' after 1 ns; + reset_counter <= '0'; end if; end if; end process; @@ -84,19 +95,19 @@ last_timer <= timer when rising_edge(CLK); when idle => PULSE <= "0000"; - pulse_width_i <= PULSE_WIDTH; + pulse_width_i <= pulse_width_in; - if last_timer = x"000000" then + if last_timer = x"000000" and ENABLE = '1' then state <= generate_pulse; end if; when generate_pulse => if pulse_width_i = x"000002" then - PULSE <= "0011" after 1 ns; + PULSE <= "0011"; elsif pulse_width_i = x"000003" then - PULSE <= "0111" after 1 ns; + PULSE <= "0111"; elsif pulse_width_i >= x"000004" then - PULSE <= "1111" after 1 ns; + PULSE <= "1111"; else PULSE <= "0001"; end if; diff --git a/pulser/trb3sc_pulser.lpf b/pulser/trb3sc_pulser.lpf index feb6162..3515067 100644 --- a/pulser/trb3sc_pulser.lpf +++ b/pulser/trb3sc_pulser.lpf @@ -8,10 +8,16 @@ MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_right 20 ns; MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_left 20 ns; -BLOCK PATH TO CELL "THE_PULSER/period*" ; -BLOCK PATH TO CELL "THE_PULSER/length*" ; -BLOCK PATH TO CELL "THE_PULSER/offset*" ; +BLOCK NET "THE_PULSER/period*" ; +BLOCK NET "THE_PULSER/length*" ; +BLOCK NET "THE_PULSER/offset*" ; +BLOCK NET "THE_PULSER/pulser_reset*" ; +BLOCK NET "THE_PULSER/pulser_enable*" ; + +CLOCK_TO_OUT "OUTP*" 30 NS CLKNET = "THE_PULSER/THE_LEFT_DDR/clkop"; +CLOCK_TO_OUT "OUTP*" 30 NS CLKNET = "THE_PULSER/THE_RIGHT_DDR/clkop"; +CLOCK_TO_OUT "SEL*" 40 NS CLKNET = "clk_sys"; # REGION "REGION_PULSER_LEFT" "R2C2D" 114 36 DEVSIZE; -- 2.43.0