From e2e69021536ad92ac32928055ca5c43c33d466ae Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 6 Oct 2010 12:42:44 +0000 Subject: [PATCH] *** empty log message *** --- media_interfaces/trb_net16_rx_checker.vhd | 2 +- .../trb_net16_rx_comma_handler.vhd | 16 ++--- media_interfaces/trb_net16_rx_control.vhd | 53 ++++++++++++++- media_interfaces/trb_net16_tx_control.vhd | 33 +++++----- testbenches/error_generator.vhd | 64 +++++++++---------- testbenches/tb_trb_net16_rxtx_control.vhd | 11 +++- trb_net_CRC8.vhd | 12 ++-- trb_net_components.vhd | 11 ++++ 8 files changed, 135 insertions(+), 67 deletions(-) diff --git a/media_interfaces/trb_net16_rx_checker.vhd b/media_interfaces/trb_net16_rx_checker.vhd index 759014d..427a844 100644 --- a/media_interfaces/trb_net16_rx_checker.vhd +++ b/media_interfaces/trb_net16_rx_checker.vhd @@ -76,7 +76,7 @@ begin end process STATE_MEM; -- state transitions -STATE_TRANSFORM: process( current_state, PKT_TOC_IN, RX_IC_IN, STX_FND_IN, PKT_IN_TRANS_IN ) +STATE_TRANSFORM: process( current_state, PKT_TOC_IN, RX_IC_IN, STX_FND_IN, PKT_IN_TRANS_IN, STX_TOC_IN ) begin next_state <= IDLE; -- avoid latches fifo_rst_x <= '0'; diff --git a/media_interfaces/trb_net16_rx_comma_handler.vhd b/media_interfaces/trb_net16_rx_comma_handler.vhd index 0f5d267..21d59e1 100644 --- a/media_interfaces/trb_net16_rx_comma_handler.vhd +++ b/media_interfaces/trb_net16_rx_comma_handler.vhd @@ -118,7 +118,7 @@ signal crc_match : std_logic; signal crc_reset : std_logic; -- gk 05.10.10 -signal start_toc : std_logic_vector(7 downto 0); +signal start_toc : unsigned(7 downto 0); signal start_toc_c : std_logic; begin @@ -274,10 +274,10 @@ fifo_wr_x <= comma_toggle and data_valid_x and not fifo_inhibit; THE_FIFO_INHIBIT_PROC: process( CLK_IN ) begin if( rising_edge(CLK_IN) ) then - if ( (RESET_IN = '1') or (comma_stx = '1') or (ENABLE_CORRECTION_IN = '0') or (start_toc_c = '1') )then -- gk 05.10.10 + if ( (RESET_IN = '1') or (comma_stx = '1') or (ENABLE_CORRECTION_IN = '0') )then -- gk 05.10.10 fifo_inhibit <= '0'; elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') and c_reset_x = '0' ) - or (crc_match = '0' and comma_crc_x = '1' and crc_active = '1') + or ((crc_match = '0' or buf_rx_cv = '1') and comma_crc_x = '1' and crc_active = '1') or c_invalid_k_x = '1' or START_GONE_WRONG_IN = '1' then fifo_inhibit <= '1'; @@ -289,16 +289,16 @@ end process THE_FIFO_INHIBIT_PROC; START_TOC_PROC : process(CLK_IN) begin if rising_edge(CLK_IN) then - if (RESET_IN = '1') or (fifo_inhibit = '0') then + if (RESET_IN = '1') or (fifo_inhibit = '0') or start_toc_c = '1' then start_toc <= (others => '0'); elsif (fifo_inhibit = '1') and (comma_stx = '0') then - start_toc <= start_toc + x"1"; - end if; + start_toc <= start_toc + to_unsigned(1,1); + end if; end if; end process START_TOC_PROC; -- gk 05.10.10 -start_toc_c <= '1' when (start_toc >= x"c8") else '0'; +start_toc_c <= '1' when (start_toc >= to_unsigned(200,8)) else '0'; -- gk 05.10.10 START_TOC_OUT_PROC : process(CLK_IN) @@ -324,7 +324,7 @@ THE_CRC : trb_net_CRC8 ); crc_reset <= RESET_IN or (fifo_inhibit and not comma_stx) or (not crc_active and not comma_crc); - crc_enable <= (not buf_rx_k and not (comma_idle_x or comma_error_x or comma_stx_x or comma_crc_x)) or comma_crc_x; + crc_enable <= ((not buf_rx_k and not (comma_idle_x or comma_error_x or comma_stx_x or comma_crc_x)) or comma_crc_x) and not buf_rx_cv; ---------------------------------------------------------------------- diff --git a/media_interfaces/trb_net16_rx_control.vhd b/media_interfaces/trb_net16_rx_control.vhd index 6f6f042..b5eda04 100644 --- a/media_interfaces/trb_net16_rx_control.vhd +++ b/media_interfaces/trb_net16_rx_control.vhd @@ -67,6 +67,8 @@ port( RX_POSITION_OUT : out std_logic_vector(7 downto 0); LD_START_POSITION_OUT : out std_logic; START_POSITION_OUT : out std_logic_vector(7 downto 0); + START_GONE_WRONG_IN : in std_logic; + START_TIMEOUT_OUT : out std_logic; -- Check COMMA_LOCKED_OUT : out std_logic; -- reset handling @@ -117,6 +119,7 @@ port( PKT_TOC_IN : in std_logic; -- full packet RX timeout RX_IC_IN : in std_logic; -- illegal comma or CodeViolation on RX STX_FND_IN : in std_logic; -- StartOfTransmission found on RX + STX_TOC_IN : in std_logic; -- timeout waiting for StartOfTransmission PKT_IN_TRANS_IN : in std_logic; -- paket in transmission to media interface -- control signals FIFO_RST_OUT : out std_logic; -- clear RX FIFO @@ -212,7 +215,12 @@ signal statreg_rxfullpackets : std_logic_vector(15 downto 0); signal statreg_rxcommahandler : std_logic_vector(15 downto 0); signal statreg_rxchecker : std_logic_vector(15 downto 0); +signal start_position_mismatch : std_logic; +signal start_position_mismatch_x : std_logic; +signal req_position_buffer : std_logic_vector(7 downto 0); +signal stx_toc_found_x : std_logic; +signal stx_toc_found : std_logic; begin @@ -239,6 +247,8 @@ port map( RX_POSITION_OUT => rx_position, LD_START_POSITION_OUT => start_retransmit_x, START_POSITION_OUT => start_position, + START_GONE_WRONG_IN => start_position_mismatch, + START_TIMEOUT_OUT => stx_toc_found_x, -- Check COMMA_LOCKED_OUT => comma_locked, -- reset handling @@ -250,6 +260,28 @@ port map( DEBUG_OUT => debug_rch ); +-- clock domain transfer for restart gone wrong +THE_STX_PULSE_SYNC: pulse_sync +port map( + CLK_A_IN => SYSCLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => start_position_mismatch_x, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => start_position_mismatch +); + +-- clock domain transfer for internal RX data counter +THE_STX_TOC_PULSE_SYNC: pulse_sync +port map( + CLK_A_IN => CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => stx_toc_found_x, + CLK_B_IN => SYSCLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => stx_toc_found +); + -- clock domain transfer for internal RX data counter THE_LD_PULSE_SYNC: pulse_sync port map( @@ -353,7 +385,7 @@ port map( -- Status signals RX_ALLOW_IN => RX_ALLOW_IN, RX_RESUME_IN => rx_resume, - RX_LD_DATA_CTR_IN => ld_rx_position, + RX_LD_DATA_CTR_IN => '0', --ld_rx_position, RX_DATA_CTR_VAL_IN => rx_position, RX_DATA_CTR_OUT => request_position, PACKET_TIMEOUT_OUT => packet_timeout, @@ -385,6 +417,7 @@ port map( RX_IC_IN => rx_gone_wrong, STX_FND_IN => ld_rx_position, PKT_IN_TRANS_IN => pkt_in_transit, + STX_TOC_IN => stx_toc_found, -- control signals FIFO_RST_OUT => fifo_rst, RESUME_OUT => rx_resume, @@ -394,6 +427,24 @@ port map( DBG_OUT => debug_rxc ); + +---------------------------------------------------------------------- +-- Check start +---------------------------------------------------------------------- +process(SYSCLK_IN) + begin + if rising_edge(SYSCLK_IN) then + start_position_mismatch_x <= '0'; + if request_retransmit = '1' then + req_position_buffer <= request_position; + elsif ld_rx_position = '1' then + if req_position_buffer /= rx_position then + start_position_mismatch_x <= '1'; + end if; + end if; + end if; + end process; + ---------------------------------------------------------------------- -- Debug signals ---------------------------------------------------------------------- diff --git a/media_interfaces/trb_net16_tx_control.vhd b/media_interfaces/trb_net16_tx_control.vhd index 49deb70..c56e951 100644 --- a/media_interfaces/trb_net16_tx_control.vhd +++ b/media_interfaces/trb_net16_tx_control.vhd @@ -148,15 +148,15 @@ begin end if; end process; -ct_fifo_reset <= not tx_allow_qtx; -TX_READ_OUT <= buf_tx_read_out; + ct_fifo_reset <= not tx_allow_qtx; + TX_READ_OUT <= buf_tx_read_out; -ct_fifo_write<= buf_tx_read_out and TX_WRITE_IN; -ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty; + ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN; + ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty; --- gk 05.10.10 -save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0'; -save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0'; + -- gk 05.10.10 + save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0'; + save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0'; ---------------------------------------------------------------------- -- RAM @@ -465,14 +465,14 @@ save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0'; -- gk 05.10.10 CRC_CALC : trb_net_CRC8 - port map( - CLK => TXCLK_IN, - RESET => crc_reset, - CLK_EN => crc_en, - DATA_IN => crc_data, - CRC_OUT => crc_q, - CRC_match => open - ); + port map( + CLK => TXCLK_IN, + RESET => crc_reset, + CLK_EN => crc_en, + DATA_IN => crc_data, + CRC_OUT => crc_q, + CRC_match => open + ); ---------------------------------------------------------------------- @@ -497,7 +497,8 @@ save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0'; STAT_REG_OUT(19) <= TX_ALLOW_IN; STAT_REG_OUT(20) <= make_restart_i; STAT_REG_OUT(21) <= make_request_i; - STAT_REG_OUT(31 downto 22) <= (others => '0'); + STAT_REG_OUT(22) <= load_eop; + STAT_REG_OUT(31 downto 23) <= (others => '0'); end if; end process; diff --git a/testbenches/error_generator.vhd b/testbenches/error_generator.vhd index 17d183d..27a8a97 100644 --- a/testbenches/error_generator.vhd +++ b/testbenches/error_generator.vhd @@ -50,7 +50,7 @@ begin UNIFORM(seed1, seed2, rand); int_rand := INTEGER(TRUNC(rand * 1000000.0)); - if( (int_rand MOD 100) = 0 ) then + if( (int_rand MOD 1000) = 0 ) then buf_RX1_CV_OUT <= not RX1_CV_IN; assert false report "RX1_CV" severity note; wait for 40 ns; @@ -88,40 +88,40 @@ end process; -- end process; --- RD1_DATA_proc : process --- variable seed1 : positive; --- variable seed2 : positive := 3; --- variable rand : real; --- variable int_rand : integer; --- begin --- --- wait until rising_edge(RXCLK_IN); --- --- UNIFORM(seed1, seed2, rand); --- int_rand := INTEGER(TRUNC(rand * 256.0)); --- --- if( (int_rand MOD 40) = 0 ) then --- --- UNIFORM(seed1, seed2, rand); --- int_rand := INTEGER(TRUNC(rand * 256.0)); --- --- buf_RX1_DATA_OUT(int_rand mod 8) <= not RX1_DATA_IN(int_rand mod 8); --- --- assert false report "RX1_DATA" severity note; --- --- wait for 40 ns; --- buf_RX1_DATA_OUT <= RX1_DATA_IN; --- else --- buf_RX1_DATA_OUT <= RX1_DATA_IN; --- end if; --- --- wait for 400 ns; --- --- end process; +RD1_DATA_proc : process +variable seed1 : positive; +variable seed2 : positive := 3; +variable rand : real; +variable int_rand : integer; +begin + + wait until rising_edge(RXCLK_IN); + + UNIFORM(seed1, seed2, rand); + int_rand := INTEGER(TRUNC(rand * 1000000.0)); + + if( (int_rand MOD 200) = 0 ) then + + UNIFORM(seed1, seed2, rand); + int_rand := INTEGER(TRUNC(rand * 256.0)); + + buf_RX1_DATA_OUT <= RX1_DATA_IN; + buf_RX1_DATA_OUT(int_rand mod 8) <= not RX1_DATA_IN(int_rand mod 8); + + assert false report "RX1_DATA" severity note; + + wait for 40 ns; + buf_RX1_DATA_OUT <= RX1_DATA_IN; + else + buf_RX1_DATA_OUT <= RX1_DATA_IN; + end if; + + +end process; process begin wait until rising_edge(RXCLK_IN); - buf_RX1_DATA_OUT <= RX1_DATA_IN; +-- buf_RX1_DATA_OUT <= RX1_DATA_IN; buf_RX1_K_OUT <= RX1_K_IN; end process; diff --git a/testbenches/tb_trb_net16_rxtx_control.vhd b/testbenches/tb_trb_net16_rxtx_control.vhd index 6e5f5e5..e16e569 100644 --- a/testbenches/tb_trb_net16_rxtx_control.vhd +++ b/testbenches/tb_trb_net16_rxtx_control.vhd @@ -20,6 +20,7 @@ architecture arch of rxtxtb is RESET_IN : in std_logic; TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); TX_WRITE_IN : in std_logic; TX_READ_OUT : out std_logic; @@ -140,6 +141,8 @@ architecture arch of rxtxtb is signal rx2_cv_in : std_logic := '0'; signal rx2_allow_in : std_logic := '0'; + signal tx1_packet_num_in : std_logic_vector(2 downto 0); + signal tx2_packet_num_in : std_logic_vector(2 downto 0); signal tx1_request_retransmit_in : std_logic := '0'; signal tx1_request_position_in : std_logic_vector( 7 downto 0) := (others => '0'); @@ -231,7 +234,7 @@ begin wait until rising_edge(clk); wait for 1 ns; rx1_allow_in <= '1'; rx2_allow_in <= '1'; - wait for 2050 ns; + wait for 3050 ns; wait until rising_edge(clk); wait for 1 ns; tx1_allow_in <= '1'; tx2_allow_in <= '1'; @@ -251,6 +254,7 @@ begin RESET_IN => reset, TX_DATA_IN => tx1_data_in, + TX_PACKET_NUMBER_IN => tx1_packet_num_in, TX_WRITE_IN => tx1_write_in, TX_READ_OUT => tx1_read_out, @@ -277,6 +281,7 @@ begin RESET_IN => reset, TX_DATA_IN => tx2_data_in, + TX_PACKET_NUMBER_IN => tx2_packet_num_in, TX_WRITE_IN => tx2_write_in, TX_READ_OUT => tx2_read_out, @@ -502,7 +507,7 @@ THE_ERROR : error_generator MED_READ_OUT => open, MED_DATAREADY_OUT => tx1_write_in, MED_DATA_OUT => tx1_data_in, - MED_PACKET_NUM_OUT => open, + MED_PACKET_NUM_OUT => tx1_packet_num_in, MED_READ_IN => tx1_read_out, -- Internal direction port INT_DATA_OUT => open, @@ -549,7 +554,7 @@ THE_ERROR : error_generator MED_READ_OUT => rxread2_out, MED_DATAREADY_OUT => open, MED_DATA_OUT => open, - MED_PACKET_NUM_OUT => open, + MED_PACKET_NUM_OUT => tx2_packet_num_in, MED_READ_IN => '1', -- Internal direction port INT_DATA_OUT(15 downto 0) => rxdata2, diff --git a/trb_net_CRC8.vhd b/trb_net_CRC8.vhd index 23482ec..1e0ad73 100644 --- a/trb_net_CRC8.vhd +++ b/trb_net_CRC8.vhd @@ -34,7 +34,7 @@ architecture imp_crc of trb_net_CRC8 is signal lfsr_c: std_logic_vector (7 downto 0); begin CRC_OUT <= lfsr_q; - CRC_match <= not and_all(lfsr_q); + CRC_match <= not or_all(lfsr_c); lfsr_c(0) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor data_in(0) xor data_in(3) xor data_in(4) xor data_in(6); lfsr_c(1) <= lfsr_q(1) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor data_in(1) xor data_in(4) xor data_in(5) xor data_in(7); @@ -46,11 +46,11 @@ begin lfsr_c(7) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor data_in(2) xor data_in(3) xor data_in(5); - process (CLK,RESET) begin - if (RESET = '1') then - lfsr_q <= b"00000000"; - elsif rising_edge(CLK) then - if (CLK_EN = '1') then + process (CLK) begin + if rising_edge(CLK) then + if (RESET = '1') then + lfsr_q <= b"00000000"; + elsif (CLK_EN = '1') then lfsr_q <= lfsr_c; end if; end if; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index df75e12..3614ed6 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -274,6 +274,16 @@ end component trb_net16_med_scm_sfp_gbe; end component; + component trb_net_CRC8 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + CRC_OUT : out std_logic_vector(7 downto 0); + CRC_match : out std_logic + ); + end component; component ddr_off is port ( @@ -2830,6 +2840,7 @@ end component; RESET_IN : in std_logic; TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); TX_WRITE_IN : in std_logic; TX_READ_OUT : out std_logic; -- 2.43.0