From e3c51d86ee9727502524dd1982b9546e4696f1ad Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 6 Nov 2007 12:20:50 +0000 Subject: [PATCH] renamed some files --- trb_net16_endpoint_0_trg_1_api.vhd | 646 +++++++++++++++++++++++ trb_net16_endpoint_1_trg_0_api.vhd | 468 +++++++++++++++++ trb_net16_endpoint_1_trg_1_api.vhd | 797 +++++++++++++++++++++++++++++ trb_net16_hub_base.vhd | 450 ++++++++++++++++ trb_net16_hub_logic.vhd | 107 ++++ 5 files changed, 2468 insertions(+) create mode 100644 trb_net16_endpoint_0_trg_1_api.vhd create mode 100644 trb_net16_endpoint_1_trg_0_api.vhd create mode 100644 trb_net16_endpoint_1_trg_1_api.vhd create mode 100644 trb_net16_hub_base.vhd create mode 100644 trb_net16_hub_logic.vhd diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd new file mode 100644 index 0000000..5e209c7 --- /dev/null +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -0,0 +1,646 @@ +-- an active api together with an iobuf + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + +--Entity decalaration for clock generator +entity trb_net16_endpoint_0_trg_1_api is + + generic ( + API_TYPE : integer range 0 to 1 := 1; + INIT_DEPTH : integer range 0 to 6 := 0; + REPLY_DEPTH : integer range 0 to 6 := 1; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 1; + FIFO_TO_APL_DEPTH : integer range 0 to 6 := 1; + SBUF_VERSION : integer range 0 to 1 := 0; + MUX_WIDTH : integer range 1 to 5 := 3; + MUX_SECURE_MODE : integer range 0 to 1 := 0; + DAT_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 0; + DATA_WIDTH : integer := 16; + NUM_WIDTH : integer := 2 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_READ_IN: in std_logic; -- Media is reading + + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_READ_OUT: out std_logic; -- buffer reads a word from media + MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + + -- APL Transmitter port + APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in std_logic; -- + APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out + APL_READ_IN: in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT: out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + + -- Status and control port => just coming from the iobuf for debugging + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + STAT_api_control_signals: out std_logic_vector(31 downto 0); + STAT_MPLEX: out std_logic_vector(31 downto 0); + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); + MPLEX_CTRL: in std_logic_vector (31 downto 0); + API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); +end entity; + +architecture trb_net16_endpoint_0_trg_1_api_arch of trb_net16_endpoint_0_trg_1_api is + +component trb_net16_iobuf is + + generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if + -- the initibuf + REPLY_DEPTH : integer := 3); -- or the replyibuf + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; -- Media is reading + + MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media + MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; -- Media is reading + + MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media + MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + -- Internal direction port + + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_READ_IN: in std_logic; + + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT: out std_logic; + + INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) + ); +end component; + +component trb_net16_base_api is + generic ( + API_TYPE : integer := 1; + FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), + -- for the direction to + -- internal world + FIFO_TO_APL_DEPTH : integer := 3; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + SBUF_VERSION : integer range 0 to 1 := 0 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in std_logic; -- + APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out + APL_READ_IN: in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT: out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + + -- Internal direction port + -- This is just a clone from trb_net_iobuf + + INT_MASTER_DATAREADY_OUT: out std_logic; + INT_MASTER_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_MASTER_READ_IN: in std_logic; + + INT_MASTER_DATAREADY_IN: in std_logic; + INT_MASTER_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_MASTER_READ_OUT: out std_logic; + + + INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the SLAVE path) + INT_SLAVE_DATAREADY_OUT: out std_logic; + INT_SLAVE_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_SLAVE_READ_IN: in std_logic; + + INT_SLAVE_DATAREADY_IN: in std_logic; + INT_SLAVE_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_SLAVE_READ_OUT: out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); +end component; + + + +component trb_net16_io_multiplexer is + + generic ( + DATA_WIDTH : integer := 16; + NUM_WIDTH : integer := 2; + MUX_WIDTH : integer range 1 to 5 := 3; + MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); + -- highest bits are mult. + MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_READ_OUT: out std_logic; + + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_READ_IN: in std_logic; + + -- Internal direction port + INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + + INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + + -- Status and control port + CTRL: in std_logic_vector (31 downto 0); + STAT: out std_logic_vector (31 downto 0) + ); +end component; + + component trb_net16_term_buf is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; + MED_INIT_DATAREADY_IN: in std_logic; + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; + MED_REPLY_DATAREADY_IN: in std_logic; + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic + ); + end component; + +signal apl_to_buf_INIT_DATAREADY: std_logic; +signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0); +signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0); +signal apl_to_buf_INIT_READ : std_logic; + +signal buf_to_apl_INIT_DATAREADY: std_logic; +signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0); +signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0); +signal buf_to_apl_INIT_READ : std_logic; + +signal apl_to_buf_REPLY_DATAREADY: std_logic; +signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0); +signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); +signal apl_to_buf_REPLY_READ : std_logic; + +signal buf_to_apl_REPLY_DATAREADY: std_logic; +signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0); +signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); +signal buf_to_apl_REPLY_READ : std_logic; + +-- for the connection to the multiplexer +signal MED_INIT_DATAREADY_OUT : std_logic; +signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0); +signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0); +signal MED_INIT_READ_IN : std_logic; + +signal MED_INIT_DATAREADY_IN : std_logic; +signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0); +signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0); +signal MED_INIT_READ_OUT : std_logic; + +signal MED_REPLY_DATAREADY_OUT : std_logic; +signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0); +signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0); +signal MED_REPLY_READ_IN : std_logic; + +signal MED_REPLY_DATAREADY_IN : std_logic; +signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0); +signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0); +signal MED_REPLY_READ_OUT : std_logic; + +signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); +signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); + +signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); +signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); + +signal buf_STAT_INIT_BUFFER : std_logic_vector (31 downto 0); +signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (31 downto 0); + +begin + + --Connections for data channel + genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate + gendat: if i = DAT_CHANNEL generate + m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT; + m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; + MED_INIT_READ_IN <= m_READ_IN(i*2); + MED_REPLY_READ_IN <= m_READ_IN(i*2+1); + MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); + MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); + MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); + MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); + MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); + MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + m_READ_OUT(i*2) <= MED_INIT_READ_OUT; + m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT; + end generate; + genelse: if i /= DAT_CHANNEL generate + termbuf: trb_net16_term_buf + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), + MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), + MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), + MED_INIT_READ_OUT => m_READ_OUT(i*2), + + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), + MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), + MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), + MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) + ); + end generate; + end generate; + + + + gen_actapi: if API_TYPE = 1 generate + DAT_ACTIVE_API: trb_net16_base_api + generic map ( + API_TYPE => 1, + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, + FIFO_TERM_BUFFER_DEPTH => 0, + SBUF_VERSION => SBUF_VERSION + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN, + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, + APL_WRITE_IN => APL_WRITE_IN, + APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, + APL_SEND_IN => APL_SEND_IN, + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT, + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, + APL_TYP_OUT => APL_TYP_OUT, + APL_DATAREADY_OUT => APL_DATAREADY_OUT, + APL_READ_IN => APL_READ_IN, + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT, + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT, + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA, + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM, + INT_MASTER_READ_IN => apl_to_buf_INIT_READ, + INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, + INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA, + INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM, + INT_MASTER_READ_OUT => buf_to_apl_INIT_READ, + INT_SLAVE_HEADER_IN => '0', + INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, + INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA, + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM, + INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ, + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA, + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM, + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ, + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int, + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl + ); + end generate; + + gen_pasapi: if API_TYPE = 0 generate + DAT_PASSIVE_API: trb_net16_base_api + generic map ( + API_TYPE => 0, + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, + FIFO_TERM_BUFFER_DEPTH => 0, + SBUF_VERSION => SBUF_VERSION + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN, + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, + APL_WRITE_IN => APL_WRITE_IN, + APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, + APL_SEND_IN => APL_SEND_IN, + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT, + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, + APL_TYP_OUT => APL_TYP_OUT, + APL_DATAREADY_OUT => APL_DATAREADY_OUT, + APL_READ_IN => APL_READ_IN, + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT, + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT, + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA, + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM, + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ, + INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, + INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA, + INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM, + INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ, + INT_SLAVE_HEADER_IN => '0', + INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, + INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA, + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM, + INT_SLAVE_READ_IN => apl_to_buf_INIT_READ, + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA, + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM, + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ, + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int, + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl + ); + end generate; +api_stat_fifo_to_apl <= buf_api_stat_fifo_to_apl; +api_stat_fifo_to_int <= buf_api_stat_fifo_to_int; + +STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); +STAT_api_control_signals(3) <= APL_WRITE_IN; +STAT_api_control_signals(4) <= APL_SEND_IN; +STAT_api_control_signals(7 downto 5) <= (others => '0'); +STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0); +STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY; +STAT_api_control_signals(12) <= apl_to_buf_INIT_READ; +STAT_api_control_signals(28 downto 13) <= (others => '0'); + +STAT_api_control_signals(31) <= buf_to_apl_INIT_READ; +--STAT_api_control_signals(30) <= buf_to_apl_INIT_PACKET_NUM(0); +--STAT_api_control_signals(29) <= buf_to_apl_INIT_DATAREADY; +STAT_api_control_signals(30) <= buf_api_stat_fifo_to_apl(3); +STAT_api_control_signals(29) <= buf_api_stat_fifo_to_apl(14); + + +IOBUF: trb_net16_iobuf + + generic map (INIT_DEPTH => INIT_DEPTH, + REPLY_DEPTH => REPLY_DEPTH) + + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, + MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, + MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT, + MED_INIT_READ_IN => MED_INIT_READ_IN, + + MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, + MED_INIT_DATA_IN => MED_INIT_DATA_IN, + MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN, + MED_INIT_READ_OUT => MED_INIT_READ_OUT, + MED_INIT_ERROR_IN => (others => '0'), + + MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, + MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, + MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT, + MED_REPLY_READ_IN => MED_REPLY_READ_IN, + + MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, + MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, + MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN, + MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, + MED_REPLY_ERROR_IN => (others => '0'), + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM, + INT_INIT_READ_IN => buf_to_apl_INIT_READ, + + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM, + INT_INIT_READ_OUT => apl_to_buf_INIT_READ, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM, + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, + + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM, + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, + + -- Status and control port + STAT_GEN => STAT_GEN, + STAT_LOCKED => STAT_LOCKED, + STAT_INIT_BUFFER => buf_STAT_INIT_BUFFER, + STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, + CTRL_GEN => CTRL_GEN, + CTRL_LOCKED => CTRL_LOCKED, + STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, + STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER + ); + +STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER; + + MPLEX: trb_net16_io_multiplexer + generic map ( + DATA_WIDTH => DATA_WIDTH, + NUM_WIDTH => NUM_WIDTH, + MUX_WIDTH => MUX_WIDTH, + MUX_SECURE_MODE => MUX_SECURE_MODE + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => m_DATAREADY_IN, + INT_DATA_OUT => m_DATA_IN, + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, + INT_READ_IN => m_READ_OUT, + INT_DATAREADY_IN => m_DATAREADY_OUT, + INT_DATA_IN => m_DATA_OUT, + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, + INT_READ_OUT => m_READ_IN, + CTRL => MPLEX_CTRL + ); + +end architecture; + diff --git a/trb_net16_endpoint_1_trg_0_api.vhd b/trb_net16_endpoint_1_trg_0_api.vhd new file mode 100644 index 0000000..a14d008 --- /dev/null +++ b/trb_net16_endpoint_1_trg_0_api.vhd @@ -0,0 +1,468 @@ +-- a trigger receiver - as simple as possible + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + +--Entity decalaration for clock generator +entity trb_net16_endpoint_1_trg_0_api is + + generic ( + TRG_INIT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), if + -- the initibuf + TRG_REPLY_DEPTH : integer := 0; -- or the replyibuf + MUX_WIDTH : integer := 3; + MUX_SECURE_MODE : integer := 0; + TRG_CHANNEL : integer := 0; + DATA_WIDTH : integer := 16; --not to be changed + NUM_WIDTH : integer := 2; --not to be changed + TRG_SECURE_MODE : integer := 0 -- if 0, error pattern and dtype must be valid until next + -- trigger comes in. if 1 these can be valid on falling edge of hold_trm only + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; -- Media is reading + + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; -- buffer reads a word from media + MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + TRG_GOT_TRIGGER_OUT : out std_logic; + TRG_DTYPE_OUT : out std_logic_vector(3 downto 0); + TRG_SEQNR_OUT : out std_logic_vector(7 downto 0); + TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + TRG_RELEASE_IN : in std_logic; + + -- Status and control port => just coming from the iobuf for debugging + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + STAT_api_control_signals: out std_logic_vector(31 downto 0); + STAT_MPLEX: out std_logic_vector(31 downto 0); + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); + MPLEX_CTRL: in std_logic_vector (31 downto 0); + API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); +end entity; + +architecture trb_net16_endpoint_1_trg_0_api_arch of trb_net16_endpoint_1_trg_0_api is + + component trb_net16_iobuf is + generic (INIT_DEPTH : integer := TRG_INIT_DEPTH; -- Depth of the FIFO, 2^(n+1), if + -- the initibuf + REPLY_DEPTH : integer := TRG_REPLY_DEPTH); -- or the replyibuf + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; -- Media is reading + MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media + MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; -- Media is reading + MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media + MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + -- Internal direction port + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_READ_IN: in std_logic; + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT: out std_logic; + INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) + ); + end component; + component trb_net16_io_multiplexer is + generic ( + DATA_WIDTH : integer := DATA_WIDTH; + NUM_WIDTH : integer := NUM_WIDTH; + MUX_WIDTH : integer range 1 to 5 := MUX_WIDTH; + MUX_SECURE_MODE : integer range 0 to 1 := MUX_SECURE_MODE --use sbufs or not? + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); + -- highest bits are mult. + MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_READ_OUT: out std_logic; + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_READ_IN: in std_logic; + -- Internal direction port + INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + -- Status and control port + CTRL: in std_logic_vector (31 downto 0); + STAT: out std_logic_vector (31 downto 0) + ); + end component; + component trb_net16_term is + generic ( + FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + SECURE_MODE : integer range 0 to 1 := TRG_SECURE_MODE + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these must be available when hold_trm goes low + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + INT_READ_IN: in std_logic; + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_READ_OUT: out std_logic; + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + APL_GOT_TRM: out std_logic; + APL_RELEASE_TRM: in std_logic; + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr + -- Status and control port + ); + end component; + component trb_net16_term_buf is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; + MED_INIT_DATAREADY_IN: in std_logic; + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; + MED_REPLY_DATAREADY_IN: in std_logic; + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic + ); + end component; + + signal apl_to_buf_INIT_DATAREADY: std_logic; + signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0); + signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0); + signal apl_to_buf_INIT_READ : std_logic; + + signal buf_to_apl_INIT_DATAREADY: std_logic; + signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0); + signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0); + signal buf_to_apl_INIT_READ : std_logic; + + signal apl_to_buf_REPLY_DATAREADY: std_logic; + signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0); + signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); + signal apl_to_buf_REPLY_READ : std_logic; + + signal buf_to_apl_REPLY_DATAREADY: std_logic; + signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0); + signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); + signal buf_to_apl_REPLY_READ : std_logic; + + -- for the connection to the multiplexer + signal MED_INIT_DATAREADY_OUT : std_logic; + signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0); + signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0); + signal MED_INIT_READ_IN : std_logic; + + signal MED_INIT_DATAREADY_IN : std_logic; + signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0); + signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0); + signal MED_INIT_READ_OUT : std_logic; + + signal MED_REPLY_DATAREADY_OUT : std_logic; + signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0); + signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0); + signal MED_REPLY_READ_IN : std_logic; + + signal MED_REPLY_DATAREADY_IN : std_logic; + signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0); + signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0); + signal MED_REPLY_READ_OUT : std_logic; + +signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); +signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*(2**MUX_WIDTH)-1 downto 0); +signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*(2**MUX_WIDTH)-1 downto 0); +signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); + +signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); +signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); + +begin +------------------------------------------------- +--Connection between multiplexer and iobuf +------------------------------------------------- + --Connections for data and trigger channel + genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate + gentrg: if i = TRG_CHANNEL generate + m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT; + m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; + MED_INIT_READ_IN <= m_READ_IN(i*2); + MED_REPLY_READ_IN <= m_READ_IN(i*2+1); + MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); + MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); + MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); + MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); + MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); + MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + m_READ_OUT(i*2) <= MED_INIT_READ_OUT; + m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT; + end generate; + genelse: if i /= TRG_CHANNEL generate + termbuf: trb_net16_term_buf + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), + MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), + MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), + MED_INIT_READ_OUT => m_READ_OUT(i*2), + + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), + MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), + MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), + MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) + ); + end generate; + end generate; + +IOBUF: trb_net16_iobuf + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, + MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, + MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT, + MED_INIT_READ_IN => MED_INIT_READ_IN, + MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, + MED_INIT_DATA_IN => MED_INIT_DATA_IN, + MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN, + MED_INIT_READ_OUT => MED_INIT_READ_OUT, + MED_INIT_ERROR_IN => (others => '0'), + MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, + MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, + MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT, + MED_REPLY_READ_IN => MED_REPLY_READ_IN, + MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, + MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, + MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN, + MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, + MED_REPLY_ERROR_IN => (others => '0'), + -- Internal direction port + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM, + INT_INIT_READ_IN => buf_to_apl_INIT_READ, + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM, + INT_INIT_READ_OUT => apl_to_buf_INIT_READ, + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM, + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM, + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, + -- Status and control port + STAT_GEN => STAT_GEN, + STAT_LOCKED => STAT_LOCKED, + STAT_INIT_BUFFER => STAT_INIT_BUFFER, + STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, + CTRL_GEN => CTRL_GEN, + CTRL_LOCKED => CTRL_LOCKED, + STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, + STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER + ); + + MPLEX: trb_net16_io_multiplexer + generic map ( + DATA_WIDTH => DATA_WIDTH, + NUM_WIDTH => NUM_WIDTH, + MUX_WIDTH => MUX_WIDTH, + MUX_SECURE_MODE => MUX_SECURE_MODE + ) + port map ( + CLK => CLK, + RESET => RESET , + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => m_DATAREADY_IN, + INT_DATA_OUT =>m_DATA_IN, + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, + INT_READ_IN =>m_READ_OUT, + INT_DATAREADY_IN =>m_DATAREADY_OUT, + INT_DATA_IN =>m_DATA_OUT, + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, + INT_READ_OUT =>m_READ_IN, + CTRL => MPLEX_CTRL + ); + + + TRM_INIT : trb_net16_term + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, + INT_DATA_OUT => apl_to_buf_REPLY_DATA, + INT_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM, + INT_READ_IN => apl_to_buf_REPLY_READ, + INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, + INT_DATA_IN => buf_to_apl_INIT_DATA, + INT_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM, + INT_READ_OUT => buf_to_apl_INIT_READ, + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT => TRG_DTYPE_OUT, + APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT, + APL_SEQNR_OUT => TRG_SEQNR_OUT, + APL_GOT_TRM => TRG_GOT_TRIGGER_OUT, + APL_RELEASE_TRM => TRG_RELEASE_IN, + APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN + -- Status and control port + ); + + +-- TRM_REPLY : trb_net16_term +-- port map( +-- -- Misc +-- CLK => CLK, +-- RESET => RESET, +-- CLK_EN => CLK_EN, +-- INT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, +-- INT_DATA_OUT => apl_to_buf_INIT_DATA, +-- INT_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM, +-- INT_READ_IN => apl_to_buf_INIT_READ, +-- INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, +-- INT_DATA_IN => buf_to_apl_REPLY_DATA, +-- INT_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM, +-- INT_READ_OUT => buf_to_apl_REPLY_READ, +-- -- "mini" APL, just to see the triggers coming in +-- APL_DTYPE_OUT => open, +-- APL_ERROR_PATTERN_OUT => open, +-- APL_SEQNR_OUT => open, +-- APL_GOT_TRM => open, +-- APL_RELEASE_TRM => '1', +-- APL_ERROR_PATTERN_IN => (others => '0') +-- -- Status and control port +-- ); +apl_to_buf_INIT_DATAREADY <= '0'; +apl_to_buf_INIT_DATA <= (others => '0'); +apl_to_buf_INIT_PACKET_NUM <= (others => '0'); +buf_to_apl_REPLY_READ <= '1'; + + +end architecture; \ No newline at end of file diff --git a/trb_net16_endpoint_1_trg_1_api.vhd b/trb_net16_endpoint_1_trg_1_api.vhd new file mode 100644 index 0000000..7a4e47d --- /dev/null +++ b/trb_net16_endpoint_1_trg_1_api.vhd @@ -0,0 +1,797 @@ +-- this is an trigger receiver combined with a passive api + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + +--Entity decalaration for clock generator +entity trb_net16_endpoint_1_trg_1_api is + + generic ( + --api type for data channel + API_TYPE : integer range 0 to 1 := 0; + --Fifo for data channel + DAT_INIT_DEPTH : integer range 0 to 7 := 2; + DAT_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here + DAT_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1; + DAT_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1; + --SBUF_DATA_VERSION : integer range 0 to 1 := 0; + --Fifo for TRG channel + TRG_INIT_DEPTH : integer range 0 to 7 := 0; + TRG_REPLY_DEPTH : integer range 0 to 7 := 0; + TRG_SECURE_MODE : integer range 0 to 1 := 0; + --SBUF_TRG_VERSION : integer range 0 to 1 := 0; + --Multiplexer + MUX_WIDTH : integer range 1 to 5 := 3; + MUX_SECURE_MODE : integer range 0 to 1 := 0; + TRG_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 0; + DAT_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 2; + --General + DATA_WIDTH : integer range 16 to 16 := 16; + NUM_WIDTH : integer range 2 to 2 := 2 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out + MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_READ_IN: in std_logic; -- Media is reading + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_READ_OUT: out std_logic; -- buffer reads a word from media + MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + -- APL Transceiver port + APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in std_logic; -- + APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in std_logic; -- Release sending of the data + APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out + APL_READ_IN: in std_logic; -- Read data word + APL_RUN_OUT: out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + APL_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0); + + -- TRG Receiver port + TRG_GOT_TRIGGER_OUT : out std_logic; + TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + TRG_DTYPE_OUT : out std_logic_vector(3 downto 0); + TRG_SEQNR_OUT : out std_logic_vector(7 downto 0); + TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + TRG_RELEASE_IN : in std_logic; + + -- Status and control port => for debugging + STAT_DAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_DAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_DAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_DAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + STAT_DAT_api_control_signals: out std_logic_vector(31 downto 0); + CTRL_DAT_GEN: in std_logic_vector (31 downto 0); + CTRL_DAT_LOCKED: in std_logic_vector (31 downto 0); + STAT_DAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_DAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); + STAT_TRG_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_TRG_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_TRG_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_TRG_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + STAT_TRG_api_control_signals: out std_logic_vector(31 downto 0); + CTRL_TRG_GEN: in std_logic_vector (31 downto 0); + CTRL_TRG_LOCKED: in std_logic_vector (31 downto 0); + STAT_TRG_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_TRG_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); + STAT_MPLEX: out std_logic_vector(31 downto 0); + MPLEX_CTRL: in std_logic_vector (31 downto 0); + DAT_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + DAT_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); +end entity; + +architecture trb_net16_endpoint_1_trg_1_api_arch of trb_net16_endpoint_1_trg_1_api_endpoint is + + component trb_net16_iobuf is + + generic ( + INIT_DEPTH : integer := 1; + REPLY_DEPTH : integer := 1 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; -- Media is reading + + MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media + MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; -- Media is reading + + MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media + MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + -- Internal direction port + + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_READ_IN: in std_logic; + + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT: out std_logic; + + INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_base_api is + generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active + --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets + FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium + FIFO_TO_APL_DEPTH : integer := 1; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path + -- if set to 0, no buffer is used + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN : in std_logic; -- + APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN : in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out + APL_READ_IN : in std_logic; -- Read data word + -- APL Control port + APL_RUN_OUT : out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_READ_IN : in std_logic; + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_term is + generic ( + FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + SECURE_MODE : integer range 0 to 1 := 0 + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these must be available when hold_trm goes low + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + INT_READ_IN: in std_logic; + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_READ_OUT: out std_logic; + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + APL_GOT_TRM: out std_logic; + APL_RELEASE_TRM: in std_logic; + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr + -- Status and control port + ); + end component; + + component trb_net16_io_multiplexer is + generic ( + DATA_WIDTH : integer := 16; + NUM_WIDTH : integer := 2; + MUX_WIDTH : integer range 1 to 5 := 3; + MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + -- Internal direction port + INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + -- Status and control port + CTRL: in std_logic_vector (31 downto 0); + STAT: out std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_term_buf is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; + MED_INIT_DATAREADY_IN: in std_logic; + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; + MED_REPLY_DATAREADY_IN: in std_logic; + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic + ); + end component; +signal apl_to_buf_DAT_INIT_DATAREADY: std_logic; +signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); +signal apl_to_buf_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); +signal apl_to_buf_DAT_INIT_READ : std_logic; + +signal buf_to_apl_DAT_INIT_DATAREADY: std_logic; +signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); +signal buf_to_apl_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); +signal buf_to_apl_DAT_INIT_READ : std_logic; + +signal apl_to_buf_DAT_REPLY_DATAREADY: std_logic; +signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); +signal apl_to_buf_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); +signal apl_to_buf_DAT_REPLY_READ : std_logic; + +signal buf_to_apl_DAT_REPLY_DATAREADY: std_logic; +signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); +signal buf_to_apl_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); +signal buf_to_apl_DAT_REPLY_READ : std_logic; + +signal apl_to_buf_TRG_INIT_DATAREADY: std_logic; +signal apl_to_buf_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); +signal apl_to_buf_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); +signal apl_to_buf_TRG_INIT_READ : std_logic; + +signal buf_to_apl_TRG_INIT_DATAREADY: std_logic; +signal buf_to_apl_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); +signal buf_to_apl_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); +signal buf_to_apl_TRG_INIT_READ : std_logic; + +signal apl_to_buf_TRG_REPLY_DATAREADY: std_logic; +signal apl_to_buf_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); +signal apl_to_buf_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); +signal apl_to_buf_TRG_REPLY_READ : std_logic; + +signal buf_to_apl_TRG_REPLY_DATAREADY: std_logic; +signal buf_to_apl_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); +signal buf_to_apl_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); +signal buf_to_apl_TRG_REPLY_READ : std_logic; + +-- for the connection to the multiplexer +signal MED_DAT_INIT_DATAREADY_OUT : std_logic; +signal MED_DAT_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); +signal MED_DAT_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); +signal MED_DAT_INIT_READ_IN : std_logic; + +signal MED_DAT_INIT_DATAREADY_IN : std_logic; +signal MED_DAT_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); +signal MED_DAT_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); +signal MED_DAT_INIT_READ_OUT : std_logic; + +signal MED_DAT_REPLY_DATAREADY_OUT : std_logic; +signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); +signal MED_DAT_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); +signal MED_DAT_REPLY_READ_IN : std_logic; + +signal MED_DAT_REPLY_DATAREADY_IN : std_logic; +signal MED_DAT_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); +signal MED_DAT_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); +signal MED_DAT_REPLY_READ_OUT : std_logic; + +signal MED_TRG_INIT_DATAREADY_OUT : std_logic; +signal MED_TRG_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); +signal MED_TRG_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); +signal MED_TRG_INIT_READ_IN : std_logic; + +signal MED_TRG_INIT_DATAREADY_IN : std_logic; +signal MED_TRG_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); +signal MED_TRG_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); +signal MED_TRG_INIT_READ_OUT : std_logic; + +signal MED_TRG_REPLY_DATAREADY_OUT : std_logic; +signal MED_TRG_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); +signal MED_TRG_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); +signal MED_TRG_REPLY_READ_IN : std_logic; + +signal MED_TRG_REPLY_DATAREADY_IN : std_logic; +signal MED_TRG_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); +signal MED_TRG_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); +signal MED_TRG_REPLY_READ_OUT : std_logic; + +signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); +signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); + +signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); +signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0); +signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); +signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); + +begin + + --Connections for data and trigger channel + genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate + gendat: if i = DAT_CHANNEL generate + m_DATAREADY_OUT(i*2) <= MED_DAT_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(i*2+1) <= MED_DAT_REPLY_DATAREADY_OUT; + m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT_REPLY_PACKET_NUM_OUT; + MED_DAT_INIT_READ_IN <= m_READ_IN(i*2); + MED_DAT_REPLY_READ_IN <= m_READ_IN(i*2+1); + MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); + MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); + MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); + MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); + MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); + MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + m_READ_OUT(i*2) <= MED_DAT_INIT_READ_OUT; + m_READ_OUT(i*2+1) <= MED_DAT_REPLY_READ_OUT; + end generate; + gentrg: if i = TRG_CHANNEL generate + m_DATAREADY_OUT(i*2) <= MED_TRG_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(i*2+1) <= MED_TRG_REPLY_DATAREADY_OUT; + m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG_REPLY_PACKET_NUM_OUT; + MED_TRG_INIT_READ_IN <= m_READ_IN(i*2); + MED_TRG_REPLY_READ_IN <= m_READ_IN(i*2+1); + MED_TRG_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); + MED_TRG_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); + MED_TRG_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); + MED_TRG_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); + MED_TRG_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); + MED_TRG_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + m_READ_OUT(i*2) <= MED_TRG_INIT_READ_OUT; + m_READ_OUT(i*2+1) <= MED_TRG_REPLY_READ_OUT; + end generate; + genelse: if i /= DAT_CHANNEL and i /= TRG_CHANNEL generate + termbuf: trb_net16_term_buf + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), + MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), + MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), + MED_INIT_READ_OUT => m_READ_OUT(i*2), + + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), + MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), + MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), + MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) + ); + end generate; + end generate; + + gen_actapi: if API_TYPE = 1 generate + DAT_ACTIVE_API: trb_net16_base_api + generic map ( + API_TYPE => 1, + FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH, + FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH, + FIFO_TERM_BUFFER_DEPTH => 0 + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN, + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, + APL_WRITE_IN => APL_WRITE_IN, + APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, + APL_SEND_IN => APL_SEND_IN, + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT, + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, + APL_TYP_OUT => APL_TYP_OUT, + APL_DATAREADY_OUT => APL_DATAREADY_OUT, + APL_READ_IN => APL_READ_IN, + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT, + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT, + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY, + INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA, + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM, + INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ, + INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY, + INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA, + INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM, + INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ, + INT_SLAVE_HEADER_IN => '0', + INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY, + INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA, + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM, + INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ, + INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY, + INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA, + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM, + INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ, + -- Status and control port + STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int, + STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl + ); + end generate; + + gen_pasapi: if API_TYPE = 0 generate + DAT_PASSIVE_API: trb_net16_base_api + generic map ( + API_TYPE => 0, + FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH, + FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH, + FIFO_TERM_BUFFER_DEPTH => 0 + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN, + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, + APL_WRITE_IN => APL_WRITE_IN, + APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, + APL_SEND_IN => APL_SEND_IN, + APL_TARGET_ADDRESS_IN => (others => '0'), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT, + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, + APL_TYP_OUT => APL_TYP_OUT, + APL_DATAREADY_OUT => APL_DATAREADY_OUT, + APL_READ_IN => APL_READ_IN, + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT, + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT, + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY, + INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA, + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM, + INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ, + INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY, + INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA, + INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM, + INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ, + INT_SLAVE_HEADER_IN => '0', + INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY, + INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA, + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM, + INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ, + INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY, + INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA, + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM, + INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ, + -- Status and control port + STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int, + STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl + ); + end generate; + +STAT_DAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); +STAT_DAT_api_control_signals(3) <= APL_WRITE_IN; +STAT_DAT_api_control_signals(4) <= APL_SEND_IN; +STAT_DAT_api_control_signals(7 downto 5) <= (others => '0'); +STAT_DAT_api_control_signals(10 downto 8) <= apl_to_buf_DAT_INIT_DATA(2 downto 0); +STAT_DAT_api_control_signals(11) <= apl_to_buf_DAT_INIT_DATAREADY; +STAT_DAT_api_control_signals(12) <= apl_to_buf_DAT_INIT_READ; +STAT_DAT_api_control_signals(31 downto 13) <= (others => '0'); + + + +DAT_IOBUF: trb_net16_iobuf + generic map( + INIT_DEPTH => DAT_INIT_DEPTH, + REPLY_DEPTH => DAT_REPLY_DEPTH + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_DAT_INIT_DATAREADY_OUT, + MED_INIT_DATA_OUT => MED_DAT_INIT_DATA_OUT, + MED_INIT_PACKET_NUM_OUT => MED_DAT_INIT_PACKET_NUM_OUT, + MED_INIT_READ_IN => MED_DAT_INIT_READ_IN, + MED_INIT_DATAREADY_IN => MED_DAT_INIT_DATAREADY_IN, + MED_INIT_DATA_IN => MED_DAT_INIT_DATA_IN, + MED_INIT_PACKET_NUM_IN => MED_DAT_INIT_PACKET_NUM_IN, + MED_INIT_READ_OUT => MED_DAT_INIT_READ_OUT, + MED_INIT_ERROR_IN => (others => '0'), + MED_REPLY_DATAREADY_OUT => MED_DAT_REPLY_DATAREADY_OUT, + MED_REPLY_DATA_OUT => MED_DAT_REPLY_DATA_OUT, + MED_REPLY_PACKET_NUM_OUT=> MED_DAT_REPLY_PACKET_NUM_OUT, + MED_REPLY_READ_IN => MED_DAT_REPLY_READ_IN, + MED_REPLY_DATAREADY_IN => MED_DAT_REPLY_DATAREADY_IN, + MED_REPLY_DATA_IN => MED_DAT_REPLY_DATA_IN, + MED_REPLY_PACKET_NUM_IN => MED_DAT_REPLY_PACKET_NUM_IN, + MED_REPLY_READ_OUT => MED_DAT_REPLY_READ_OUT, + MED_REPLY_ERROR_IN => (others => '0'), + -- Internal direction port + INT_INIT_DATAREADY_OUT => buf_to_apl_DAT_INIT_DATAREADY, + INT_INIT_DATA_OUT => buf_to_apl_DAT_INIT_DATA, + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT_INIT_PACKET_NUM, + INT_INIT_READ_IN => buf_to_apl_DAT_INIT_READ, + INT_INIT_DATAREADY_IN => apl_to_buf_DAT_INIT_DATAREADY, + INT_INIT_DATA_IN => apl_to_buf_DAT_INIT_DATA, + INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT_INIT_PACKET_NUM, + INT_INIT_READ_OUT => apl_to_buf_DAT_INIT_READ, + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT_REPLY_DATAREADY, + INT_REPLY_DATA_OUT => buf_to_apl_DAT_REPLY_DATA, + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT_REPLY_PACKET_NUM, + INT_REPLY_READ_IN => buf_to_apl_DAT_REPLY_READ, + INT_REPLY_DATAREADY_IN => apl_to_buf_DAT_REPLY_DATAREADY, + INT_REPLY_DATA_IN => apl_to_buf_DAT_REPLY_DATA, + INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT_REPLY_PACKET_NUM, + INT_REPLY_READ_OUT => apl_to_buf_DAT_REPLY_READ, + -- Status and control port + STAT_GEN => STAT_DAT_GEN, + STAT_LOCKED => STAT_DAT_LOCKED, + STAT_INIT_BUFFER => STAT_DAT_INIT_BUFFER, + STAT_REPLY_BUFFER => STAT_DAT_REPLY_BUFFER, + CTRL_GEN => CTRL_DAT_GEN, + CTRL_LOCKED => CTRL_DAT_LOCKED, + STAT_CTRL_INIT_BUFFER => STAT_DAT_CTRL_INIT_BUFFER, + STAT_CTRL_REPLY_BUFFER => STAT_DAT_CTRL_REPLY_BUFFER + ); + + TRG_IOBUF: trb_net16_iobuf + generic map( + INIT_DEPTH => TRG_INIT_DEPTH, + REPLY_DEPTH => TRG_REPLY_DEPTH + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_TRG_INIT_DATAREADY_OUT, + MED_INIT_DATA_OUT => MED_TRG_INIT_DATA_OUT, + MED_INIT_PACKET_NUM_OUT => MED_TRG_INIT_PACKET_NUM_OUT, + MED_INIT_READ_IN => MED_TRG_INIT_READ_IN, + MED_INIT_DATAREADY_IN => MED_TRG_INIT_DATAREADY_IN, + MED_INIT_DATA_IN => MED_TRG_INIT_DATA_IN, + MED_INIT_PACKET_NUM_IN => MED_TRG_INIT_PACKET_NUM_IN, + MED_INIT_READ_OUT => MED_TRG_INIT_READ_OUT, + MED_INIT_ERROR_IN => (others => '0'), + MED_REPLY_DATAREADY_OUT => MED_TRG_REPLY_DATAREADY_OUT, + MED_REPLY_DATA_OUT => MED_TRG_REPLY_DATA_OUT, + MED_REPLY_PACKET_NUM_OUT=> MED_TRG_REPLY_PACKET_NUM_OUT, + MED_REPLY_READ_IN => MED_TRG_REPLY_READ_IN, + MED_REPLY_DATAREADY_IN => MED_TRG_REPLY_DATAREADY_IN, + MED_REPLY_DATA_IN => MED_TRG_REPLY_DATA_IN, + MED_REPLY_PACKET_NUM_IN => MED_TRG_REPLY_PACKET_NUM_IN, + MED_REPLY_READ_OUT => MED_TRG_REPLY_READ_OUT, + MED_REPLY_ERROR_IN => (others => '0'), + -- Internal direction port + INT_INIT_DATAREADY_OUT => buf_to_apl_TRG_INIT_DATAREADY, + INT_INIT_DATA_OUT => buf_to_apl_TRG_INIT_DATA, + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG_INIT_PACKET_NUM, + INT_INIT_READ_IN => buf_to_apl_TRG_INIT_READ, + INT_INIT_DATAREADY_IN => apl_to_buf_TRG_INIT_DATAREADY, + INT_INIT_DATA_IN => apl_to_buf_TRG_INIT_DATA, + INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG_INIT_PACKET_NUM, + INT_INIT_READ_OUT => apl_to_buf_TRG_INIT_READ, + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG_REPLY_DATAREADY, + INT_REPLY_DATA_OUT => buf_to_apl_TRG_REPLY_DATA, + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG_REPLY_PACKET_NUM, + INT_REPLY_READ_IN => buf_to_apl_TRG_REPLY_READ, + INT_REPLY_DATAREADY_IN => apl_to_buf_TRG_REPLY_DATAREADY, + INT_REPLY_DATA_IN => apl_to_buf_TRG_REPLY_DATA, + INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG_REPLY_PACKET_NUM, + INT_REPLY_READ_OUT => apl_to_buf_TRG_REPLY_READ, + -- Status and control port + STAT_GEN => STAT_TRG_GEN, + STAT_LOCKED => STAT_TRG_LOCKED, + STAT_INIT_BUFFER => STAT_TRG_INIT_BUFFER, + STAT_REPLY_BUFFER => STAT_TRG_REPLY_BUFFER, + CTRL_GEN => CTRL_TRG_GEN, + CTRL_LOCKED => CTRL_TRG_LOCKED, + STAT_CTRL_INIT_BUFFER => STAT_TRG_CTRL_INIT_BUFFER, + STAT_CTRL_REPLY_BUFFER => STAT_TRG_CTRL_REPLY_BUFFER + ); + + MPLEX: trb_net16_io_multiplexer + generic map ( + DATA_WIDTH => DATA_WIDTH, + NUM_WIDTH => NUM_WIDTH, + MUX_WIDTH => MUX_WIDTH, + MUX_SECURE_MODE => MUX_SECURE_MODE + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => m_DATAREADY_IN, + INT_DATA_OUT =>m_DATA_IN, + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, + INT_READ_IN =>m_READ_OUT, + INT_DATAREADY_IN =>m_DATAREADY_OUT, + INT_DATA_IN =>m_DATA_OUT, + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, + INT_READ_OUT =>m_READ_IN, + CTRL => MPLEX_CTRL + ); + + TRG_INIT : trb_net16_term + generic map ( + FIFO_TERM_BUFFER_DEPTH => 0, + SECURE_MODE => TRG_SECURE_MODE + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + INT_DATAREADY_OUT => apl_to_buf_TRG_REPLY_DATAREADY, + INT_DATA_OUT => apl_to_buf_TRG_REPLY_DATA, + INT_PACKET_NUM_OUT => apl_to_buf_TRG_REPLY_PACKET_NUM, + INT_READ_IN => apl_to_buf_TRG_REPLY_READ, + INT_DATAREADY_IN => buf_to_apl_TRG_INIT_DATAREADY, + INT_DATA_IN => buf_to_apl_TRG_INIT_DATA, + INT_PACKET_NUM_IN => buf_to_apl_TRG_INIT_PACKET_NUM, + INT_READ_OUT => buf_to_apl_TRG_INIT_READ, + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT => TRG_DTYPE_OUT, + APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT, + APL_SEQNR_OUT => TRG_SEQNR_OUT, + APL_GOT_TRM => TRG_GOT_TRIGGER_OUT, + APL_RELEASE_TRM => TRG_RELEASE_IN, + APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN + -- Status and control port + ); + + + +apl_to_buf_TRG_INIT_DATAREADY <= '0'; +apl_to_buf_TRG_INIT_DATA <= (others => '0'); +apl_to_buf_TRG_INIT_PACKET_NUM <= (others => '0'); +buf_to_apl_TRG_REPLY_READ <= '1'; +end architecture; diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd new file mode 100644 index 0000000..b83ebd0 --- /dev/null +++ b/trb_net16_hub_base.vhd @@ -0,0 +1,450 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + + +entity trb_net16_hub_base is + generic{ + --media interfaces + MII_NUMBER : integer range 2 to 16 := 2; + MII_INIT_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; + MII_REPLY_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; + -- settings for apis + API_NUMBER : integer range 0 to 16 := 1; + API_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"3"; + --channel, each api is connected to + API_TYPE : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + API_INIT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + API_REPLY_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + API_FIFO_TO_INT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + API_FIFO_TO_APL_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + --trigger reading interfaces + TRG_NUMBER : integer range 0 to 16 := 2; + TRG_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"10"; + --general settings + MUX_SECURE_MODE : integer range 0 to 1 := 0; + MUX_WIDTH : integer range 1 to 5 := 3; + MUX_CTRL_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3; + DATA_WIDTH : integer range 16 to 16 := 16; + NUM_WIDTH : integer range 2 to 2 := 2 + } + port { + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --Media interfacces + --each port is one bit bigger than actually necessary to avoid error messages + MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0); + MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); + MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); + MED_READ_IN : in std_logic_vector (MII_NUMBER downto 0); + MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER downto 0); + MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); + MED_READ_OUT : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media + MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3 downto 0); + --API: interfaces + APL_DATA_IN : in std_logic_vector (APL_NUMBER*DATA_WIDTH downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0); + APL_WRITE_IN : in std_logic_vector (APL_NUMBER downto 0); + APL_FIFO_FULL_OUT : out std_logic_vector (APL_NUMBER downto 0); + APL_SHORT_TRANSFER_IN : in std_logic_vector (APL_NUMBER downto 0); + APL_DTYPE_IN : in std_logic_vector (APL_NUMBER*4 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (APL_NUMBER*32 downto 0); + APL_SEND_IN : in std_logic_vector (APL_NUMBER downto 0); + APL_TARGET_ADDRESS_IN : in std_logic_vector (APL_NUMBER*16 downto 0); + APL_DATA_OUT : out std_logic_vector (APL_NUMBER*16 downto 0); + APL_PACKET_NUM_OUT: out std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0); + APL_TYP_OUT : out std_logic_vector (APL_NUMBER*3 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (APL_NUMBER downto 0); + APL_READ_IN : in std_logic_vector (APL_NUMBER downto 0); + APL_RUN_OUT : out std_logic_vector (APL_NUMBER downto 0); + APL_MY_ADDRESS_IN : in std_logic_vector (APL_NUMBRT*16 downto 0); + APL_SEQNR_OUT : out std_logic_vector (APL_NUMBER*8 downto 0); + --TRG interfaces + TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0); + TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0); + TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0); + TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0); + TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0); + TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0); + --Status ports (for debugging) + HUB_CHANNEL_STAT : out std_logic_vector (2**(MUX_WIDTH-1)*16 downto 0); + HUB_GEN_STAT : out std_logic_vector (31 downto 0); + MPLEX_CTRL : out std_logic_vector (MII_NUMBER*32-1 downto 0); + + } +end entity; + +architecture trb_net16_hub_base_arch of trb_net16_hub_base is + + signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); + signal m_DATA_OUT : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0); + signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0); + signal m_READ_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); + signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); + signal m_DATA_IN : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0); + signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0); + signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); + + signal hub_to_buf_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal hub_to_buf_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); + signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); + signal hub_to_buf_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + + signal buf_to_hub_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal buf_to_hub_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); + signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); + signal buf_to_hub_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + + signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal hub_to_buf_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); + signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); + signal hub_to_buf_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + + signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal buf_to_hub_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); + signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); + signal buf_to_hub_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + + component trb_net16_base_hub_logic is + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to 16 := 2; + INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; + REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; + --general settings + DATA_WIDTH : integer range 16 to 16 := 16; + NUM_WIDTH : integer range 2 to 2 := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER downto 0); + INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER downto 0); + INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER downto 0); + REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER downto 0); + REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER downto 0); + REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER downto 0); + STAT_CHANNEL : out std_logic_vector (15 downto 0); + STAT_GEN : out std_logic_vector (31 downto 0); + CTRL_CHANNEL : in std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0) + ); +end component; + + + component trb_net16_io_multiplexer is + generic ( + DATA_WIDTH : integer := 16; + NUM_WIDTH : integer := 2; + MUX_WIDTH : integer range 1 to 5 := 3; + MUX_SECURE_MODE : integer range 0 to 1 := 0 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + -- Internal direction port + INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + -- Status and control port + CTRL: in std_logic_vector (31 downto 0); + STAT: out std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_iobuf is + generic ( + INIT_DEPTH : integer := 1; + REPLY_DEPTH : integer := 1 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; -- Media is reading + MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media + MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; -- Media is reading + MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media + MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + -- Internal direction port + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_READ_IN: in std_logic; + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT: out std_logic; + INT_REPLY_HEADER_IN: in std_logic; + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN: in std_logic; + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) + ); + end component; + + + component trb_net16_base_api is + generic ( + API_TYPE : integer := API_TYPE; + FIFO_TO_INT_DEPTH : integer := 1; + FIFO_TO_APL_DEPTH : integer := 1; + FIFO_TERM_BUFFER_DEPTH : integer := 0); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN : in std_logic; -- + APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN : in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out + APL_READ_IN : in std_logic; -- Read data word + -- APL Control port + APL_RUN_OUT : out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + -- Internal direction port + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_READ_IN : in std_logic; + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + + +begin + +--generate multiplexers + gen_muxes: for i in 0 to MII_NUMBER-1 generate + MPLEX: trb_net16_io_multiplexer + generic map ( + DATA_WIDTH => DATA_WIDTH, + NUM_WIDTH => NUM_WIDTH, + MUX_WIDTH => MUX_WIDTH, + MUX_SECURE_MODE => MUX_SECURE_MODE + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN(i*2+1 downto i*2), + MED_DATA_IN => MED_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), + MED_READ_OUT => MED_READ_OUT(i*2+1 downto i*2), + MED_DATAREADY_OUT => MED_DATAREADY_OUT(i*2+1 downto i*2), + MED_DATA_OUT => MED_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), + MED_READ_IN => MED_READ_IN(i*2+1 downto i*2), + INT_DATAREADY_OUT => m_DATAREADY_IN(i*2+1 downto i*2), + INT_DATA_OUT => m_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), + INT_READ_IN => m_READ_OUT(i*2+1 downto i*2), + INT_DATAREADY_IN => m_DATAREADY_OUT(i*2+1 downto i*2), + INT_DATA_IN => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), + INT_READ_OUT => m_READ_IN(i*2+1 downto i*2), + CTRL => MPLEX_CTRL((i+1)*32-1) downto i*32) + ); + end generate; + +--generate IOBufs for MII + gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate + IOBUF: trb_net16_iobuf + generic map ( + INIT_DEPTH => to_integer(MII_INIT_DEPTH((i+1)*4-1 downto i)), + REPLY_DEPTH => to_integer(MII_REPLY_DEPTH((i+1)*4-1 downto i)) + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), + MED_INIT_READ_IN => m_READ_IN(i*2), + + MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), + MED_INIT_DATA_IN => m_DATA_�N((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), + MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), + MED_INIT_READ_OUT => m_READ_OUT(i*2), + MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), + + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + + MED_REPLY_DATAREADY_IN => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_IN => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2), + MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2), + MED_REPLY_READ_OUT => m_READ_IN(i*2+1), + MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_INIT_READ_IN => buf_to_hub_INIT_READ(i), + + INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i), + + INT_REPLY_HEADER_IN => buf_to_hub_REPLY_SEND_HEADER(i), + INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i), + + INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i), + + -- Status and control port + STAT_GEN => IOBUF_STAT_GEN((i+1)*32 downto i*32), + STAT_LOCKED => IOBUF_STAT_LOCKED((i+1)*32 downto i*32), + STAT_INIT_BUFFER => IOBUF_buf_STAT_INIT_BUFFER((i+1)*32 downto i*32), + STAT_REPLY_BUFFER => IOBUF_STAT_REPLY_BUFFER((i+1)*32 downto i*32), + CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32 downto i*32), + CTRL_LOCKED => IOBUF_CTRL_LOCKED((i+1)*32 downto i*32), + STAT_CTRL_INIT_BUFFER => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32 downto i*32), + STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32 downto i*32) + ); + end generate; + + gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate + HUBLOGIC : trb_net16_base_hub_logic + generic map{ + --media interfaces + POINT_NUMBER => MII_NUMBER, + INIT_DEPTH => MII_INIT_DEPTH((i+1)*4 downto i*4), + REPLY_DEPTH => MII_REPLY_DEPTH((i+1)*4 downto i*4), + --general settings + DATA_WIDTH => DATA_WIDTH, + NUM_WIDTH => NUM_WIDTH + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + INIT_DATAREADY_IN => buf_to_hub_INIT_DATAREADY(i), + INIT_DATA_IN => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INIT_PACKET_NUM_IN => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INIT_READ_OUT => buf_to_hub_INIT_READ(i), + INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), + INIT_DATA_OUT => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INIT_PACKET_NUM_OUT => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INIT_READ_IN => hub_to_buf_INIT_READ(i), + REPLY_HEADER_OUT => hub_to_buf_REPLY_HEADER_OUT(i), + REPLY_DATAREADY_IN => buf_to_hub_REPLY_DATAREADY(i), + REPLY_DATA_IN => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + REPLY_PACKET_NUM_IN => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + REPLY_READ_OUT => buf_to_hub_REPLY_READ(i), + REPLY_DATAREADY_OUT => hub_to_buf_REPLY_DATAREADY(i), + REPLY_DATA_OUT => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + REPLY_READ_IN => hub_to_buf_REPLY_READ(i), + STAT_INTERFACE => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32), + STAT_GEN => HUB_STAT_GEN((i+1)*32-1 downto i*32), + CTRL_INTERFACE => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32), + CTRL_GEN => HUB_CTRL_GEN((i+1)*32-1 downto i*32) + ) + end generate; + +end architecture; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd new file mode 100644 index 0000000..9211b70 --- /dev/null +++ b/trb_net16_hub_logic.vhd @@ -0,0 +1,107 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + + +entity trb_net16_hub_logic is + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to 16 := 2; + INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; + REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; + --general settings + DATA_WIDTH : integer range 16 to 16 := 16; + NUM_WIDTH : integer range 2 to 2 := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + --Internal interfaccs to IOBufs + INIT_DATAREADY_IN : in std_logic_vector (PONUMBER downto 0); + INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*PONUMBER downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*PONUMBER downto 0); + INIT_READ_OUT : out std_logic_vector (PONUMBER downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (PONUMBER downto 0); + INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0); + INIT_READ_IN : in std_logic_vector (PONUMBER downto 0); + REPLY_HEADER_OUT : out std_logic_vector (PONUMBER downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (PONUMBER downto 0); + REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*PONUMBER downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*PONUMBER downto 0); + REPLY_READ_OUT : out std_logic_vector (PONUMBER downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (PONUMBER downto 0); + REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0); + REPLY_READ_IN : in std_logic_vector (PONUMBER downto 0); + --Status ports (for debugging) + STAT_CHANNEL : out std_logic_vector (15 downto 0); + STAT_GEN : out std_logic_vector (31 downto 0); + CTRL_CHANNEL : in std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is +begin +--Datapool for Init-Channel + INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0); + INIT_POOL_READ <= + and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_pool_has_read(POINT_NUMBER-1 downto 0)); + + gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate + process(INIT_DATA_IN) + variable VAR_INIT_POOL_DATA : std_logic; + begin + VAR_INIT_POOL_DATA := 0; + gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop + VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i); + end loop; + INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA; + end process; + end generate; + +--Data for obuf output + gen_init_dataready_out: for i in 0 to POINT_NUMBER-1 generate + INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_pool_has_read(i); + end generate; + + gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate + INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA; + end generate; + + gen_init_read_in + + --DATAREADY for each OBUF is dataready from all ibufs and not already have been reading this word + -- gen_init_datapool_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate + -- gen_init_datapool_m: for MEDIA in 0 to MII_NUMBER-1 generate + -- hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) <= + -- or_all(buf_to_hub_DATAREADY((CHANNEL+1)*MII_NUMBER-1 downto CHANNEL*MII_NUMBER) + -- and not buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA); + -- hub_to_buf_INIT_DATA((CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH+1)-1 downto CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH)) <= + -- or_all( + -- end generate; + -- end generate; + + -- gen_init_has_read_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate + -- gen_init_has_read_m: for MEDIA in 0 to MII_NUMBER-1 generate + -- process(CLK) + -- begin + -- if rising_edge(CLK) then + -- if RESET = '1' or buf_to_hub_INIT_CHANNEL_READ(CHANNEL) = '1' then + -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '0'; + -- else + -- if hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) = '1' + -- and hub_to_buf_INIT_READ(CHANNEL*MII_NUMBER+MEDIA) = '1' then + -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '1'; + -- end if; + -- end if; + -- end if; + -- end process; + -- end generate; + -- end generate; +end architecture; \ No newline at end of file -- 2.43.0