From e419940822cd6e188c588405abaf22cff1399258 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 18 Sep 2009 15:39:27 +0000 Subject: [PATCH] attilio: header fifo --- design/fifo_512depth_72width_reg_out.vhd | 2060 ++++++++++++++++++++++ 1 file changed, 2060 insertions(+) create mode 100644 design/fifo_512depth_72width_reg_out.vhd diff --git a/design/fifo_512depth_72width_reg_out.vhd b/design/fifo_512depth_72width_reg_out.vhd new file mode 100644 index 0000000..8ff05ee --- /dev/null +++ b/design/fifo_512depth_72width_reg_out.vhd @@ -0,0 +1,2060 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 4.6 +--/storage120/lattice/isplever7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 72 -depth 512 -regout -no_enable -pe 0 -pf 0 -fill -e + +-- Fri Sep 18 16:09:46 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_512depth_72width_reg_out is + port ( + Data: in std_logic_vector(71 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmEmptyThresh: in std_logic_vector(8 downto 0); + AmFullThresh: in std_logic_vector(8 downto 0); + Q: out std_logic_vector(71 downto 0); + WCNT: out std_logic_vector(9 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_512depth_72width_reg_out; + +architecture Structure of fifo_512depth_72width_reg_out is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal rcnt_reg_8_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal rptr_9: std_logic; + signal ffidata_0: std_logic; + signal ffidata_1: std_logic; + signal ffidata_2: std_logic; + signal ffidata_3: std_logic; + signal ffidata_4: std_logic; + signal ffidata_5: std_logic; + signal ffidata_6: std_logic; + signal ffidata_7: std_logic; + signal ffidata_8: std_logic; + signal ffidata_9: std_logic; + signal ffidata_10: std_logic; + signal ffidata_11: std_logic; + signal ffidata_12: std_logic; + signal ffidata_13: std_logic; + signal ffidata_14: std_logic; + signal ffidata_15: std_logic; + signal ffidata_16: std_logic; + signal ffidata_17: std_logic; + signal ffidata_18: std_logic; + signal ffidata_19: std_logic; + signal ffidata_20: std_logic; + signal ffidata_21: std_logic; + signal ffidata_22: std_logic; + signal ffidata_23: std_logic; + signal ffidata_24: std_logic; + signal ffidata_25: std_logic; + signal ffidata_26: std_logic; + signal ffidata_27: std_logic; + signal ffidata_28: std_logic; + signal ffidata_29: std_logic; + signal ffidata_30: std_logic; + signal ffidata_31: std_logic; + signal ffidata_32: std_logic; + signal ffidata_33: std_logic; + signal ffidata_34: std_logic; + signal ffidata_35: std_logic; + signal ffidata_36: std_logic; + signal ffidata_37: std_logic; + signal ffidata_38: std_logic; + signal ffidata_39: std_logic; + signal ffidata_40: std_logic; + signal ffidata_41: std_logic; + signal ffidata_42: std_logic; + signal ffidata_43: std_logic; + signal ffidata_44: std_logic; + signal ffidata_45: std_logic; + signal ffidata_46: std_logic; + signal ffidata_47: std_logic; + signal ffidata_48: std_logic; + signal ffidata_49: std_logic; + signal ffidata_50: std_logic; + signal ffidata_51: std_logic; + signal ffidata_52: std_logic; + signal ffidata_53: std_logic; + signal ffidata_54: std_logic; + signal ffidata_55: std_logic; + signal ffidata_56: std_logic; + signal ffidata_57: std_logic; + signal ffidata_58: std_logic; + signal ffidata_59: std_logic; + signal ffidata_60: std_logic; + signal ffidata_61: std_logic; + signal ffidata_62: std_logic; + signal ffidata_63: std_logic; + signal ffidata_64: std_logic; + signal ffidata_65: std_logic; + signal ffidata_66: std_logic; + signal ffidata_67: std_logic; + signal ffidata_68: std_logic; + signal ffidata_69: std_logic; + signal ffidata_70: std_logic; + signal ffidata_71: std_logic; + signal rcnt_reg_9: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co4: std_logic; + signal co3: std_logic; + signal cmp_ci: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4_1: std_logic; + signal wcount_9: std_logic; + signal co3_3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_2: std_logic; + signal rcount_9: std_logic; + signal co3_4: std_logic; + signal rcnt_sub_0: std_logic; + signal r_nw_inv_inv: std_logic; + signal rcount_0: std_logic; + signal r_nw_inv: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_5: std_logic; + signal rcount_1: std_logic; + signal rcount_2: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_5: std_logic; + signal rcount_3: std_logic; + signal rcount_4: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_5: std_logic; + signal rcount_5: std_logic; + signal rcount_6: std_logic; + signal rcnt_sub_7: std_logic; + signal rcnt_sub_8: std_logic; + signal co3_5: std_logic; + signal rcount_7: std_logic; + signal rcount_8: std_logic; + signal rcnt_sub_9: std_logic; + signal co4_3: std_logic; + signal rcnt_sub_msb: std_logic; + signal rden_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_6: std_logic; + signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; + signal co3_6: std_logic; + signal rcnt_reg_8: std_logic; + signal ae_set_clrsig: std_logic; + signal ae_set_setsig: std_logic; + signal ae_set_d: std_logic; + signal ae_set_d_c: std_logic; + signal wcnt_sub_0: std_logic; + signal cnt_con_inv: std_logic; + signal rptr_0: std_logic; + signal cnt_con: std_logic; + signal wcount_0: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal co0_7: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal wcount_1: std_logic; + signal wcount_2: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal co1_7: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal wcount_3: std_logic; + signal wcount_4: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal co2_7: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal wcount_5: std_logic; + signal wcount_6: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal co3_7: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal wcount_7: std_logic; + signal wcount_8: std_logic; + signal wcnt_sub_9: std_logic; + signal co4_4: std_logic; + signal wcnt_sub_msb: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_8: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_8: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_8: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_8: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KB + -- synopsys translate_off + generic (CSDECODE_R : in std_logic_vector(2 downto 0); + CSDECODE_W : in std_logic_vector(2 downto 0); + GSR : in String; RESETMODE : in String; + REGMODE : in String; DATA_WIDTH_R : in Integer; + DATA_WIDTH_W : in Integer); + -- synopsys translate_on + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_R : string; + attribute CSDECODE_W : string; + attribute RESETMODE : string; + attribute REGMODE : string; + attribute DATA_WIDTH_R : string; + attribute DATA_WIDTH_W : string; + attribute GSR : string; + attribute initval of LUT4_1 : label is "0x3232"; + attribute initval of LUT4_0 : label is "0x3232"; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512depth_72width_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute CSDECODE_R of pdp_ram_0_0_1 : label is "0b000"; + attribute CSDECODE_W of pdp_ram_0_0_1 : label is "0b001"; + attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; + attribute REGMODE of pdp_ram_0_0_1 : label is "NOREG"; + attribute DATA_WIDTH_R of pdp_ram_0_0_1 : label is "36"; + attribute DATA_WIDTH_W of pdp_ram_0_0_1 : label is "36"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512depth_72width_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute CSDECODE_R of pdp_ram_0_1_0 : label is "0b000"; + attribute CSDECODE_W of pdp_ram_0_1_0 : label is "0b001"; + attribute GSR of pdp_ram_0_1_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC"; + attribute REGMODE of pdp_ram_0_1_0 : label is "NOREG"; + attribute DATA_WIDTH_R of pdp_ram_0_1_0 : label is "36"; + attribute DATA_WIDTH_W of pdp_ram_0_1_0 : label is "36"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t8: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t7: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t6: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t5: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t4: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>r_nw, Z=>r_nw_inv); + + XOR2_t3: XOR2 + port map (A=>wcount_9, B=>rcount_9, Z=>rcnt_sub_msb); + + INV_2: INV + port map (A=>r_nw_inv, Z=>r_nw_inv_inv); + + INV_1: INV + port map (A=>rcnt_reg_8, Z=>rcnt_reg_8_inv); + + AND2_t2: AND2 + port map (A=>rcnt_reg_9, B=>rcnt_reg_8_inv, Z=>ae_set_clrsig); + + AND2_t1: AND2 + port map (A=>rcnt_reg_9, B=>rcnt_reg_8, Z=>ae_set_setsig); + + XOR2_t0: XOR2 + port map (A=>wcount_9, B=>rptr_9, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_1: PDPW16KB + -- synopsys translate_off + generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, + ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>Clock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>ffidata_18, DO1=>ffidata_19, + DO2=>ffidata_20, DO3=>ffidata_21, DO4=>ffidata_22, + DO5=>ffidata_23, DO6=>ffidata_24, DO7=>ffidata_25, + DO8=>ffidata_26, DO9=>ffidata_27, DO10=>ffidata_28, + DO11=>ffidata_29, DO12=>ffidata_30, DO13=>ffidata_31, + DO14=>ffidata_32, DO15=>ffidata_33, DO16=>ffidata_34, + DO17=>ffidata_35, DO18=>ffidata_0, DO19=>ffidata_1, + DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4, + DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7, + DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10, + DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13, + DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16, + DO35=>ffidata_17); + + pdp_ram_0_1_0: PDPW16KB + -- synopsys translate_off + generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), + DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), + DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), + DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), + DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, + ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, + ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, + ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, + ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, + CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_54, + DO1=>ffidata_55, DO2=>ffidata_56, DO3=>ffidata_57, + DO4=>ffidata_58, DO5=>ffidata_59, DO6=>ffidata_60, + DO7=>ffidata_61, DO8=>ffidata_62, DO9=>ffidata_63, + DO10=>ffidata_64, DO11=>ffidata_65, DO12=>ffidata_66, + DO13=>ffidata_67, DO14=>ffidata_68, DO15=>ffidata_69, + DO16=>ffidata_70, DO17=>ffidata_71, DO18=>ffidata_36, + DO19=>ffidata_37, DO20=>ffidata_38, DO21=>ffidata_39, + DO22=>ffidata_40, DO23=>ffidata_41, DO24=>ffidata_42, + DO25=>ffidata_43, DO26=>ffidata_44, DO27=>ffidata_45, + DO28=>ffidata_46, DO29=>ffidata_47, DO30=>ffidata_48, + DO31=>ffidata_49, DO32=>ffidata_50, DO33=>ffidata_51, + DO34=>ffidata_52, DO35=>ffidata_53); + + FF_145: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_144: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_143: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_142: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_141: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_140: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_139: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_138: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_137: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_136: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_135: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_134: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_133: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_132: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_131: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_130: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_129: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_128: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_127: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_126: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_125: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_124: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_123: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_122: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_121: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_0, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_1, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_2, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_3, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_4, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_5, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_6, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_7, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_8, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_9, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(9)); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_10, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(10)); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_11, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(11)); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_12, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(12)); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_13, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(13)); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_14, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(14)); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_15, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(15)); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_16, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(16)); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_17, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(17)); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_18, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(18)); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_19, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(19)); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_20, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(20)); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_21, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(21)); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_22, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(22)); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_23, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(23)); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_24, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(24)); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_25, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(25)); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_26, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(26)); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_27, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(27)); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_28, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(28)); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_29, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(29)); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_30, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(30)); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_31, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(31)); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_32, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(32)); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_33, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(33)); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_34, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(34)); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_35, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(35)); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_36, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(36)); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_37, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(37)); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_38, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(38)); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_39, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(39)); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_40, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(40)); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_41, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(41)); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_42, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(42)); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_43, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(43)); + + FF_49: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_44, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(44)); + + FF_48: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_45, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(45)); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_46, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(46)); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_47, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(47)); + + FF_45: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_48, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(48)); + + FF_44: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_49, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(49)); + + FF_43: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_50, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(50)); + + FF_42: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_51, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(51)); + + FF_41: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_52, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(52)); + + FF_40: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_53, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(53)); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_54, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(54)); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_55, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(55)); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_56, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(56)); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_57, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(57)); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_58, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(58)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_59, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(59)); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_60, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(60)); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_61, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(61)); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_62, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(62)); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_63, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(63)); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_64, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(64)); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_65, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(65)); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_66, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(66)); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_67, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(67)); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_68, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(68)); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_69, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(69)); + + FF_23: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_70, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(70)); + + FF_22: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_71, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(71)); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_1, CK=>Clock, CD=>Reset, Q=>rcnt_reg_1); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_2, CK=>Clock, CD=>Reset, Q=>rcnt_reg_2); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_3, CK=>Clock, CD=>Reset, Q=>rcnt_reg_3); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_4, CK=>Clock, CD=>Reset, Q=>rcnt_reg_4); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_5, CK=>Clock, CD=>Reset, Q=>rcnt_reg_5); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_6, CK=>Clock, CD=>Reset, Q=>rcnt_reg_6); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_7, CK=>Clock, CD=>Reset, Q=>rcnt_reg_7); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_8, CK=>Clock, CD=>Reset, Q=>rcnt_reg_8); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_9, CK=>Clock, CD=>Reset, Q=>rcnt_reg_9); + + FF_11: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ae_set_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_1: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv, + CI=>co3_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1, + NC0=>iwcount_8, NC1=>iwcount_9); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2, + NC0=>ircount_8, NC1=>ircount_9); + + rcnt_0: FSUB2B + port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv, + B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2, + BI=>co0_5, BOUT=>co1_5, S0=>rcnt_sub_1, S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_3, B1=>rcount_4, + BI=>co1_5, BOUT=>co2_5, S0=>rcnt_sub_3, S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_5, B1=>rcount_6, + BI=>co2_5, BOUT=>co3_5, S0=>rcnt_sub_5, S1=>rcnt_sub_6); + + rcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_7, B1=>rcount_8, + BI=>co3_5, BOUT=>co4_3, S0=>rcnt_sub_7, S1=>rcnt_sub_8); + + rcnt_5: FSUB2B + port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co4_3, BOUT=>open, S0=>rcnt_sub_9, + S1=>open); + + ae_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + ae_set_cmp_0: AGEB2 + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6); + + ae_set_cmp_1: AGEB2 + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6); + + ae_set_cmp_2: AGEB2 + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_6, GE=>co2_6); + + ae_set_cmp_3: AGEB2 + port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_6, GE=>co3_6); + + ae_set_cmp_4: AGEB2 + port map (A0=>AmEmptyThresh(8), A1=>ae_set_setsig, + B0=>rcnt_reg_8, B1=>ae_set_clrsig, CI=>co3_6, GE=>ae_set_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, + S1=>open); + + wcnt_0: FSUB2B + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + BI=>scuba_vlo, BOUT=>co0_7, S0=>open, S1=>wcnt_sub_0); + + wcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + BI=>co0_7, BOUT=>co1_7, S0=>wcnt_sub_1, S1=>wcnt_sub_2); + + wcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + BI=>co1_7, BOUT=>co2_7, S0=>wcnt_sub_3, S1=>wcnt_sub_4); + + wcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + BI=>co2_7, BOUT=>co3_7, S0=>wcnt_sub_5, S1=>wcnt_sub_6); + + wcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + BI=>co3_7, BOUT=>co4_4, S0=>wcnt_sub_7, S1=>wcnt_sub_8); + + wcnt_5: FSUB2B + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co4_4, BOUT=>open, S0=>wcnt_sub_9, + S1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_8); + + af_set_cmp_1: AGEB2 + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), CI=>co0_8, GE=>co1_8); + + af_set_cmp_2: AGEB2 + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), CI=>co1_8, GE=>co2_8); + + af_set_cmp_3: AGEB2 + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), CI=>co2_8, GE=>co3_8); + + af_set_cmp_4: AGEB2 + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>scuba_vlo, CI=>co3_8, GE=>af_set_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_512depth_72width_reg_out is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:ALEB2 use entity ecp2m.ALEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:CB2 use entity ecp2m.CB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on -- 2.43.0