From e48df706474b3b80e6ba77747ef5a16565fe9811 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Thu, 9 Aug 2018 16:41:46 +0200 Subject: [PATCH] increase speed of fast slow control to 5 MHz --- mupix/Mupix8/sources/MupixBoard.vhd | 2 +- mupix/Mupix8/trb3_periph.vhd | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 958c2c7..18e2303 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -170,7 +170,7 @@ architecture Behavioral of MupixBoard8 is end component PixelControl; constant fpga_clk_speed : integer := 1e8; -- 100 MHz - constant mupix_spi_clk_speed : integer := 4e5; -- 400 kHz + constant mupix_spi_clk_speed : integer := 5e6; -- 5 MHz constant board_spi_clk_speed : integer := 5e4; -- 50 kHz signal mupixslctrl_i : MupixSlowControl; diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd index a5b6740..288e59e 100644 --- a/mupix/Mupix8/trb3_periph.vhd +++ b/mupix/Mupix8/trb3_periph.vhd @@ -117,7 +117,7 @@ end entity; architecture trb3_periph_arch of trb3_periph is constant c_clock_speed : clk_speed_t := c_40MHz; -- clock speed for data taking - constant c_linksimulation : integer := c_YES; -- built the link simulation part + constant c_linksimulation : integer := c_No; -- built the link simulation part -- only use clock speed = 40 -- MHz with this option -- 2.43.0