From e4958abef4758fdad004ea4739dc95f701bc89e4 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 14 Jun 2018 16:40:22 +0200 Subject: [PATCH] change reset handler to newer scheme --- code/clock_reset_handler.vhd | 15 +++++++++------ code/sedcheck.vhd | 4 ++-- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 82c87d7..d4b4147 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -12,6 +12,7 @@ entity clock_reset_handler is port ( CLOCK_IN : in std_logic; -- oscillator RESET_FROM_NET : in std_logic; + SEND_RESET_IN : in std_logic := '0'; BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; @@ -38,7 +39,7 @@ signal timer : unsigned(24 downto 0) := (others => '0'); signal clear_n_i : std_logic := '0'; signal reset_i, reset_rising, last_reset_i : std_logic; signal debug_reset_handler : std_logic_vector(15 downto 0); - +signal send_reset_detect, trb_reset_i : std_logic := '0'; signal pll_lock : std_logic; attribute syn_keep of clear_n_i : signal is true; @@ -72,15 +73,15 @@ gen_fast_clock : if USE_120_MHZ = 1 generate end generate; -clear_n_i <= timer(24) when rising_edge(clock_200_raw); +clear_n_i <= timer(22) when rising_edge(clock_200_raw); process begin wait until rising_edge(sys_clk_i); - if timer(24) = '1' then + if timer(22) = '1' then timer <= timer; elsif reset_rising = '1' then - timer <= 0; + timer <= (others => '0'); elsif pll_lock = '1' then timer <= timer + 1; end if; @@ -101,14 +102,16 @@ THE_RESET_HANDLER : trb_net_reset_handler SYSCLK_IN => sys_clk_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK) + TRB_RESET_IN => trb_reset_i, -- TRBnet reset signal (SYSCLK) CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE! RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => debug_reset_handler ); RESET_OUT <= reset_i; - +send_reset_detect <= SEND_RESET_IN when rising_edge(clock_200_raw); +trb_reset_i <= RESET_FROM_NET or (send_reset_detect and not SEND_RESET_IN); + last_reset_i <= reset_i when rising_edge(clock_200_raw); reset_rising <= reset_i and not last_reset_i; diff --git a/code/sedcheck.vhd b/code/sedcheck.vhd index 02087fe..d0c9ebf 100644 --- a/code/sedcheck.vhd +++ b/code/sedcheck.vhd @@ -195,8 +195,8 @@ status_i(8) <= sed_inprogress_q; status_i(9) <= sed_error_q; status_i(10) <= sed_edge; status_i(15 downto 11) <= (others => '0'); -status_i(23 downto 16) <= std_logic_vector(run_counter)(7 downto 0); -status_i(31 downto 24) <= std_logic_vector(error_counter)(7 downto 0); +status_i(23 downto 16) <= std_logic_vector(run_counter); +status_i(31 downto 24) <= std_logic_vector(error_counter); ERROR_OUT <= sed_error; DEBUG <= status_i when rising_edge(CLK); -- 2.43.0