From e4aa59ff23d338ff7b7c71091d2ebf591a76d2c0 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Wed, 25 Jun 2014 00:26:20 +0200 Subject: [PATCH] nxyter: additional debug line out for new addon board --- nxyter/nodelist.txt | 5 -- nxyter/source/debug_multiplexer.vhd | 27 +++++--- nxyter/source/registers.txt | 7 ++- nxyter/trb3_periph_multi.p2t | 2 +- nxyter/trb3_periph_nx1.vhd | 19 ++++-- nxyter/trb3_periph_nxyter.lpf | 95 +++++++---------------------- 6 files changed, 60 insertions(+), 95 deletions(-) diff --git a/nxyter/nodelist.txt b/nxyter/nodelist.txt index bf612aa..74db793 100755 --- a/nxyter/nodelist.txt +++ b/nxyter/nodelist.txt @@ -1,8 +1,3 @@ -[c1] -system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ [c2] system = linux corenum = 4 diff --git a/nxyter/source/debug_multiplexer.vhd b/nxyter/source/debug_multiplexer.vhd index 21df593..b116439 100644 --- a/nxyter/source/debug_multiplexer.vhd +++ b/nxyter/source/debug_multiplexer.vhd @@ -31,9 +31,14 @@ end entity; architecture Behavioral of debug_multiplexer is + -- Multiplexer signal port_select : std_logic_vector(7 downto 0); signal debug_line_o : std_logic_vector(15 downto 0); - + + -- Checkerboard + signal checker_counter : unsigned(15 downto 0); + + -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; signal slv_unknown_addr_o : std_logic; @@ -45,19 +50,27 @@ begin DEBUG_LINE_IN) begin if (unsigned(port_select) < NUM_PORTS) then - debug_line_o <= + debug_line_o <= DEBUG_LINE_IN(to_integer(unsigned(port_select))); elsif (unsigned(port_select) = NUM_PORTS) then -- Checkerboard - for I in 0 to 7 loop - debug_line_o(I * 2) <= CLK_IN; - debug_line_o(I * 2 + 1) <= not CLK_IN; - end loop; + debug_line_o <= checker_counter; else - debug_line_o <= (others => '1'); + debug_line_o <= (others => '1'); end if; end process PROC_MULTIPLEXER; + PROC_CHECKERBOARD: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + checker_counter <= (others => '0'); + else + checker_counter <= checker_counter + 1; + end if; + end if; + end process PROC_CHECKERBOARD; + PROC_SLAVE_BUS: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index 2ac959b..2da5a0a 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -48,9 +48,12 @@ 0x8160 : r/w Enable Testpulse Signal (default: off) 0x8161 : r/w Delay Testpulse Signal after Trigger (12 Bit, in 10ns) 0x8162 : r/w Length of Trigger TestPulse (12 Bit, in 4ns) -0x8163 : r Accepted Trigger Rate (28 Bit, in Hz) -0x8164 : r/w r: Invalid Timing Trigger Counter +0x8163 : r/w r: Invalid Timing Trigger Counter (16 Bit) w: Clear Counter +0x8164 : r/w Clear Countercceptred Trigger Rate (1/s) +0x8165 : r/w Testpulse Rate (1/s) +0x8166 : r/w Bit0: Bypass CTS Trigger + Bit1: Bypass Status Trigger -- NX Data Receiver 0x8500 : r current Timestamp FIFO value diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_multi.p2t index f4c82ff..b7195f8 100644 --- a/nxyter/trb3_periph_multi.p2t +++ b/nxyter/trb3_periph_multi.p2t @@ -1,7 +1,7 @@ -w -i 2 -l 5 --n 24 +-n 20 -t 30 -s 1 -c 1 diff --git a/nxyter/trb3_periph_nx1.vhd b/nxyter/trb3_periph_nx1.vhd index 1bb7be4..16cb420 100644 --- a/nxyter/trb3_periph_nx1.vhd +++ b/nxyter/trb3_periph_nx1.vhd @@ -67,7 +67,7 @@ entity trb3_periph is NX1B_ADC_B_IN : in std_logic; NX1B_ADC_NX_IN : in std_logic; NX1B_ADC_D_IN : in std_logic; - + --------------------------------------------------------------------------- -- END AddonBoard nXyter --------------------------------------------------------------------------- @@ -87,7 +87,8 @@ entity trb3_periph is LED_YELLOW : out std_logic; SUPPL : in std_logic; --terminated diff pair, PCLK, Pads --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) + TEST_LINE : out std_logic_vector(15 downto 0); + NX1_DEBUG_LINE : out std_logic_vector(15 downto 0) ); attribute syn_useioff : boolean; @@ -107,7 +108,8 @@ entity trb3_periph is attribute syn_useioff of FLASH_DIN : signal is true; attribute syn_useioff of FLASH_DOUT : signal is true; attribute syn_useioff of FPGA5_COMM : signal is true; - attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of TEST_LINE : signal is false; + attribute syn_useioff of NX1_DEBUG_LINE : signal is false; --attribute syn_useioff of INP : signal is false; attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true; @@ -273,6 +275,8 @@ architecture trb3_periph_arch of trb3_periph is signal nx1_regio_no_more_data_out : std_logic; signal nx1_regio_unknown_addr_out : std_logic; + signal nx1_debug_line_o : std_logic_vector(15 downto 0); + -- Internal Trigger signal fee1_trigger : std_logic; @@ -700,12 +704,15 @@ begin REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out, REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out, - DEBUG_LINE_OUT => TEST_LINE + DEBUG_LINE_OUT => nx1_debug_line_o --DEBUG_LINE_OUT => open ); - - FPGA5_COMM(10) <= fee1_trigger; + TEST_LINE <= nx1_debug_line_o; + NX1_DEBUG_LINE <= nx1_debug_line_o; + + FPGA5_COMM(10) <= fee1_trigger; + ----------------------------------------------------------------------------- -- nXyter Main and ADC Clocks ----------------------------------------------------------------------------- diff --git a/nxyter/trb3_periph_nxyter.lpf b/nxyter/trb3_periph_nxyter.lpf index c645d2d..7fc041f 100644 --- a/nxyter/trb3_periph_nxyter.lpf +++ b/nxyter/trb3_periph_nxyter.lpf @@ -74,7 +74,7 @@ LOCATE COMP "TEST_LINE_13" SITE "C10"; LOCATE COMP "TEST_LINE_14" SITE "H10"; LOCATE COMP "TEST_LINE_15" SITE "H11"; DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN SLEWRATE=FAST; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST; ################################################################# # Connection to AddOn @@ -159,79 +159,26 @@ IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4; IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4; IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4; - - -# nXyter 2 - -#LOCATE COMP "NX2_ADC_SAMPLE_CLK_OUT" SITE "Y19"; #DQLR0_2 #133 -#LOCATE COMP "NX2_RESET_OUT" SITE "W23"; #DQLR1_0 #169 -#LOCATE COMP "NX2_MAIN_CLK_OUT" SITE "AA26"; #DQLR1_4 #177 -#LOCATE COMP "NX2_TESTPULSE_OUT" SITE "AA24"; #DQLR1_6 #185 -#LOCATE COMP "NX2_DATA_CLK_IN" SITE "M23"; #DQSUR1_T #118 -##LOCATE COMP "NX2_DATA_CLK_IN" SITE "N23"; #DQUR2_2 #134 -# -#LOCATE COMP "NX2_I2C_SCL_INOUT" SITE "R25"; #DQLR2_0 #170 -#LOCATE COMP "NX2_I2C_SDA_INOUT" SITE "R26"; #DQLR2_1 #172 -#LOCATE COMP "NX2_I2C_REG_RESET_OUT" SITE "T25"; #DQLR2_2 #174 -#LOCATE COMP "NX2_I2C_SM_RESET_OUT" SITE "T24"; #DQLR2_3 #176 -# -#LOCATE COMP "NX2_SPI_SDIO_INOUT" SITE "T26"; #DQLR2_4 #178 -#LOCATE COMP "NX2_SPI_SCLK_OUT" SITE "U26"; #DQLR2_5 #180 -#LOCATE COMP "NX2_SPI_CSB_OUT" SITE "U24"; #DQLR2_6 #186 -# -#LOCATE COMP "NX2_ADC_D_IN" SITE "J23"; #DQUR0_0 #105 -#LOCATE COMP "NX2_ADC_A_IN" SITE "G26"; #DQUR0_2 #109 -#LOCATE COMP "NX2_ADC_DCLK_IN" SITE "F24"; #DQSUR0_T #113 -#LOCATE COMP "NX2_ADC_NX_IN" SITE "H26"; #DQUR0_4 #117 -#LOCATE COMP "NX2_ADC_B_IN" SITE "K23"; #DQUR0_6 #121 -#LOCATE COMP "NX2_ADC_FCLK_IN" SITE "F25"; #DQUR0_8 #125 #input only -# -#LOCATE COMP "NX2_TIMESTAMP_IN_0" SITE "H24"; #DQUR1_0 #106 -#LOCATE COMP "NX2_TIMESTAMP_IN_1" SITE "L20"; #DQUR1_2 #110 -#LOCATE COMP "NX2_TIMESTAMP_IN_2" SITE "K24"; #DQUR1_4 #114 -#LOCATE COMP "NX2_TIMESTAMP_IN_3" SITE "L24"; #DQUR1_6 #122 -#LOCATE COMP "NX2_TIMESTAMP_IN_4" SITE "M22"; #DQUR1_8 #126 -#LOCATE COMP "NX2_TIMESTAMP_IN_5" SITE "J26"; #DQUR2_0 #130 -#LOCATE COMP "NX2_TIMESTAMP_IN_6" SITE "K19"; #DQUR2_4 #138 -#LOCATE COMP "NX2_TIMESTAMP_IN_7" SITE "L25"; #DQUR2_6 #146 -# -# -##DEFINE PORT GROUP "LVDS_group3" "NX2_TIMESTAMP*" ; -##IOBUF GROUP "LVDS_group3" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100; -# -# -##DEFINE PORT GROUP "LVDS_group4" "NX2_ADC*IN" ; -##IOBUF GROUP "LVDS_group4" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25; -# -#IOBUF PORT "NX2_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -#IOBUF PORT "NX2_TESTPULSE_OUT" IO_TYPE=LVDS25; -#IOBUF PORT "NX2_MAIN_CLK_OUT" IO_TYPE=LVDS25; -#IOBUF PORT "NX2_RESET_OUT" IO_TYPE=LVDS25; -# -#IOBUF PORT "NX2_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN; -#IOBUF PORT "NX2_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP; -#IOBUF PORT "NX2_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP; -#IOBUF PORT "NX2_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP; -# -#IOBUF PORT "NX2_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN; -#IOBUF PORT "NX2_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN; -#IOBUF PORT "NX2_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP; - +# Nxyter Debug Lines Addon Board +LOCATE COMP "NX1_DEBUG_LINE_1" SITE "R25"; #DQLR2_0 #170 +LOCATE COMP "NX1_DEBUG_LINE_3" SITE "R26"; #DQLR2_1 #172 +LOCATE COMP "NX1_DEBUG_LINE_5" SITE "T25"; #DQLR2_2 #174 +LOCATE COMP "NX1_DEBUG_LINE_7" SITE "T24"; #DQLR2_3 #176 +LOCATE COMP "NX1_DEBUG_LINE_9" SITE "T26"; #DQLR2_4 #178 +LOCATE COMP "NX1_DEBUG_LINE_11" SITE "U26"; #DQLR2_5 #180 +LOCATE COMP "NX1_DEBUG_LINE_13" SITE "U24"; #DQLR2_6 #186 +LOCATE COMP "NX1_DEBUG_LINE_15" SITE "V24"; #DQLR2_7 #188 +LOCATE COMP "NX1_DEBUG_LINE_14" SITE "W23"; #DQLR1_0 #169 +LOCATE COMP "NX1_DEBUG_LINE_12" SITE "W22"; #DQLR1_1 #171 +LOCATE COMP "NX1_DEBUG_LINE_10" SITE "AA25"; #DQLR1_2 #173 +LOCATE COMP "NX1_DEBUG_LINE_8" SITE "Y24"; #DQLR1_3 #175 +LOCATE COMP "NX1_DEBUG_LINE_6" SITE "AA26"; #DQLR1_4 #177 +LOCATE COMP "NX1_DEBUG_LINE_4" SITE "AB26"; #DQLR1_5 #179 +LOCATE COMP "NX1_DEBUG_LINE_2" SITE "AA24"; #DQLR1_6 #185 +LOCATE COMP "NX1_DEBUG_LINE_0" SITE "AA23"; #DQLR1_7 #187 + +DEFINE PORT GROUP "NX1_DEBUG_LINE_group" "NX1_DEBUG_LINE_*" ; +IOBUF GROUP "NX1_DEBUG_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST; ################################################################# # Additional Lines to AddOn -- 2.43.0