From e522e4d44c3787ddb1088395221450a5d1def744 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 4 Oct 2010 13:53:28 +0000 Subject: [PATCH] *** empty log message *** --- testbenches/error_generator.vhd | 267 ++++++++++++---------- testbenches/tb_trb_net16_rxtx_control.vhd | 139 +++++++++-- 2 files changed, 258 insertions(+), 148 deletions(-) diff --git a/testbenches/error_generator.vhd b/testbenches/error_generator.vhd index 0af128f..b5c4b04 100644 --- a/testbenches/error_generator.vhd +++ b/testbenches/error_generator.vhd @@ -12,7 +12,7 @@ port( RX1_DATA_IN : in std_logic_vector(7 downto 0); RX1_DATA_OUT : out std_logic_vector(7 downto 0); - + RX2_DATA_IN : in std_logic_vector(7 downto 0); RX2_DATA_OUT : out std_logic_vector(7 downto 0); @@ -32,6 +32,10 @@ end entity; architecture arch of error_generator is + signal buf_RX1_DATA_OUT : std_logic_vector(7 downto 0); + signal buf_RX1_K_OUT : std_logic; + signal buf_RX1_CV_OUT : std_logic; + begin CV1_PROC : process @@ -44,107 +48,121 @@ begin wait until rising_edge(RXCLK_IN); UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 256.0)); + int_rand := INTEGER(TRUNC(rand * 1000000.0)); - if( (int_rand MOD 40) = 0 ) then - RX1_CV_OUT <= not RX1_CV_IN; + if( (int_rand MOD 500) = 0 ) then + buf_RX1_CV_OUT <= not RX1_CV_IN; assert false report "RX1_CV" severity note; wait for 40 ns; - RX1_CV_OUT <= RX1_CV_IN; + buf_RX1_CV_OUT <= RX1_CV_IN; else - RX1_CV_OUT <= RX1_CV_IN; + buf_RX1_CV_OUT <= RX1_CV_IN; end if; - wait for 400 ns; +-- wait for 400 ns; end process; -CV2_PROC : process -variable seed1 : positive; -variable seed2 : positive := 2; -variable rand : real; -variable int_rand : integer; -begin - - wait until rising_edge(RXCLK_IN); - - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 256.0)); - - if( (int_rand MOD 40) = 0 ) then - RX2_CV_OUT <= not RX2_CV_IN; - assert false report "RX2_CV" severity note; - wait for 40 ns; - RX2_CV_OUT <= RX2_CV_IN; - else - RX2_CV_OUT <= RX2_CV_IN; - end if; - - wait for 400 ns; - -end process; - -RD1_DATA_proc : process -variable seed1 : positive; -variable seed2 : positive := 3; -variable rand : real; -variable int_rand : integer; -begin - - wait until rising_edge(RXCLK_IN); - - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 256.0)); - - if( (int_rand MOD 40) = 0 ) then - - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 256.0)); - - RX1_DATA_OUT(int_rand mod 8) <= not RX1_DATA_IN(int_rand mod 8); - - assert false report "RX1_DATA" severity note; - - wait for 40 ns; - RX1_DATA_OUT <= RX1_DATA_IN; - else - RX1_DATA_OUT <= RX1_DATA_IN; - end if; - - wait for 400 ns; - -end process; - -RD2_DATA_proc : process -variable seed1 : positive; -variable seed2 : positive := 4; -variable rand : real; -variable int_rand : integer; -begin - - wait until rising_edge(RXCLK_IN); - - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 256.0)); - - if( (int_rand MOD 40) = 0 ) then - - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 256.0)); - - RX2_DATA_OUT(int_rand mod 8) <= not RX2_DATA_IN(int_rand mod 8); - - assert false report "RX2_DATA" severity note; - - wait for 40 ns; - RX2_DATA_OUT <= RX2_DATA_IN; - else - RX2_DATA_OUT <= RX2_DATA_IN; - end if; - - wait for 400 ns; - -end process; +-- CV2_PROC : process +-- variable seed1 : positive; +-- variable seed2 : positive := 2; +-- variable rand : real; +-- variable int_rand : integer; +-- begin +-- +-- wait until rising_edge(RXCLK_IN); +-- +-- UNIFORM(seed1, seed2, rand); +-- int_rand := INTEGER(TRUNC(rand * 2**20)); +-- +-- if( (int_rand MOD 500) = 0 ) then +-- RX2_CV_OUT <= not RX2_CV_IN; +-- assert false report "RX2_CV" severity note; +-- wait for 40 ns; +-- RX2_CV_OUT <= RX2_CV_IN; +-- else +-- RX2_CV_OUT <= RX2_CV_IN; +-- end if; + +-- wait for 400 ns; + +-- end process; + +-- RD1_DATA_proc : process +-- variable seed1 : positive; +-- variable seed2 : positive := 3; +-- variable rand : real; +-- variable int_rand : integer; +-- begin +-- +-- wait until rising_edge(RXCLK_IN); +-- +-- UNIFORM(seed1, seed2, rand); +-- int_rand := INTEGER(TRUNC(rand * 256.0)); +-- +-- if( (int_rand MOD 40) = 0 ) then +-- +-- UNIFORM(seed1, seed2, rand); +-- int_rand := INTEGER(TRUNC(rand * 256.0)); +-- +-- buf_RX1_DATA_OUT(int_rand mod 8) <= not RX1_DATA_IN(int_rand mod 8); +-- +-- assert false report "RX1_DATA" severity note; +-- +-- wait for 40 ns; +-- buf_RX1_DATA_OUT <= RX1_DATA_IN; +-- else +-- buf_RX1_DATA_OUT <= RX1_DATA_IN; +-- end if; +-- +-- wait for 400 ns; +-- +-- end process; +process + begin + wait until rising_edge(RXCLK_IN); + buf_RX1_DATA_OUT <= RX1_DATA_IN; + end process; + +RX1_DATA_OUT <= transport buf_RX1_DATA_OUT after 200 ns; +RX1_K_OUT <= transport buf_RX1_K_OUT after 200 ns; +RX1_CV_OUT <= transport buf_RX1_CV_OUT after 200 ns; + + +-- RD2_DATA_proc : process +-- variable seed1 : positive; +-- variable seed2 : positive := 4; +-- variable rand : real; +-- variable int_rand : integer; +-- begin +-- +-- wait until rising_edge(RXCLK_IN); +-- +-- UNIFORM(seed1, seed2, rand); +-- int_rand := INTEGER(TRUNC(rand * 256.0)); +-- +-- if( (int_rand MOD 40) = 0 ) then +-- +-- UNIFORM(seed1, seed2, rand); +-- int_rand := INTEGER(TRUNC(rand * 256.0)); +-- +-- RX2_DATA_OUT(int_rand mod 8) <= not RX2_DATA_IN(int_rand mod 8); +-- +-- assert false report "RX2_DATA" severity note; +-- +-- wait for 40 ns; +-- RX2_DATA_OUT <= RX2_DATA_IN; +-- else +-- RX2_DATA_OUT <= RX2_DATA_IN; +-- end if; +-- +-- wait for 400 ns; +-- +-- end process; + +RX2_DATA_OUT <= RX2_DATA_IN; +RX2_CV_OUT <= RX2_CV_IN; +RX2_K_OUT <= RX2_K_IN; K1_PROC : process variable seed1 : positive; @@ -156,45 +174,46 @@ begin wait until rising_edge(RXCLK_IN); UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 256.0)); + int_rand := INTEGER(TRUNC(rand * 1000000.0)); - if( (int_rand MOD 40) = 0 ) then - RX1_K_OUT <= not RX1_K_IN; + if( (int_rand MOD 10000) = 0 ) then + buf_RX1_K_OUT <= not RX1_K_IN; assert false report "RX1_K" severity note; - wait for 40 ns; - RX1_K_OUT <= RX1_K_IN; +-- assert false report int_rand'image(integer) severity note; + wait for 39 ns; + buf_RX1_K_OUT <= RX1_K_IN; else - RX1_K_OUT <= RX1_K_IN; + buf_RX1_K_OUT <= RX1_K_IN; end if; - wait for 400 ns; +-- wait for 400 ns; end process; -K2_PROC : process -variable seed1 : positive; -variable seed2 : positive := 6; -variable rand : real; -variable int_rand : integer; -begin - - wait until rising_edge(RXCLK_IN); - - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 256.0)); - - if( (int_rand MOD 40) = 0 ) then - RX2_K_OUT <= not RX2_K_IN; - assert false report "RX2_K" severity note; - wait for 40 ns; - RX2_K_OUT <= RX2_K_IN; - else - RX2_K_OUT <= RX2_K_IN; - end if; - - wait for 400 ns; - -end process; +-- K2_PROC : process +-- variable seed1 : positive; +-- variable seed2 : positive := 6; +-- variable rand : real; +-- variable int_rand : integer; +-- begin +-- +-- wait until rising_edge(RXCLK_IN); +-- +-- UNIFORM(seed1, seed2, rand); +-- int_rand := INTEGER(TRUNC(rand * 2**20)); +-- +-- if( (int_rand MOD 10000) = 0 ) then +-- RX2_K_OUT <= not RX2_K_IN; +-- assert false report "RX2_K" severity note; +-- wait for 39 ns; +-- RX2_K_OUT <= RX2_K_IN; +-- else +-- RX2_K_OUT <= RX2_K_IN; +-- end if; +-- +-- -- wait for 400 ns; +-- +-- end process; end architecture; diff --git a/testbenches/tb_trb_net16_rxtx_control.vhd b/testbenches/tb_trb_net16_rxtx_control.vhd index a83111c..ef841c1 100644 --- a/testbenches/tb_trb_net16_rxtx_control.vhd +++ b/testbenches/tb_trb_net16_rxtx_control.vhd @@ -74,6 +74,32 @@ architecture arch of rxtxtb is end component; + component error_generator is + port( + RXCLK_IN : in std_logic; + RESET_IN : in std_logic; + + RX1_DATA_IN : in std_logic_vector(7 downto 0); + RX1_DATA_OUT : out std_logic_vector(7 downto 0); + + RX2_DATA_IN : in std_logic_vector(7 downto 0); + RX2_DATA_OUT : out std_logic_vector(7 downto 0); + + RX1_K_IN : in std_logic; + RX1_K_OUT : out std_logic; + + RX2_K_IN : in std_logic; + RX2_K_OUT : out std_logic; + + RX1_CV_IN : in std_logic; + RX1_CV_OUT : out std_logic; + + RX2_CV_IN : in std_logic; + RX2_CV_OUT : out std_logic + ); + end component; + + signal clk : std_logic := '1'; signal clk251 : std_logic := '1'; signal clk252 : std_logic := '1'; @@ -128,7 +154,17 @@ architecture arch of rxtxtb is signal dataready2 : std_logic; signal number2 : std_logic_vector(2 downto 0); signal data2 : std_logic_vector(15 downto 0); - signal dummy : std_logic_vector(31 downto 0); + signal dummy : std_logic_vector(63 downto 0); + + signal rxdata1 : std_logic_vector(15 downto 0); + signal rxdata2 : std_logic_vector(15 downto 0); + signal rxdataready1 : std_logic; + signal rxdataready2 : std_logic; + + signal rxdata2_in : std_logic_vector(15 downto 0); + signal rxdataready2_in : std_logic; + signal rxpacketnum2_in : std_logic_vector(2 downto 0); + signal rxread2_out : std_logic; begin @@ -296,10 +332,10 @@ begin RX_ALLOW_IN => rx2_allow_in, -- media interface SYSCLK_IN => clk, - MED_DATA_OUT => open, - MED_DATAREADY_OUT => open, - MED_READ_IN => '1', - MED_PACKET_NUM_OUT => open, + MED_DATA_OUT => rxdata2_in, + MED_DATAREADY_OUT => rxdataready2_in, + MED_READ_IN => rxread2_out, + MED_PACKET_NUM_OUT => rxpacketnum2_in, -- request retransmission in case of error while receiving REQUEST_RETRANSMIT_OUT => tx2_request_retransmit_in, REQUEST_POSITION_OUT => tx2_request_position_in, @@ -324,10 +360,29 @@ rx1_data_in <= transport tx2_data_out after 200 ns; rx1_k_in <= transport tx2_k_out after 200 ns; rx1_cv_in <= '0'; -rx2_data_in <= transport tx1_data_out after 200 ns; -rx2_k_in <= transport tx1_k_out after 200 ns; -rx2_cv_in <= '0', '1' after 4400 ns, '0' after 4440 ns; +-- rx2_data_in <= transport tx1_data_out after 200 ns; +-- rx2_k_in <= transport tx1_k_out after 200 ns; +-- rx2_cv_in <= '0', '1' after 4400 ns, '0' after 4440 ns; +THE_ERROR : error_generator + port map( + RXCLK_IN => clk251, + RESET_IN => reset, + + RX1_DATA_IN => tx1_data_out, + RX1_DATA_OUT => rx2_data_in, + RX1_K_IN => tx1_k_out, + RX1_K_OUT => rx2_k_in, + RX1_CV_IN => '0', + RX1_CV_OUT => rx2_cv_in, + + RX2_DATA_IN => x"00", + RX2_DATA_OUT => open, + RX2_K_IN => '0', + RX2_K_OUT => open, + RX2_CV_IN => '0', + RX2_CV_OUT => open + ); --------------------------------------------------------------------- --Data input 1 @@ -342,15 +397,15 @@ rx2_cv_in <= '0', '1' after 4400 ns, '0' after 4440 ns; toggle1 <= '0'; counter1 <= (others => '0'); else - if ((counter1 < 19 and toggle1 = '1') or (counter1 < 14 and toggle1 = '0')) or - (((counter1 < 20 and toggle1 = '1') or (counter1 < 15 and toggle1 = '0')) and read1 = '0') then + if ((counter1 < 199 and toggle1 = '1') or (counter1 < 149 and toggle1 = '0')) or + (((counter1 < 200 and toggle1 = '1') or (counter1 < 150 and toggle1 = '0')) and read1 = '0') then dataready1 <= '1'; if read1 = '1' and dataready1 = '1' then counter1 <= counter1 + 1; end if; else dataready1 <= '0'; - if counter1 = 2046 then + if counter1 = 1530 then counter1 <= (others => '0'); toggle1 <= not toggle1; else @@ -386,16 +441,15 @@ rx2_cv_in <= '0', '1' after 4400 ns, '0' after 4440 ns; toggle2 <= '0'; counter2 <= (others => '0'); else - if ((counter2 < 23 and toggle2 = '1') or (counter2 < 18 and toggle2 = '0')) or - (((counter2 < 24 and toggle2 = '1') or (counter2 < 19 and toggle2 = '0')) and read2 = '0') or - (counter2 = 30 and (dataready2 = '0' or read2 = '0')) then + if ((counter2 < 24 and toggle2 = '1') or (counter2 < 19 and toggle2 = '0')) or + (((counter2 < 25 and toggle2 = '1') or (counter2 < 20 and toggle2 = '0')) and read2 = '0') then dataready2 <= '1'; if read2 = '1' and dataready2 = '1' then counter2 <= counter2 + 1; end if; else dataready2 <= '0'; - if counter2 = 2047 then + if counter2 = 2000 then counter2 <= (others => '0'); toggle2 <= not toggle2; else @@ -415,7 +469,7 @@ rx2_cv_in <= '0', '1' after 4400 ns, '0' after 4440 ns; --------------------------------------------------------------------- ---Multiplexer +--Sender Multiplexer --------------------------------------------------------------------- the_test_mux : trb_net16_io_multiplexer @@ -441,26 +495,63 @@ rx2_cv_in <= '0', '1' after 4400 ns, '0' after 4440 ns; INT_PACKET_NUM_OUT => open, INT_DATAREADY_OUT => open, INT_READ_IN => (others => '1'), - INT_DATAREADY_IN(0) => dataready1, + INT_DATAREADY_IN(0) => dataready2, INT_DATAREADY_IN(1) => '0', - INT_DATAREADY_IN(2) => dataready2, + INT_DATAREADY_IN(2) => dataready1, INT_DATAREADY_IN(7 downto 3) => (others => '0'), - INT_DATA_IN(15 downto 0) => data1, + INT_DATA_IN(15 downto 0) => data2, INT_DATA_IN(31 downto 16) => (others => '0'), - INT_DATA_IN(47 downto 32) => data2, + INT_DATA_IN(47 downto 32) => data1, INT_DATA_IN(127 downto 48) => (others => '0'), - INT_PACKET_NUM_IN(2 downto 0) => number1, + INT_PACKET_NUM_IN(2 downto 0) => number2, INT_PACKET_NUM_IN(5 downto 3) => "000", - INT_PACKET_NUM_IN(8 downto 6) => number2, + INT_PACKET_NUM_IN(8 downto 6) => number1, INT_PACKET_NUM_IN(23 downto 9)=> (others => '0'), - INT_READ_OUT(0) => read1, + INT_READ_OUT(0) => read2, INT_READ_OUT(1) => dummy(0), - INT_READ_OUT(2) => read2, + INT_READ_OUT(2) => read1, INT_READ_OUT(3) => dummy(1), INT_READ_OUT(7 downto 4) => dummy(6 downto 3), ctrl => (others => '0') ); +--------------------------------------------------------------------- +--Receiver Multiplexer +--------------------------------------------------------------------- + + the_test_rx_mux : trb_net16_io_multiplexer + generic map ( + USE_INPUT_SBUF => (others => c_NO) + ) + port map( + -- Misc + CLK => clk, + RESET => reset, + CLK_EN => '1', + -- Media direction port + MED_DATAREADY_IN => rxdataready2_in, + MED_DATA_IN => rxdata2_in, + MED_PACKET_NUM_IN => rxpacketnum2_in, + MED_READ_OUT => rxread2_out, + MED_DATAREADY_OUT => open, + MED_DATA_OUT => open, + MED_PACKET_NUM_OUT => open, + MED_READ_IN => '1', + -- Internal direction port + INT_DATA_OUT(15 downto 0) => rxdata2, + INT_DATA_OUT(31 downto 16)=> rxdata1, + INT_DATA_OUT(63 downto 32)=> dummy(40 downto 9), + INT_PACKET_NUM_OUT => open, + INT_DATAREADY_OUT(0) => rxdataready2, + INT_DATAREADY_OUT(1) => rxdataready1, + INT_DATAREADY_OUT(3 downto 2) => dummy(8 downto 7), + INT_READ_IN => (others => '1'), + INT_DATAREADY_IN => (others => '0'), + INT_DATA_IN => (others => '0'), + INT_PACKET_NUM_IN => (others => '0'), + INT_READ_OUT => open, + ctrl => (others => '0') + ); -- --Data 1 input -- 2.43.0