From e60369d5b8cbb48043970848da3789f5d88431ef Mon Sep 17 00:00:00 2001 From: hadaq Date: Mon, 17 Oct 2011 18:00:36 +0000 Subject: [PATCH] update --- pexor/kernel-module/pexor_trb.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/pexor/kernel-module/pexor_trb.c b/pexor/kernel-module/pexor_trb.c index 5d8f747..c3ac4df 100644 --- a/pexor/kernel-module/pexor_trb.c +++ b/pexor/kernel-module/pexor_trb.c @@ -1233,7 +1233,8 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata *priv, unsigned long arg) { unsigned int i; if (descriptor.arg1 > PEXOR_MEMWRITE_SIZE) { - pexor_msg(KERN_ERR "ERROR> REG_WRITE_MEM: invalid size%x\n", command); + pexor_msg(KERN_ERR "ERROR> REG_WRITE_MEM: invalid size: %d shoud be < %d\n", + descriptor.arg1, PEXOR_MEMWRITE_SIZE); status = -EFAULT; goto OUT_IOCTL; } @@ -1360,18 +1361,24 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata *priv, unsigned long arg) /* wait for dma complete */ for (loops = 0; loops < PEXOR_DMA_MAXPOLLS * 100; loops++) { dmastat = ioread32(priv->pexor.dma_control_stat); + //pexor_msg(KERN_ERR "DMA: Status: is: 0x%08x %d\n", dmastat, loops); mb(); if ((dmastat & PEXOR_TRB_BIT_DMA_FINISHED) != 0) { /* DMA is completed */ dmaSize = dmastat >> 8; + if (dmaSize == 0) { + pexor_msg(KERN_ERR "DMA: Zero Length Error, Status: 0x%08x\n", dmastat); + } break; } if ((dmastat & PEXOR_TRB_BIT_DMA_MORE) != 0) { /* Card needs more DMA-Buffers */ + //pexor_msg(KERN_ERR "DMA: More Status: 0x%08x\n", dmastat); break; } if ((dmastat & PEXOR_TRB_BIT_DMA_TIMEOUT) != 0) { /* TRBNet Timeout */ + //pexor_msg(KERN_ERR "DMA: Timeout Status: 0x%08x\n", dmastat); pexor_msg(KERN_ERR "ERROR> wait_dma_complete: TRBNet Timeout Bit set " "Status: 0x%08x\n", @@ -1414,9 +1421,8 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata *priv, unsigned long arg) } status = dmaSize; - pexor_msg(KERN_ERR "DMA: dmaSize: %d\n", dmaSize); - //#ifdef PEXOR_TRB_DEBUG -#if 1 + +#ifdef PEXOR_TRB_DEBUG { int i; pexor_msg(KERN_ERR "DMA: dmaSize: %d\n", dmaSize); @@ -1429,10 +1435,7 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata *priv, unsigned long arg) } } #endif - OUT_DMA: - /* reset DMA */ - iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat); - + } else { /* do FIFO transfer to DMA Buffer */ pexor_dbg(KERN_ERR "Start FIFO copy to DMA buffer\n"); @@ -1443,6 +1446,8 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata *priv, unsigned long arg) } } +OUT_DMA: + OUT_IOCTL: spin_unlock((&(priv->dma_lock))); return status; -- 2.43.0