From e69691286f21f8e7ad1be6a9f9a41f5dbf934303 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 7 Mar 2018 13:58:21 +0100 Subject: [PATCH] re-add PLL to calibration signal generation --- releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd | 8 +++++++- releases/tdc_v2.3/trb3_periph_gpin.vhd | 8 +++++++- releases/tdc_v2.3/trb3_periph_padiwa.vhd | 8 +++++++- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd index 3a9ca8d..e9d68ed 100644 --- a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd +++ b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd @@ -93,6 +93,7 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -165,6 +166,11 @@ begin LOCK => pll_lock ); + pll_calibration : entity work.pll_in125_out33 + port map ( + CLK => CLK_GPLL_LEFT, + CLKOP => osc_int, + LOCK => open); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -402,7 +408,7 @@ begin CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => CLK_GPLL_LEFT, -- Hits for calibrating the TDC + HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), diff --git a/releases/tdc_v2.3/trb3_periph_gpin.vhd b/releases/tdc_v2.3/trb3_periph_gpin.vhd index d6c13b2..a18d554 100644 --- a/releases/tdc_v2.3/trb3_periph_gpin.vhd +++ b/releases/tdc_v2.3/trb3_periph_gpin.vhd @@ -95,6 +95,7 @@ architecture trb3_periph_gpin_arch of trb3_periph_gpin is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal clk_cal : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -242,6 +243,11 @@ begin LOCK => pll_lock ); + pll_calibration : entity work.pll_in125_out33 + port map ( + CLK => CLK_GPLL_LEFT, + CLKOP => clk_cal, + LOCK => open); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -656,7 +662,7 @@ begin CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => CLK_GPLL_LEFT, -- Hits for calibrating the TDC + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), diff --git a/releases/tdc_v2.3/trb3_periph_padiwa.vhd b/releases/tdc_v2.3/trb3_periph_padiwa.vhd index 569c98e..d02e501 100644 --- a/releases/tdc_v2.3/trb3_periph_padiwa.vhd +++ b/releases/tdc_v2.3/trb3_periph_padiwa.vhd @@ -104,6 +104,7 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -267,6 +268,11 @@ begin LOCK => pll_lock ); + pll_calibration: entity work.pll_in125_out33 + port map ( + CLK => CLK_GPLL_LEFT, + CLKOP => osc_int, + LOCK => open); gen_sync_clocks : if SYNC_MODE = c_YES generate clk_100_i <= rx_clock_100; @@ -720,7 +726,7 @@ begin CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => CLK_GPLL_LEFT, -- Hits for calibrating the TDC + HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), -- 2.43.0