From e75b0c04a79592f84114d4467505ca05b7884f4f Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 4 Apr 2014 15:45:05 +0200 Subject: [PATCH] Fixed CBM MBS implementation in CTS and connected again to TDC --- cts/compile_central_frankfurt.pl | 2 +- cts/config_default.vhd | 5 +++-- cts/source/mbs_vulom_recv.vhd | 7 +++++++ cts/trb3_central.vhd | 18 +++++++++++------- cts/trb3_central_constraints.lpf | 4 ++-- 5 files changed, 24 insertions(+), 12 deletions(-) diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index 81eecdb..d77d2bc 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -48,7 +48,7 @@ unless(-e 'workdir') { #create full lpf file system("cp ../base/trb3_central_cts.lpf workdir/$TOPNAME.lpf"); -system("cat tdc_release/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); +system("cat tdc_release/tdc_constraints_4.lpf >> workdir/$TOPNAME.lpf"); system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); system("sed -i 's#THE_TDC/#gen_TDC_THE_TDC/#g' workdir/$TOPNAME.lpf"); diff --git a/cts/config_default.vhd b/cts/config_default.vhd index 2c371db..eee9a7f 100644 --- a/cts/config_default.vhd +++ b/cts/config_default.vhd @@ -11,7 +11,8 @@ package config is ------------------------------------------------------------------------------ --include TDC for all four trigger input lines - constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO; + constant INCLUDE_TDC : integer range c_NO to c_YES := c_YES; + constant TDC_CHANNEL_NUMBER : integer := 5; --use all four SFP (1-4) as downlink to other boards. constant USE_4_SFP : integer range c_NO to c_YES := c_NO; @@ -22,7 +23,7 @@ package config is --Which external trigger module (ETM) to use? type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2); - constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MAINZ_A2; + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; ------------------------------------------------------------------------------ --End of configuration diff --git a/cts/source/mbs_vulom_recv.vhd b/cts/source/mbs_vulom_recv.vhd index bcc1325..631323e 100644 --- a/cts/source/mbs_vulom_recv.vhd +++ b/cts/source/mbs_vulom_recv.vhd @@ -33,6 +33,12 @@ entity mbs_vulom_recv is HEADER_REG_OUT : out std_logic_vector(1 downto 0); DEBUG : out std_logic_vector(31 downto 0) ); + + attribute syn_useioff : boolean; + --no IO-FF for MBS input + attribute syn_useioff of MBS_IN : signal is false; + + end entity; --MBS format @@ -105,6 +111,7 @@ TRG_SYNC_OUT <= trg_sync when rising_edge(CLK); PROC_FSM: process begin wait until rising_edge(CLK_200); + case state is when IDLE => bitcnt <= 37; diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index 30c98eb..ffe9852 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -371,7 +371,7 @@ architecture trb3_central_arch of trb3_central is signal timer_ticks : std_logic_vector(1 downto 0); signal trigger_busy_i : std_logic; - signal trigger_in_buf_i : std_logic_vector(3 downto 0); + signal tdc_inputs : std_logic_vector(TDC_CHANNEL_NUMBER-2 downto 0); signal select_tc : std_logic_vector(31 downto 0); signal select_tc_data_in : std_logic_vector(31 downto 0); @@ -431,8 +431,8 @@ architecture trb3_central_arch of trb3_central is signal led_time_ref_i : std_logic; begin -- MBS Module - gen_mbs_vulom_as_etm : if ETM_CHOICE = ETM_CHOICE_MBS_VULOM generate - THE_MBS: entity work.mbs_vulom_recv + gen_mbs_vulom_as_etm : if ETM_CHOICE = ETM_CHOICE_MBS_VULOM generate + THE_MBS: entity work.mbs_vulom_recv port map ( CLK => clk_100_i, RESET_IN => reset_i, @@ -440,7 +440,7 @@ begin MBS_IN => CLK_EXT(3), CLK_200 => clk_200_i, - -- TRG_ASYNC_OUT => , + TRG_ASYNC_OUT => tdc_inputs(0), TRG_SYNC_OUT => cts_ext_trigger, TRIGGER_IN => cts_rdo_trg_data_valid, @@ -455,6 +455,7 @@ begin DEBUG => cts_ext_debug ); + end generate; -- Mainz A2 Module @@ -1297,7 +1298,7 @@ THE_FPGA_REBOOT : fpga_reboot gen_TDC : if INCLUDE_TDC = c_YES generate THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 5, -- Number of TDC channels + CHANNEL_NUMBER => TDC_CHANNEL_NUMBER, -- Number of TDC channels STATUS_REG_NR => 20, -- Number of status regs CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr TDC_VERSION => x"160" -- TDC version number @@ -1307,7 +1308,7 @@ gen_TDC : if INCLUDE_TDC = c_YES generate CLK_TDC => CLK_PCLK_RIGHT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => cts_trigger_out, -- Reference time input - HIT_IN => trigger_in_buf_i, -- Channel start signals + HIT_IN => tdc_inputs, -- Channel start signals HIT_CALIBRATION => osc_int, --clk_20_i, -- Hits for calibrating the TDC TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width @@ -1491,7 +1492,10 @@ LED_YELLOW <= link_ok; --debug(3); -- TEST_LINE(9) <= med_dataready_out(0); TEST_LINE(15 downto 0) <= tdc_debug; - TEST_LINE(31 downto 16) <= (others => '0'); + + TEST_LINE(16) <= CLK_EXT(3); --this prevents adding an input register in the CBM MBS input module + + TEST_LINE(31 downto 17) <= (others => '0'); -- TEST_LINE(31 downto 0) <= cts_ext_debug; diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf index 933eec9..c9ba32a 100644 --- a/cts/trb3_central_constraints.lpf +++ b/cts/trb3_central_constraints.lpf @@ -55,8 +55,8 @@ LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; # UGROUP "cts_group" # BLKNAME THE_CTS; # LOCATE UGROUP "cts_group" REGION "REGION_CTS"; -MULTICYCLE TO CELL "THE_MBS/trg_sync" 20 ns; -MULTICYCLE TO CELL "THE_MBS/error_reg" 20 ns; +MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/trg_sync" 20 ns; +MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/error_reg" 20 ns; #TrbNet Hub REGION "REGION_IOBUF" "R40C40D" 55 75 DEVSIZE; -- 2.43.0