From e83101ab5e80b9716f93f6942fab0f4c8423ee5f Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Tue, 15 Apr 2014 14:44:02 +0200 Subject: [PATCH] preparing to move from source to code --- soda_source.ldf | 38 +- soda_source_probe.rvl | 18 +- source/med_ecp3_sfp_4_sync_down.vhd | 662 ++++++ source/serdes_sync_client_upstream.ipx | 11 + source/serdes_sync_client_upstream.vhd | 2698 ++++++++++++++++++++++ source/soda_clockscaler.vhd | 50 + source/soda_cmd_handler.vhd | 170 ++ source/soda_hub_synconstraints.fdc | 64 + source/soda_source_clock_constraints.sdc | 11 + source/soda_source_syn_translated.fdc | 66 + source/soda_tx_control.vhd | 515 +++++ source/trb3_periph_sodahub.vhd | 784 +++++++ source/trb_net_CRC.vhd | 74 + source/trb_net_CRC8.vhd | 61 + 14 files changed, 5192 insertions(+), 30 deletions(-) create mode 100644 source/med_ecp3_sfp_4_sync_down.vhd create mode 100644 source/serdes_sync_client_upstream.ipx create mode 100644 source/serdes_sync_client_upstream.vhd create mode 100644 source/soda_clockscaler.vhd create mode 100644 source/soda_cmd_handler.vhd create mode 100644 source/soda_hub_synconstraints.fdc create mode 100644 source/soda_source_clock_constraints.sdc create mode 100644 source/soda_source_syn_translated.fdc create mode 100644 source/soda_tx_control.vhd create mode 100644 source/trb3_periph_sodahub.vhd create mode 100644 source/trb_net_CRC.vhd create mode 100644 source/trb_net_CRC8.vhd diff --git a/soda_source.ldf b/soda_source.ldf index c15cb96..fbb4eb8 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -5,46 +5,40 @@ - + - + - + - + - + - + - + - + - + - + - + - - - - - - - + @@ -308,13 +302,13 @@ - + - + - + @@ -323,7 +317,7 @@ - + diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl index 16425f8..e089486 100644 --- a/soda_source_probe.rvl +++ b/soda_source_probe.rvl @@ -1,10 +1,10 @@ - + - + - + @@ -172,14 +172,16 @@ - - - - - + + + + + + + diff --git a/source/med_ecp3_sfp_4_sync_down.vhd b/source/med_ecp3_sfp_4_sync_down.vhd new file mode 100644 index 0000000..b17c088 --- /dev/null +++ b/source/med_ecp3_sfp_4_sync_down.vhd @@ -0,0 +1,662 @@ +--4 channel Media interface for Lattice ECP3 using PCS at 2GHz + +LIBRARY IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; +use IEEE.std_logic_unsigned.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; +use work.soda_components.all; + +entity med_ecp3_sfp_4_sync_down is + generic( SERDES_NUM : integer range 0 to 3 := 0; + IS_SYNC_SLAVE : integer := c_NO); --select slave mode + port( + CLK : in std_logic; -- _internal_ 200 MHz reference clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + --------------------------------------------------------------------------------------------------------------------------------------------------------- + LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. + --------------------------------------------------------------------------------------------------------------------------------------------------------- + --Internal Connection TX + MED_DATA_IN : in t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0'); + --Internal Connection RX + MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0'); + MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); + MED_READ_IN : in std_logic_vector(3 downto 0); + + CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + + --Sync operation + RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! + LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! + + --SFP Connection + SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used + SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used + SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + -- Status and control port + STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); + CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end entity; + + +architecture med_ecp3_sfp_4_sync_down_arch of med_ecp3_sfp_4_sync_down is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of med_ecp3_sfp_4_sync_down_arch : architecture is "media_downlink_group"; + attribute syn_sharing : string; + attribute syn_sharing of med_ecp3_sfp_4_sync_down_arch : architecture is "off"; + + + +component DCS +-- synthesis translate_off +generic + ( + DCSMODE : string :=“POS” + ); +-- synthesis translate_on +port ( + CLK0 : in std_logic ; + CLK1 : in std_logic ; + SEL : in std_logic ; + DCSOUT : out std_logic) ; +end component; + + +signal clk_200_i : std_logic_vector(3 downto 0); +signal clk_200_internal : std_logic_vector(3 downto 0); +signal clk_rx_full : std_logic_vector(3 downto 0); +signal clk_rx_half : std_logic_vector(3 downto 0); +signal clk_tx_full : std_logic_vector(3 downto 0); +signal clk_tx_half : std_logic_vector(3 downto 0); + +signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); +signal tx_k : std_logic_vector(3 downto 0); +signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); +signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0); + + +signal rst_n : t_HUB_BIT; +signal rst : t_HUB_BIT; -- PL! +signal rx_serdes_rst : t_HUB_BIT; +signal tx_serdes_rst : t_HUB_BIT; +signal tx_pcs_rst : t_HUB_BIT; +signal rx_pcs_rst : t_HUB_BIT; +signal rst_qd : t_HUB_BIT; +signal rst_down_quad : std_logic; +signal serdes_rst_qd : t_HUB_BIT; +signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad +signal sd_los_i : t_HUB_BIT; --PL! + +signal rx_los_low : t_HUB_BIT; +signal lsm_status : t_HUB_BIT; +signal rx_cdr_lol : t_HUB_BIT; +signal tx_pll_lol : t_HUB_BIT; +signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad + +signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; +signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; +signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL! +signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0); +signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0); +signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0); + +signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0'); +signal watchdog_timer : t_HUB_TIMER21 := (others => (others => '0')); --unsigned(20 downto 0) := (others => '0'); +signal watchdog_trigger : t_HUB_BIT := (others => '0'); --std_logic_vector(3 downto 0) := (others => '0'); + +signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); +signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); + + +signal sci_ch_i : std_logic_vector(3 downto 0); +signal sci_qd_i : std_logic; +signal sci_reg_i : std_logic; +signal sci_addr_i : std_logic_vector(8 downto 0); +signal sci_data_in_i : std_logic_vector(7 downto 0); +signal sci_data_out_i : std_logic_vector(7 downto 0); +signal sci_read_i : std_logic; +signal sci_write_i : std_logic; +signal sci_write_shift_i : std_logic_vector(2 downto 0); +signal sci_read_shift_i : std_logic_vector(2 downto 0); + +signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); +signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); +signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); +signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); +signal debug_reg : std_logic_vector(63 downto 0); + +type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); +signal sci_state : sci_ctrl; +signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0'); + +begin + + +--SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready + + +gen_clocks : for i in 0 to 3 generate + + rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); + rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); + + clk_200_internal(i) <= CLK; -- This external clock is the rx_fulll of the uplink !!! + CLK_RX_FULL_OUT(i) <= clk_rx_full(i); + +-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate + clk_200_i(i) <= CLK; --clk_rx_full(i); +-- end generate; + +-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate +-- clk_200_i(i) <= clk_200_internal(i); +-- end generate; +end generate; + + +------------------------------------------------- +-- Serdes +------------------------------------------------- +THE_SERDES : entity work.serdes_4_sync_downstream + port map( + -- CHANNEL0 -- + hdinp_ch0 => SD_RXD_P_IN(0), + hdinn_ch0 => SD_RXD_N_IN(0), + hdoutp_ch0 => SD_TXD_P_OUT(0), + hdoutn_ch0 => SD_TXD_N_OUT(0), + sci_sel_ch0 => sci_ch_i(0), + txiclk_ch0 => clk_200_i(0), + rx_full_clk_ch0 => clk_rx_full(0), + rx_half_clk_ch0 => clk_rx_half(0), + tx_full_clk_ch0 => clk_tx_full(0), + tx_half_clk_ch0 => clk_tx_half(0), + fpga_rxrefclk_ch0 => clk_200_internal(0), + txdata_ch0 => tx_data(0), + tx_k_ch0 => tx_k(0), + tx_force_disp_ch0 => '0', + tx_disp_sel_ch0 => '0', + rxdata_ch0 => rx_data(0), + rx_k_ch0 => rx_k(0), + rx_disp_err_ch0 => open, + rx_cv_err_ch0 => rx_error(0), + rx_serdes_rst_ch0_c => rx_serdes_rst(0), + sb_felb_ch0_c => '0', + sb_felb_rst_ch0_c => '0', + tx_pcs_rst_ch0_c => tx_pcs_rst(0), + tx_pwrup_ch0_c => '1', + rx_pcs_rst_ch0_c => rx_pcs_rst(0), + rx_pwrup_ch0_c => '1', + rx_los_low_ch0_s => rx_los_low(0), + lsm_status_ch0_s => lsm_status(0), + rx_cdr_lol_ch0_s => rx_cdr_lol(0), + tx_div2_mode_ch0_c => '0', + rx_div2_mode_ch0_c => '0', + -- CHANNEL1 -- + hdinp_ch1 => SD_RXD_P_IN(1), + hdinn_ch1 => SD_RXD_N_IN(1), + hdoutp_ch1 => SD_TXD_P_OUT(1), + hdoutn_ch1 => SD_TXD_N_OUT(1), + sci_sel_ch1 => sci_ch_i(1), + txiclk_ch1 => clk_200_i(1), + rx_full_clk_ch1 => clk_rx_full(1), + rx_half_clk_ch1 => clk_rx_half(1), + tx_full_clk_ch1 => clk_tx_full(1), + tx_half_clk_ch1 => clk_tx_half(1), + fpga_rxrefclk_ch1 => clk_200_internal(1), + txdata_ch1 => tx_data(1), + tx_k_ch1 => tx_k(1), + tx_force_disp_ch1 => '0', + tx_disp_sel_ch1 => '0', + rxdata_ch1 => rx_data(1), + rx_k_ch1 => rx_k(1), + rx_disp_err_ch1 => open, + rx_cv_err_ch1 => rx_error(1), + rx_serdes_rst_ch1_c => rx_serdes_rst(1), + sb_felb_ch1_c => '0', + sb_felb_rst_ch1_c => '0', + tx_pcs_rst_ch1_c => tx_pcs_rst(1), + tx_pwrup_ch1_c => '1', + rx_pcs_rst_ch1_c => rx_pcs_rst(1), + rx_pwrup_ch1_c => '1', + rx_los_low_ch1_s => rx_los_low(1), + lsm_status_ch1_s => lsm_status(1), + rx_cdr_lol_ch1_s => rx_cdr_lol(1), + tx_div2_mode_ch1_c => '0', + rx_div2_mode_ch1_c => '0', + -- CHANNEL2 -- + hdinp_ch2 => SD_RXD_P_IN(2), + hdinn_ch2 => SD_RXD_N_IN(2), + hdoutp_ch2 => SD_TXD_P_OUT(2), + hdoutn_ch2 => SD_TXD_N_OUT(2), + sci_sel_ch2 => sci_ch_i(2), + txiclk_ch2 => clk_200_i(2), + rx_full_clk_ch2 => clk_rx_full(2), + rx_half_clk_ch2 => clk_rx_half(2), + tx_full_clk_ch2 => clk_tx_full(2), + tx_half_clk_ch2 => clk_tx_half(2), + fpga_rxrefclk_ch2 => clk_200_internal(2), + txdata_ch2 => tx_data(2), + tx_k_ch2 => tx_k(2), + tx_force_disp_ch2 => '0', + tx_disp_sel_ch2 => '0', + rxdata_ch2 => rx_data(2), + rx_k_ch2 => rx_k(2), + rx_disp_err_ch2 => open, + rx_cv_err_ch2 => rx_error(2), + rx_serdes_rst_ch2_c => rx_serdes_rst(2), + sb_felb_ch2_c => '0', + sb_felb_rst_ch2_c => '0', + tx_pcs_rst_ch2_c => tx_pcs_rst(2), + tx_pwrup_ch2_c => '1', + rx_pcs_rst_ch2_c => rx_pcs_rst(2), + rx_pwrup_ch2_c => '1', + rx_los_low_ch2_s => rx_los_low(2), + lsm_status_ch2_s => lsm_status(2), + rx_cdr_lol_ch2_s => rx_cdr_lol(2), + tx_div2_mode_ch2_c => '0', + rx_div2_mode_ch2_c => '0', + -- CHANNEL3 -- + hdinp_ch3 => SD_RXD_P_IN(3), + hdinn_ch3 => SD_RXD_N_IN(3), + hdoutp_ch3 => SD_TXD_P_OUT(3), + hdoutn_ch3 => SD_TXD_N_OUT(3), + sci_sel_ch3 => sci_ch_i(3), + txiclk_ch3 => clk_200_i(3), + rx_full_clk_ch3 => clk_rx_full(3), + rx_half_clk_ch3 => clk_rx_half(3), + tx_full_clk_ch3 => clk_tx_full(3), + tx_half_clk_ch3 => clk_tx_half(3), + fpga_rxrefclk_ch3 => clk_200_internal(3), + txdata_ch3 => tx_data(3), + tx_k_ch3 => tx_k(3), + tx_force_disp_ch3 => '0', + tx_disp_sel_ch3 => '0', + rxdata_ch3 => rx_data(3), + rx_k_ch3 => rx_k(3), + rx_disp_err_ch3 => open, + rx_cv_err_ch3 => rx_error(3), + rx_serdes_rst_ch3_c => rx_serdes_rst(3), + sb_felb_ch3_c => '0', + sb_felb_rst_ch3_c => '0', + tx_pcs_rst_ch3_c => tx_pcs_rst(3), + tx_pwrup_ch3_c => '1', + rx_pcs_rst_ch3_c => rx_pcs_rst(3), + rx_pwrup_ch3_c => '1', + rx_los_low_ch3_s => rx_los_low(3), + lsm_status_ch3_s => lsm_status(3), + rx_cdr_lol_ch3_s => rx_cdr_lol(3), + tx_div2_mode_ch3_c => '0', + rx_div2_mode_ch3_c => '0', + -- COMMON -- + sci_wrdata => sci_data_in_i, + sci_rddata => sci_data_out_i, + sci_addr => sci_addr_i(5 downto 0), + sci_sel_quad => sci_qd_i, + sci_rd => sci_read_i, + sci_wrn => sci_write_i, + + fpga_txrefclk => clk_200_i(0), + tx_serdes_rst_c => tx_serdes_rst(0), + tx_pll_lol_qd_s => tx_pll_lol_quad, + tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols + rst_qd_c => rst_down_quad, + serdes_rst_qd_c => serdes_rst_down_quad + ); + +------------------------- +-- combined quad reset -- +------------------------- +rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0'; +serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0'; + +generated_logic : for i in 0 to 3 generate + + SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready + + tx_pll_lol(i) <= tx_pll_lol_quad; + + ------------------------------------------------- + -- Reset FSM & Link states + ------------------------------------------------- + THE_RX_FSM : rx_reset_fsm + port map( + RST_N => rst_n(i), + RX_REFCLK => clk_200_i(i), + TX_PLL_LOL_QD_S => tx_pll_lol(i), + RX_SERDES_RST_CH_C => rx_serdes_rst(i), + RX_CDR_LOL_CH_S => rx_cdr_lol(i), + RX_LOS_LOW_CH_S => rx_los_low(i), + RX_PCS_RST_CH_C => rx_pcs_rst(i), + WA_POSITION => wa_position_rx(i), + STATE_OUT => rx_fsm_state(i) + ); + + THE_TX_FSM : tx_reset_fsm + port map( + RST_N => rst_n(i), + TX_REFCLK => clk_200_internal(i), + TX_PLL_LOL_QD_S => tx_pll_lol(i), + RST_QD_C => rst_qd(i), + TX_PCS_RST_CH_C => tx_pcs_rst(i), + STATE_OUT => tx_fsm_state(i) + ); + + + -- Master does not do bit-locking + wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0"; + + + PROC_ALLOW : process(clk_200_i(i)) + begin + if rising_edge(clk_200_i(i)) then + if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then + rx_allow(i) <= '1'; + tx_allow(i) <= '1'; + else + rx_allow(i) <= '0'; + tx_allow(i) <= '1'; + end if; + end if; + end process; + + rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK); + tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK); + + + PROC_START_TIMER : process(clk_200_i(i)) + begin + if rising_edge(clk_200_i(i)) then + if got_link_ready_i(i) = '1' then + watchdog_timer(i) <= (others => '0'); + if start_timer(i)(start_timer'left) = '0' then + start_timer(i) <= start_timer(i) + 1; +-- start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1; + end if; + else + start_timer(i) <= (others => '0'); + if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then + watchdog_trigger(i) <= '1'; + else + watchdog_trigger(i) <= '0'; + end if; + if watchdog_trigger(i) = '0' then + watchdog_timer(i) <= watchdog_timer(i) + 1; + else + watchdog_timer(i) <= (others => '0'); + end if; + end if; + end if; + end process; + ------------------------------------------------- + -- TX Data + ------------------------------------------------- + THE_TX : soda_tx_control + port map( + CLK_200 => clk_200_i(i), + CLK_100 => SYSCLK, + RESET_IN => rst(i), --CLEAR, PL! + + TX_DATA_IN => MED_DATA_IN(i), + TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN(i), + TX_WRITE_IN => MED_DATAREADY_IN(i), + TX_READ_OUT => MED_READ_OUT(i), + + TX_DATA_OUT => tx_data(i), + TX_K_OUT => tx_k(i), + + REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO + REQUEST_POSITION_IN => request_retr_position_i(i), --TODO + + START_RETRANSMIT_IN => start_retr_i(i), --TODO + START_POSITION_IN => request_retr_position_i(i), --TODO + + TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i), + SEND_DLM => TX_DLM(i), + SEND_DLM_WORD => TX_DLM_WORD(i), + + SEND_LINK_RESET_IN => CTRL_OP(i)(15), + TX_ALLOW_IN => tx_allow(i), + RX_ALLOW_IN => rx_allow(i), + LINK_PHASE_OUT => link_phase_S(i), --PL! + + DEBUG_OUT => debug_tx_control_i(i), + STAT_REG_OUT => stat_tx_control_i(i) + ); + + LINK_PHASE_OUT(i) <= link_phase_S(i); --PL! + ------------------------------------------------- + -- RX Data + ------------------------------------------------- + THE_RX_CONTROL : rx_control + port map( + CLK_200 => clk_rx_full(i), --clk_200_i, PL! + CLK_100 => SYSCLK, + RESET_IN => rst(i), --CLEAR, PL! + + RX_DATA_OUT => MED_DATA_OUT(i), + RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT(i), + RX_WRITE_OUT => MED_DATAREADY_OUT(i), + RX_READ_IN => MED_READ_IN(i), + + RX_DATA_IN => rx_data(i), + RX_K_IN => rx_k(i), + + REQUEST_RETRANSMIT_OUT => request_retr_i(i), + REQUEST_POSITION_OUT => request_retr_position_i(i), + + START_RETRANSMIT_OUT => start_retr_i(i), + START_POSITION_OUT => start_retr_position_i(i), + + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM + RX_DLM => RX_DLM(i), + RX_DLM_WORD => RX_DLM_WORD(i), + + SEND_LINK_RESET_OUT => send_link_reset_i(i), + MAKE_RESET_OUT => make_link_reset_i(i), + RX_ALLOW_IN => rx_allow(i), + GOT_LINK_READY => got_link_ready_i(i), + + DEBUG_OUT => debug_rx_control_i(i), + STAT_REG_OUT => stat_rx_control_i(i) + ); + + internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; + sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! + +end generate; + +------------------------------------------------- +-- SCI +------------------------------------------------- +--gives access to serdes config port from slow control and reads word alignment every ~ 40 us +PROC_SCI_CTRL: process +variable cnt : integer range 0 to 4 := 0; +begin +wait until rising_edge(SYSCLK); + SCI_ACK <= '0'; + case sci_state is + when IDLE => + sci_ch_i <= x"0"; + sci_qd_i <= '0'; + sci_reg_i <= '0'; + sci_read_i <= '0'; + sci_write_i <= '0'; + sci_timer(0) <= sci_timer(0) + 1; + sci_timer(1) <= sci_timer(1) + 1; + sci_timer(2) <= sci_timer(2) + 1; + sci_timer(3) <= sci_timer(3) + 1; + if SCI_READ = '1' or SCI_WRITE = '1' then + sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_addr_i <= SCI_ADDR; + sci_data_in_i <= SCI_DATA_IN; + sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_state <= SCTRL; + else + if sci_timer(0)(sci_timer'left) = '1' then + sci_timer(0) <= (others => '0'); + sci_state <= GET_WA; + end if; + if sci_timer(1)(sci_timer'left) = '1' then + sci_timer(1) <= (others => '0'); + sci_state <= GET_WA; + end if; + if sci_timer(2)(sci_timer'left) = '1' then + sci_timer(2) <= (others => '0'); + sci_state <= GET_WA; + end if; + if sci_timer(3)(sci_timer'left) = '1' then + sci_timer(3) <= (others => '0'); + sci_state <= GET_WA; + end if; + end if; +when SCTRL => + if sci_reg_i = '1' then + SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + else + sci_state <= SCTRL_WAIT; + end if; +when SCTRL_WAIT => + sci_state <= SCTRL_WAIT2; +when SCTRL_WAIT2 => + sci_state <= SCTRL_FINISH; +when SCTRL_FINISH => + SCI_DATA_OUT <= sci_data_out_i; + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + +when GET_WA => + if cnt = 4 then + cnt := 0; + sci_state <= IDLE; + else + sci_state <= GET_WA_WAIT; + sci_addr_i <= '0' & x"22"; + sci_ch_i <= x"0"; + sci_ch_i(cnt) <= '1'; + sci_read_i <= '1'; + end if; +when GET_WA_WAIT => + sci_state <= GET_WA_WAIT2; +when GET_WA_WAIT2 => + sci_state <= GET_WA_FINISH; +when GET_WA_FINISH => +-- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); + wa_position(cnt) <= sci_data_out_i(3 downto 0); + sci_state <= GET_WA; + cnt := cnt + 1; +end case; + +if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then + SCI_NACK <= '1'; +else + SCI_NACK <= '0'; +end if; + +end process; + + +-- ------------------------------------------------- +-- -- Debug Registers +-- ------------------------------------------------- +-- debug_reg(3 downto 0) <= rx_fsm_state; +-- debug_reg(4) <= rx_k; +-- debug_reg(5) <= rx_error; +-- debug_reg(6) <= rx_los_low; +-- debug_reg(7) <= rx_cdr_lol; +-- +-- debug_reg(8) <= tx_k; +-- debug_reg(9) <= tx_pll_lol; +-- debug_reg(10) <= lsm_status; +-- debug_reg(11) <= make_link_reset_i; +-- debug_reg(15 downto 12) <= tx_fsm_state; +-- -- debug_reg(31 downto 24) <= tx_data; +-- +-- debug_reg(16) <= '0'; +-- debug_reg(17) <= tx_allow; +-- debug_reg(18) <= RESET; +-- debug_reg(19) <= CLEAR; +-- debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8); +-- +-- debug_reg(35 downto 32) <= wa_position(3 downto 0); +-- debug_reg(36) <= debug_tx_control_i(6); +-- debug_reg(39 downto 37) <= "000"; +-- debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); + + + STAT_DEBUG <= (others => '0'); --debug_reg; + + generated_status : for i in 0 to 3 generate + -- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; + -- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! + + STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK); + STAT_OP(i)(14) <= '0'; + STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset + STAT_OP(i)(12) <= '0'; + STAT_OP(i)(11) <= '0'; + STAT_OP(i)(10) <= rx_allow(i); + STAT_OP(i)(9) <= tx_allow(i); + STAT_OP(i)(8) <= got_link_ready_i(i); + STAT_OP(i)(7) <= send_link_reset_i(i); + STAT_OP(i)(6) <= make_link_reset_i(i); + STAT_OP(i)(5) <= request_retr_i(i); + STAT_OP(i)(4) <= start_retr_i(i); + STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; + end generate; + +end med_ecp3_sfp_4_sync_down_arch; \ No newline at end of file diff --git a/source/serdes_sync_client_upstream.ipx b/source/serdes_sync_client_upstream.ipx new file mode 100644 index 0000000..c1cdc76 --- /dev/null +++ b/source/serdes_sync_client_upstream.ipx @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/source/serdes_sync_client_upstream.vhd b/source/serdes_sync_client_upstream.vhd new file mode 100644 index 0000000..d94cde4 --- /dev/null +++ b/source/serdes_sync_client_upstream.vhd @@ -0,0 +1,2698 @@ + + + +--synopsys translate_off + +library pcsd_work; +use pcsd_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSD is +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String := "REFCLK_EXT"; + CH1_CDR_SRC : String := "REFCLK_EXT"; + CH2_CDR_SRC : String := "REFCLK_EXT"; + CH3_CDR_SRC : String := "REFCLK_EXT"; + PLL_SRC : String +-- CONFIG_FILE : String := "serdes_sync_client_upstream.txt"; +-- QUAD_MODE : String := "SINGLE"; +-- CH0_CDR_SRC : String := "REFCLK_CORE"; +-- CH1_CDR_SRC : String := "REFCLK_EXT"; +-- CH2_CDR_SRC : String := "REFCLK_EXT"; +-- CH3_CDR_SRC : String := "REFCLK_CORE"; +-- PLL_SRC : String := "REFCLK_CORE" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); + +end PCSD; + +architecture PCSD_arch of PCSD is + + +component PCSD_sim +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String; + CH1_CDR_SRC : String; + CH2_CDR_SRC : String; + CH3_CDR_SRC : String; + PLL_SRC : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); +end component; + +begin + +PCSD_sim_inst : PCSD_sim +generic map ( + CONFIG_FILE => CONFIG_FILE, + QUAD_MODE => QUAD_MODE, + CH0_CDR_SRC => CH0_CDR_SRC, + CH1_CDR_SRC => CH1_CDR_SRC, + CH2_CDR_SRC => CH2_CDR_SRC, + CH3_CDR_SRC => CH3_CDR_SRC, + PLL_SRC => PLL_SRC + ) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, + FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, + FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, + FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, + FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, + FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, + FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, + FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, + FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, + FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, + FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, + FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, + FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, + FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, + FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, + FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, + FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, + FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, + FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, + LDR_CORE2TX_0 => LDR_CORE2TX_0, + LDR_CORE2TX_1 => LDR_CORE2TX_1, + LDR_CORE2TX_2 => LDR_CORE2TX_2, + LDR_CORE2TX_3 => LDR_CORE2TX_3, + FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, + FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, + FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, + FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, + PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, + PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, + PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, + PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, + PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, + PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, + PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, + PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, + PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, + PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, + PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, + PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, + PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, + PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, + PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, + PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, + PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, + PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, + PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, + PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_TX_F_CLK_0 => FF_TX_F_CLK_0, + FF_TX_F_CLK_1 => FF_TX_F_CLK_1, + FF_TX_F_CLK_2 => FF_TX_F_CLK_2, + FF_TX_F_CLK_3 => FF_TX_F_CLK_3, + FF_TX_H_CLK_0 => FF_TX_H_CLK_0, + FF_TX_H_CLK_1 => FF_TX_H_CLK_1, + FF_TX_H_CLK_2 => FF_TX_H_CLK_2, + FF_TX_H_CLK_3 => FF_TX_H_CLK_3, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, + FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, + FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, + FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RLOS_HI_0 => FFS_RLOS_HI_0, + FFS_RLOS_HI_1 => FFS_RLOS_HI_1, + FFS_RLOS_HI_2 => FFS_RLOS_HI_2, + FFS_RLOS_HI_3 => FFS_RLOS_HI_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, + PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, + PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, + PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, + PCIE_RXVALID_0 => PCIE_RXVALID_0, + PCIE_RXVALID_1 => PCIE_RXVALID_1, + PCIE_RXVALID_2 => PCIE_RXVALID_2, + PCIE_RXVALID_3 => PCIE_RXVALID_3, + FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, + FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, + FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, + FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, + FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, + FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, + FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, + FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, + LDR_RX2CORE_0 => LDR_RX2CORE_0, + LDR_RX2CORE_1 => LDR_RX2CORE_1, + LDR_RX2CORE_2 => LDR_RX2CORE_2, + LDR_RX2CORE_3 => LDR_RX2CORE_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7, + REFCLK_FROM_NQ => REFCLK_FROM_NQ, + REFCLK_TO_NQ => REFCLK_TO_NQ + ); + +end PCSD_arch; + +--synopsys translate_on + + + + +--synopsys translate_off +library ECP3; +use ECP3.components.all; +--synopsys translate_on + + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity serdes_sync_client_upstream is + GENERIC (USER_CONFIG_FILE : String := "serdes_sync_client_upstream.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (7 downto 0); + tx_k_ch0 : in std_logic; + tx_force_disp_ch0 : in std_logic; + tx_disp_sel_ch0 : in std_logic; + rxdata_ch0 : out std_logic_vector (7 downto 0); + rx_k_ch0 : out std_logic; + rx_disp_err_ch0 : out std_logic; + rx_cv_err_ch0 : out std_logic; + rx_serdes_rst_ch0_c : in std_logic; + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pcs_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pcs_rst_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + sci_int : out std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_qd_c : in std_logic; + serdes_rst_qd_c : in std_logic); + +end serdes_sync_client_upstream; + + +architecture serdes_sync_client_upstream_arch of serdes_sync_client_upstream is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; + + + +component PCSD +--synopsys translate_off +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String := "REFCLK_EXT"; + CH1_CDR_SRC : String := "REFCLK_EXT"; + CH2_CDR_SRC : String := "REFCLK_EXT"; + CH3_CDR_SRC : String := "REFCLK_EXT"; + PLL_SRC : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); +end component; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; + attribute QUAD_MODE: string; + attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; + attribute PLL_SRC: string; + attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute CH0_CDR_SRC: string; + attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100.000"; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal refclk_from_nq : std_logic := '0'; +signal fpsc_vlo : std_logic := '0'; +signal fpsc_vhi : std_logic := '1'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); +signal tx_full_clk_ch0_sig : std_logic; + +signal refclk2fpga_sig : std_logic; +signal tx_pll_lol_qd_sig : std_logic; +signal rx_los_low_ch0_sig : std_logic; +signal rx_los_low_ch1_sig : std_logic; +signal rx_los_low_ch2_sig : std_logic; +signal rx_los_low_ch3_sig : std_logic; +signal rx_cdr_lol_ch0_sig : std_logic; +signal rx_cdr_lol_ch1_sig : std_logic; +signal rx_cdr_lol_ch2_sig : std_logic; +signal rx_cdr_lol_ch3_sig : std_logic; + + + + + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); +vhi_inst : VHI port map(Z => fpsc_vhi); + + rx_los_low_ch0_s <= rx_los_low_ch0_sig; + rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; + tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; + tx_full_clk_ch0 <= tx_full_clk_ch0_sig; + +-- pcs_quad instance +PCSD_INST : PCSD +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE, + QUAD_MODE => "SINGLE", + CH0_CDR_SRC => "REFCLK_CORE", + PLL_SRC => "REFCLK_CORE" + ) +--synopsys translate_on +port map ( + REFCLKP => fpsc_vlo, + REFCLKN => fpsc_vlo, + +----- CH0 ----- + HDOUTP0 => hdoutp_ch0, + HDOUTN0 => hdoutn_ch0, + HDINP0 => hdinp_ch0, + HDINN0 => hdinn_ch0, + PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, + PCIE_TXCOMPLIANCE_0 => fpsc_vlo, + PCIE_RXPOLARITY_0 => fpsc_vlo, + PCIE_POWERDOWN_0_0 => fpsc_vlo, + PCIE_POWERDOWN_0_1 => fpsc_vlo, + PCIE_RXVALID_0 => open, + PCIE_PHYSTATUS_0 => open, + SCISELCH0 => sci_sel_ch0, + SCIENCH0 => fpsc_vhi, + FF_RXI_CLK_0 => fpsc_vlo, + FF_TXI_CLK_0 => txiclk_ch0, + FF_EBRD_CLK_0 => fpsc_vlo, + FF_RX_F_CLK_0 => rx_full_clk_ch0, + FF_RX_H_CLK_0 => rx_half_clk_ch0, + FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, + FF_TX_H_CLK_0 => tx_half_clk_ch0, + FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, + FF_TX_D_0_0 => txdata_ch0(0), + FF_TX_D_0_1 => txdata_ch0(1), + FF_TX_D_0_2 => txdata_ch0(2), + FF_TX_D_0_3 => txdata_ch0(3), + FF_TX_D_0_4 => txdata_ch0(4), + FF_TX_D_0_5 => txdata_ch0(5), + FF_TX_D_0_6 => txdata_ch0(6), + FF_TX_D_0_7 => txdata_ch0(7), + FF_TX_D_0_8 => tx_k_ch0, + FF_TX_D_0_9 => tx_force_disp_ch0, + FF_TX_D_0_10 => tx_disp_sel_ch0, + FF_TX_D_0_11 => fpsc_vlo, + FF_TX_D_0_12 => fpsc_vlo, + FF_TX_D_0_13 => fpsc_vlo, + FF_TX_D_0_14 => fpsc_vlo, + FF_TX_D_0_15 => fpsc_vlo, + FF_TX_D_0_16 => fpsc_vlo, + FF_TX_D_0_17 => fpsc_vlo, + FF_TX_D_0_18 => fpsc_vlo, + FF_TX_D_0_19 => fpsc_vlo, + FF_TX_D_0_20 => fpsc_vlo, + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => fpsc_vlo, + FF_TX_D_0_23 => fpsc_vlo, + FF_RX_D_0_0 => rxdata_ch0(0), + FF_RX_D_0_1 => rxdata_ch0(1), + FF_RX_D_0_2 => rxdata_ch0(2), + FF_RX_D_0_3 => rxdata_ch0(3), + FF_RX_D_0_4 => rxdata_ch0(4), + FF_RX_D_0_5 => rxdata_ch0(5), + FF_RX_D_0_6 => rxdata_ch0(6), + FF_RX_D_0_7 => rxdata_ch0(7), + FF_RX_D_0_8 => rx_k_ch0, + FF_RX_D_0_9 => rx_disp_err_ch0, + FF_RX_D_0_10 => rx_cv_err_ch0, + FF_RX_D_0_11 => open, + FF_RX_D_0_12 => open, + FF_RX_D_0_13 => open, + FF_RX_D_0_14 => open, + FF_RX_D_0_15 => open, + FF_RX_D_0_16 => open, + FF_RX_D_0_17 => open, + FF_RX_D_0_18 => open, + FF_RX_D_0_19 => open, + FF_RX_D_0_20 => open, + FF_RX_D_0_21 => open, + FF_RX_D_0_22 => open, + FF_RX_D_0_23 => open, + + FFC_RRST_0 => rx_serdes_rst_ch0_c, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, + FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c, + FFC_TXPWDNB_0 => tx_pwrup_ch0_c, + FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, + FFC_RXPWDNB_0 => rx_pwrup_ch0_c, + FFS_RLOS_LO_0 => rx_los_low_ch0_sig, + FFS_RLOS_HI_0 => open, + FFS_PCIE_CON_0 => open, + FFS_PCIE_DONE_0 => open, + FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, + FFS_CC_OVERRUN_0 => open, + FFS_CC_UNDERRUN_0 => open, + FFS_SKP_ADDED_0 => open, + FFS_SKP_DELETED_0 => open, + FFS_RLOL_0 => rx_cdr_lol_ch0_sig, + FFS_RXFBFIFO_ERROR_0 => open, + FFS_TXFBFIFO_ERROR_0 => open, + LDR_CORE2TX_0 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, + LDR_RX2CORE_0 => open, + FFS_CDR_TRAIN_DONE_0 => open, + FFC_DIV11_MODE_TX_0 => fpsc_vlo, + FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c, + FFC_DIV11_MODE_RX_0 => fpsc_vlo, + FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c, + +----- CH1 ----- + HDOUTP1 => open, + HDOUTN1 => open, + HDINP1 => fpsc_vlo, + HDINN1 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, + PCIE_TXCOMPLIANCE_1 => fpsc_vlo, + PCIE_RXPOLARITY_1 => fpsc_vlo, + PCIE_POWERDOWN_1_0 => fpsc_vlo, + PCIE_POWERDOWN_1_1 => fpsc_vlo, + PCIE_RXVALID_1 => open, + PCIE_PHYSTATUS_1 => open, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => fpsc_vlo, + FF_TXI_CLK_1 => fpsc_vlo, + FF_EBRD_CLK_1 => fpsc_vlo, + FF_RX_F_CLK_1 => open, + FF_RX_H_CLK_1 => open, + FF_TX_F_CLK_1 => open, + FF_TX_H_CLK_1 => open, + FFC_CK_CORE_RX_1 => fpsc_vlo, + FF_TX_D_1_0 => fpsc_vlo, + FF_TX_D_1_1 => fpsc_vlo, + FF_TX_D_1_2 => fpsc_vlo, + FF_TX_D_1_3 => fpsc_vlo, + FF_TX_D_1_4 => fpsc_vlo, + FF_TX_D_1_5 => fpsc_vlo, + FF_TX_D_1_6 => fpsc_vlo, + FF_TX_D_1_7 => fpsc_vlo, + FF_TX_D_1_8 => fpsc_vlo, + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => fpsc_vlo, + FF_TX_D_1_11 => fpsc_vlo, + FF_TX_D_1_12 => fpsc_vlo, + FF_TX_D_1_13 => fpsc_vlo, + FF_TX_D_1_14 => fpsc_vlo, + FF_TX_D_1_15 => fpsc_vlo, + FF_TX_D_1_16 => fpsc_vlo, + FF_TX_D_1_17 => fpsc_vlo, + FF_TX_D_1_18 => fpsc_vlo, + FF_TX_D_1_19 => fpsc_vlo, + FF_TX_D_1_20 => fpsc_vlo, + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => fpsc_vlo, + FF_TX_D_1_23 => fpsc_vlo, + FF_RX_D_1_0 => open, + FF_RX_D_1_1 => open, + FF_RX_D_1_2 => open, + FF_RX_D_1_3 => open, + FF_RX_D_1_4 => open, + FF_RX_D_1_5 => open, + FF_RX_D_1_6 => open, + FF_RX_D_1_7 => open, + FF_RX_D_1_8 => open, + FF_RX_D_1_9 => open, + FF_RX_D_1_10 => open, + FF_RX_D_1_11 => open, + FF_RX_D_1_12 => open, + FF_RX_D_1_13 => open, + FF_RX_D_1_14 => open, + FF_RX_D_1_15 => open, + FF_RX_D_1_16 => open, + FF_RX_D_1_17 => open, + FF_RX_D_1_18 => open, + FF_RX_D_1_19 => open, + FF_RX_D_1_20 => open, + FF_RX_D_1_21 => open, + FF_RX_D_1_22 => open, + FF_RX_D_1_23 => open, + + FFC_RRST_1 => fpsc_vlo, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => fpsc_vlo, + FFC_PFIFO_CLR_1 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => fpsc_vlo, + FFC_TXPWDNB_1 => fpsc_vlo, + FFC_LANE_RX_RST_1 => fpsc_vlo, + FFC_RXPWDNB_1 => fpsc_vlo, + FFS_RLOS_LO_1 => open, + FFS_RLOS_HI_1 => open, + FFS_PCIE_CON_1 => open, + FFS_PCIE_DONE_1 => open, + FFS_LS_SYNC_STATUS_1 => open, + FFS_CC_OVERRUN_1 => open, + FFS_CC_UNDERRUN_1 => open, + FFS_SKP_ADDED_1 => open, + FFS_SKP_DELETED_1 => open, + FFS_RLOL_1 => open, + FFS_RXFBFIFO_ERROR_1 => open, + FFS_TXFBFIFO_ERROR_1 => open, + LDR_CORE2TX_1 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, + LDR_RX2CORE_1 => open, + FFS_CDR_TRAIN_DONE_1 => open, + FFC_DIV11_MODE_TX_1 => fpsc_vlo, + FFC_RATE_MODE_TX_1 => fpsc_vlo, + FFC_DIV11_MODE_RX_1 => fpsc_vlo, + FFC_RATE_MODE_RX_1 => fpsc_vlo, + +----- CH2 ----- + HDOUTP2 => open, + HDOUTN2 => open, + HDINP2 => fpsc_vlo, + HDINN2 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, + PCIE_TXCOMPLIANCE_2 => fpsc_vlo, + PCIE_RXPOLARITY_2 => fpsc_vlo, + PCIE_POWERDOWN_2_0 => fpsc_vlo, + PCIE_POWERDOWN_2_1 => fpsc_vlo, + PCIE_RXVALID_2 => open, + PCIE_PHYSTATUS_2 => open, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => fpsc_vlo, + FF_TXI_CLK_2 => fpsc_vlo, + FF_EBRD_CLK_2 => fpsc_vlo, + FF_RX_F_CLK_2 => open, + FF_RX_H_CLK_2 => open, + FF_TX_F_CLK_2 => open, + FF_TX_H_CLK_2 => open, + FFC_CK_CORE_RX_2 => fpsc_vlo, + FF_TX_D_2_0 => fpsc_vlo, + FF_TX_D_2_1 => fpsc_vlo, + FF_TX_D_2_2 => fpsc_vlo, + FF_TX_D_2_3 => fpsc_vlo, + FF_TX_D_2_4 => fpsc_vlo, + FF_TX_D_2_5 => fpsc_vlo, + FF_TX_D_2_6 => fpsc_vlo, + FF_TX_D_2_7 => fpsc_vlo, + FF_TX_D_2_8 => fpsc_vlo, + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => fpsc_vlo, + FF_TX_D_2_11 => fpsc_vlo, + FF_TX_D_2_12 => fpsc_vlo, + FF_TX_D_2_13 => fpsc_vlo, + FF_TX_D_2_14 => fpsc_vlo, + FF_TX_D_2_15 => fpsc_vlo, + FF_TX_D_2_16 => fpsc_vlo, + FF_TX_D_2_17 => fpsc_vlo, + FF_TX_D_2_18 => fpsc_vlo, + FF_TX_D_2_19 => fpsc_vlo, + FF_TX_D_2_20 => fpsc_vlo, + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => fpsc_vlo, + FF_TX_D_2_23 => fpsc_vlo, + FF_RX_D_2_0 => open, + FF_RX_D_2_1 => open, + FF_RX_D_2_2 => open, + FF_RX_D_2_3 => open, + FF_RX_D_2_4 => open, + FF_RX_D_2_5 => open, + FF_RX_D_2_6 => open, + FF_RX_D_2_7 => open, + FF_RX_D_2_8 => open, + FF_RX_D_2_9 => open, + FF_RX_D_2_10 => open, + FF_RX_D_2_11 => open, + FF_RX_D_2_12 => open, + FF_RX_D_2_13 => open, + FF_RX_D_2_14 => open, + FF_RX_D_2_15 => open, + FF_RX_D_2_16 => open, + FF_RX_D_2_17 => open, + FF_RX_D_2_18 => open, + FF_RX_D_2_19 => open, + FF_RX_D_2_20 => open, + FF_RX_D_2_21 => open, + FF_RX_D_2_22 => open, + FF_RX_D_2_23 => open, + + FFC_RRST_2 => fpsc_vlo, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => fpsc_vlo, + FFC_PFIFO_CLR_2 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => fpsc_vlo, + FFC_TXPWDNB_2 => fpsc_vlo, + FFC_LANE_RX_RST_2 => fpsc_vlo, + FFC_RXPWDNB_2 => fpsc_vlo, + FFS_RLOS_LO_2 => open, + FFS_RLOS_HI_2 => open, + FFS_PCIE_CON_2 => open, + FFS_PCIE_DONE_2 => open, + FFS_LS_SYNC_STATUS_2 => open, + FFS_CC_OVERRUN_2 => open, + FFS_CC_UNDERRUN_2 => open, + FFS_SKP_ADDED_2 => open, + FFS_SKP_DELETED_2 => open, + FFS_RLOL_2 => open, + FFS_RXFBFIFO_ERROR_2 => open, + FFS_TXFBFIFO_ERROR_2 => open, + LDR_CORE2TX_2 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, + LDR_RX2CORE_2 => open, + FFS_CDR_TRAIN_DONE_2 => open, + FFC_DIV11_MODE_TX_2 => fpsc_vlo, + FFC_RATE_MODE_TX_2 => fpsc_vlo, + FFC_DIV11_MODE_RX_2 => fpsc_vlo, + FFC_RATE_MODE_RX_2 => fpsc_vlo, + +----- CH3 ----- + HDOUTP3 => open, + HDOUTN3 => open, + HDINP3 => fpsc_vlo, + HDINN3 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, + PCIE_TXCOMPLIANCE_3 => fpsc_vlo, + PCIE_RXPOLARITY_3 => fpsc_vlo, + PCIE_POWERDOWN_3_0 => fpsc_vlo, + PCIE_POWERDOWN_3_1 => fpsc_vlo, + PCIE_RXVALID_3 => open, + PCIE_PHYSTATUS_3 => open, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => fpsc_vlo, + FF_TXI_CLK_3 => fpsc_vlo, + FF_EBRD_CLK_3 => fpsc_vlo, + FF_RX_F_CLK_3 => open, + FF_RX_H_CLK_3 => open, + FF_TX_F_CLK_3 => open, + FF_TX_H_CLK_3 => open, + FFC_CK_CORE_RX_3 => fpsc_vlo, + FF_TX_D_3_0 => fpsc_vlo, + FF_TX_D_3_1 => fpsc_vlo, + FF_TX_D_3_2 => fpsc_vlo, + FF_TX_D_3_3 => fpsc_vlo, + FF_TX_D_3_4 => fpsc_vlo, + FF_TX_D_3_5 => fpsc_vlo, + FF_TX_D_3_6 => fpsc_vlo, + FF_TX_D_3_7 => fpsc_vlo, + FF_TX_D_3_8 => fpsc_vlo, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => fpsc_vlo, + FF_TX_D_3_11 => fpsc_vlo, + FF_TX_D_3_12 => fpsc_vlo, + FF_TX_D_3_13 => fpsc_vlo, + FF_TX_D_3_14 => fpsc_vlo, + FF_TX_D_3_15 => fpsc_vlo, + FF_TX_D_3_16 => fpsc_vlo, + FF_TX_D_3_17 => fpsc_vlo, + FF_TX_D_3_18 => fpsc_vlo, + FF_TX_D_3_19 => fpsc_vlo, + FF_TX_D_3_20 => fpsc_vlo, + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => fpsc_vlo, + FF_TX_D_3_23 => fpsc_vlo, + FF_RX_D_3_0 => open, + FF_RX_D_3_1 => open, + FF_RX_D_3_2 => open, + FF_RX_D_3_3 => open, + FF_RX_D_3_4 => open, + FF_RX_D_3_5 => open, + FF_RX_D_3_6 => open, + FF_RX_D_3_7 => open, + FF_RX_D_3_8 => open, + FF_RX_D_3_9 => open, + FF_RX_D_3_10 => open, + FF_RX_D_3_11 => open, + FF_RX_D_3_12 => open, + FF_RX_D_3_13 => open, + FF_RX_D_3_14 => open, + FF_RX_D_3_15 => open, + FF_RX_D_3_16 => open, + FF_RX_D_3_17 => open, + FF_RX_D_3_18 => open, + FF_RX_D_3_19 => open, + FF_RX_D_3_20 => open, + FF_RX_D_3_21 => open, + FF_RX_D_3_22 => open, + FF_RX_D_3_23 => open, + + FFC_RRST_3 => fpsc_vlo, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => fpsc_vlo, + FFC_PFIFO_CLR_3 => fpsc_vlo, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => fpsc_vlo, + FFC_TXPWDNB_3 => fpsc_vlo, + FFC_LANE_RX_RST_3 => fpsc_vlo, + FFC_RXPWDNB_3 => fpsc_vlo, + FFS_RLOS_LO_3 => open, + FFS_RLOS_HI_3 => open, + FFS_PCIE_CON_3 => open, + FFS_PCIE_DONE_3 => open, + FFS_LS_SYNC_STATUS_3 => open, + FFS_CC_OVERRUN_3 => open, + FFS_CC_UNDERRUN_3 => open, + FFS_SKP_ADDED_3 => open, + FFS_SKP_DELETED_3 => open, + FFS_RLOL_3 => open, + FFS_RXFBFIFO_ERROR_3 => open, + FFS_TXFBFIFO_ERROR_3 => open, + LDR_CORE2TX_3 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, + LDR_RX2CORE_3 => open, + FFS_CDR_TRAIN_DONE_3 => open, + FFC_DIV11_MODE_TX_3 => fpsc_vlo, + FFC_RATE_MODE_TX_3 => fpsc_vlo, + FFC_DIV11_MODE_RX_3 => fpsc_vlo, + FFC_RATE_MODE_RX_3 => fpsc_vlo, + +----- Auxilliary ---- + SCIWDATA7 => sci_wrdata(7), + SCIWDATA6 => sci_wrdata(6), + SCIWDATA5 => sci_wrdata(5), + SCIWDATA4 => sci_wrdata(4), + SCIWDATA3 => sci_wrdata(3), + SCIWDATA2 => sci_wrdata(2), + SCIWDATA1 => sci_wrdata(1), + SCIWDATA0 => sci_wrdata(0), + SCIADDR5 => sci_addr(5), + SCIADDR4 => sci_addr(4), + SCIADDR3 => sci_addr(3), + SCIADDR2 => sci_addr(2), + SCIADDR1 => sci_addr(1), + SCIADDR0 => sci_addr(0), + SCIRDATA7 => sci_rddata(7), + SCIRDATA6 => sci_rddata(6), + SCIRDATA5 => sci_rddata(5), + SCIRDATA4 => sci_rddata(4), + SCIRDATA3 => sci_rddata(3), + SCIRDATA2 => sci_rddata(2), + SCIRDATA1 => sci_rddata(1), + SCIRDATA0 => sci_rddata(0), + SCIENAUX => fpsc_vhi, + SCISELAUX => sci_sel_quad, + SCIRD => sci_rd, + SCIWSTN => sci_wrn, + CYAWSTN => fpsc_vlo, + SCIINT => sci_int, + FFC_CK_CORE_TX => fpga_txrefclk, + FFC_MACRO_RST => serdes_rst_qd_c, + FFC_QUAD_RST => rst_qd_c, + FFC_TRST => tx_serdes_rst_c, + FFS_PLOL => tx_pll_lol_qd_sig, + FFC_SYNC_TOGGLE => fpsc_vlo, + REFCK2CORE => refclk2fpga_sig, + CIN0 => fpsc_vlo, + CIN1 => fpsc_vlo, + CIN2 => fpsc_vlo, + CIN3 => fpsc_vlo, + CIN4 => fpsc_vlo, + CIN5 => fpsc_vlo, + CIN6 => fpsc_vlo, + CIN7 => fpsc_vlo, + CIN8 => fpsc_vlo, + CIN9 => fpsc_vlo, + CIN10 => fpsc_vlo, + CIN11 => fpsc_vlo, + COUT0 => open, + COUT1 => open, + COUT2 => open, + COUT3 => open, + COUT4 => open, + COUT5 => open, + COUT6 => open, + COUT7 => open, + COUT8 => open, + COUT9 => open, + COUT10 => open, + COUT11 => open, + COUT12 => open, + COUT13 => open, + COUT14 => open, + COUT15 => open, + COUT16 => open, + COUT17 => open, + COUT18 => open, + COUT19 => open, + REFCLK_FROM_NQ => refclk_from_nq, + REFCLK_TO_NQ => open); + + + + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on +end serdes_sync_client_upstream_arch ; diff --git a/source/soda_clockscaler.vhd b/source/soda_clockscaler.vhd new file mode 100644 index 0000000..c39057a --- /dev/null +++ b/source/soda_clockscaler.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use ieee.std_logic_unsigned.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.soda_components.all; + +entity soda_clockscaler is + port( + CLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLOCK_ENABLE_OUT : out std_logic := '0'; + CLOCK_OUT : out std_logic := '0' + ); +end soda_clockscaler; + +architecture Behavioral of soda_clockscaler is + + signal counter_S : std_logic_vector(24 downto 0) := (others => '0'); -- from super-burst-nr-generator + signal clock_out_S : std_logic := '0'; + +begin + + CLOCK_OUT <= clock_out_S; + + pulse_edge_proc : process(CLK) + begin + if rising_edge(CLK) then + if (RESET='1') then + counter_S <= (others => '1'); + CLOCK_ENABLE_OUT <= '0'; + clock_out_S <= '0'; + elsif (counter_S=0) then + counter_S <= (others => '1'); + CLOCK_ENABLE_OUT <= '1'; + clock_out_S <= not(clock_out_S); + else + counter_S <= counter_S - 1; + CLOCK_ENABLE_OUT <= '0'; + end if; + end if; + end process; + + +end Behavioral; diff --git a/source/soda_cmd_handler.vhd b/source/soda_cmd_handler.vhd new file mode 100644 index 0000000..7944824 --- /dev/null +++ b/source/soda_cmd_handler.vhd @@ -0,0 +1,170 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.soda_components.all; + +entity soda_cmd_handler is + port( + SODACLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset +-- CLEAR : in std_logic; -- asynchronous reset +-- CLK_EN : in std_logic; + --Internal Connection + START_OF_SUPERBURST_IN : in std_logic := '0'; + SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); + SODA_CMD_VALID_IN : out std_logic := '0'; + SODA_CMD_WORD_IN : out std_logic_vector(30 downto 0) := (others => '0'); +-- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + CRC_VALID_OUT : out std_logic := '0'; + CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + RX_DLM_IN : in std_logic; + RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') + ); +end soda_cmd_handler; + +architecture Behavioral of soda_cmd_handler is + + signal soda_pkt_word_S : std_logic_vector(31 downto 0) := (others => '0'); + signal soda_pkt_valid_S : std_logic := '0'; + + type packet_state_type is ( c_RST, c_IDLE, c_ERROR, + c_SODA_PKT1, c_SODA_PKT2, c_SODA_PKT3, c_SODA_PKT4, + c_SODA_PKT5, c_SODA_PKT6, c_SODA_PKT7, c_SODA_PKT8 + ); + signal packet_state_S : packet_state_type := c_IDLE; + +begin + + packet_fsm_proc : process(SODACLK) + begin + if rising_edge(SODACLK) then + if (RESET='1') then + packet_state_S <= c_RST; + else + case packet_state_S is + when c_RST => + if (RX_DLM_IN='1') then -- received K28.7 #1 + packet_state_S <= c_SODA_PKT1; + else + packet_state_S <= c_IDLE; + end if; + when c_IDLE => + if (RX_DLM_IN='1') then -- received K28.7 #1 + packet_state_S <= c_SODA_PKT1; + else + packet_state_S <= c_IDLE; + end if; + when c_SODA_PKT1 => + if (RX_DLM_IN='0') then -- possibly received data-byte + packet_state_S <= c_SODA_PKT2; + else + packet_state_S <= c_ERROR; + end if; + when c_SODA_PKT2 => + if (RX_DLM_IN='1') then -- received K28.7 #2 + packet_state_S <= c_SODA_PKT3; + else + packet_state_S <= c_ERROR; + end if; + when c_SODA_PKT3 => + if (RX_DLM_IN='0') then -- possibly received data-byte + packet_state_S <= c_SODA_PKT4; + else + packet_state_S <= c_ERROR; + end if; + when c_SODA_PKT4 => + if (RX_DLM_IN='1') then -- received K28.7 #3 + packet_state_S <= c_SODA_PKT5; + else + packet_state_S <= c_ERROR; + end if; + when c_SODA_PKT5 => + if (RX_DLM_IN='0') then -- possibly received data-byte + packet_state_S <= c_SODA_PKT6; + else + packet_state_S <= c_ERROR; + end if; + when c_SODA_PKT6 => + if (RX_DLM_IN='1') then -- received K28.7 #4 + packet_state_S <= c_SODA_PKT7; + else + packet_state_S <= c_ERROR; + -- else do nothing + end if; + when c_SODA_PKT7 => + if (RX_DLM_IN='1') then + packet_state_S <= c_ERROR; -- if there's an unexpected K28.7 there's too much data + else + packet_state_S <= c_SODA_PKT8; + end if; + when c_SODA_PKT8 => + if (RX_DLM_IN='1') then -- received K28.7 #4+1... must be another packet coming in.... + packet_state_S <= c_SODA_PKT1; + else + packet_state_S <= c_IDLE; + end if; + when c_ERROR => + packet_state_S <= c_IDLE; -- TODO: Insert ERROR_HANDLER + when others => + packet_state_S <= c_IDLE; + end case; + end if; + end if; + end process; + + soda_packet_collector_proc : process(SODACLK, packet_state_S) + begin + if rising_edge(SODACLK) then + case packet_state_S is + when c_RST => + START_OF_SUPERBURST_OUT <= '0'; + SODA_CMD_VALID_OUT <= '0'; + soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= (others=>'0'); + when c_IDLE => + START_OF_SUPERBURST_OUT <= '0'; + SODA_CMD_VALID_OUT <= '0'; + soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= (others=>'0'); + when c_SODA_PKT1 => + START_OF_SUPERBURST_OUT <= '0'; + SODA_CMD_VALID_OUT <= '0'; + soda_pkt_word_S(31 downto 24) <= RX_DLM_WORD_IN; + when c_SODA_PKT2 => + -- do nothing -- disregard K28.7 + when c_SODA_PKT3 => + soda_pkt_word_S(23 downto 16) <= RX_DLM_WORD_IN; + when c_SODA_PKT4 => + -- do nothing -- disregard K28.7 + when c_SODA_PKT5 => + soda_pkt_word_S(15 downto 8) <= RX_DLM_WORD_IN; + when c_SODA_PKT6 => + -- do nothing -- disregard K28.7 + when c_SODA_PKT7 => + soda_pkt_word_S(7 downto 0) <= RX_DLM_WORD_IN; -- get transmitted CRC + when c_SODA_PKT8 => + soda_pkt_valid_S <= '1'; + if (soda_pkt_word_S(31)= '1') then + START_OF_SUPERBURST_OUT <= '1'; + SUPER_BURST_NR_OUT <= soda_pkt_word_S(30 downto 0); + else + SODA_CMD_VALID_OUT <= '1'; + SODA_CMD_WORD_OUT <= soda_pkt_word_S(30 downto 0); + end if; + when others => + START_OF_SUPERBURST_OUT <= '0'; + soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= (others=>'0'); + SODA_CMD_VALID_OUT <= '0'; + SODA_CMD_WORD_OUT <= (others=>'0'); + end case; + + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/source/soda_hub_synconstraints.fdc b/source/soda_hub_synconstraints.fdc new file mode 100644 index 0000000..694b82b --- /dev/null +++ b/source/soda_hub_synconstraints.fdc @@ -0,0 +1,64 @@ +################################################################################ +#### This file contains constraints from Synplicity SDC files that have been +#### translated into Synopsys FPGA Design Constraints (FDC). +#### Translated FDC output file: +#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc +#### client SDC files to the translation: +#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc +################################################################################ + + +###==== BEGIN Header + +# Synopsys, Inc. constraint file +# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc +# Written on Wed Dec 18 11:52:15 2013 +# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor + +# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. +# These sections are generated from SCOPE spreadsheet tabs. + +###==== END Header + + +################################################################################ +#### The following Synplicity constraints from file: +#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc +#### are disabled and have not been translated. +############################################################################## +# FDC constraints translated from Synplify Legacy Timing & Design Constraints +############################################################################## + +set_rtl_ff_names {} +###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) +define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable +define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable +define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable +define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable +###==== END Collections +###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) +create_clock -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} {n:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0} +create_clock -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} +create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} +create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} +create_clock -name {n:trb3_periph_sodahub_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodahub_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5} + + +set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} } +set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} } +#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} } +#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} } +###==== END Clocks +###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) +###==== END "Generated Clocks" +###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) +###==== END Inputs/Outputs +###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +###==== END "Delay Paths" +###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) +###==== END Attributes +###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) +###==== END "I/O Standards" +###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) +###==== END "Compile Points" + diff --git a/source/soda_source_clock_constraints.sdc b/source/soda_source_clock_constraints.sdc new file mode 100644 index 0000000..b224237 --- /dev/null +++ b/source/soda_source_clock_constraints.sdc @@ -0,0 +1,11 @@ +#define_clock {p:CLK_PCLK_LEFT} -freq 200 + +#define_clock {n:gen_200_PLL.THE_MAIN_PLL.CLKOP} -name {n:gen_200_PLL.THE_MAIN_PLL.CLKOP} -freq 100 +#define_clock {n:gen_200_PLL.THE_MAIN_PLL.CLKOK} -name {n:gen_200_PLL.THE_MAIN_PLL.CLKOK} -freq 200 + +# Just to stop the nagging: +define_clock {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -name {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -freq 100 +define_clock {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -name {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -freq 200 + +#define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200.THE_SERDES.rx_half_clk_ch1} -freq 100 +#define_clock {n:clk_raw_internal} -name {nn:clk_raw_internal} -freq 200 diff --git a/source/soda_source_syn_translated.fdc b/source/soda_source_syn_translated.fdc new file mode 100644 index 0000000..e9ff28d --- /dev/null +++ b/source/soda_source_syn_translated.fdc @@ -0,0 +1,66 @@ +################################################################################ +#### This file contains constraints from Synplicity SDC files that have been +#### translated into Synopsys FPGA Design Constraints (FDC). +#### Translated FDC output file: +#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc +#### client SDC files to the translation: +#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc +################################################################################ + + +###==== BEGIN Header + +# Synopsys, Inc. constraint file +# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc +# Written on Wed Dec 18 11:52:15 2013 +# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor + +# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. +# These sections are generated from SCOPE spreadsheet tabs. + +###==== END Header + + +################################################################################ +#### The following Synplicity constraints from file: +#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc +#### are disabled and have not been translated. +############################################################################## +# FDC constraints translated from Synplify Legacy Timing & Design Constraints +############################################################################## + +set_rtl_ff_names {} +###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) +define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable +define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable +define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable +define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable +###==== END Collections +###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) +create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0} +create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} +create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} +create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} +create_clock -name {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5} + + +#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} -period {10.0} -waveform {0 5.0} +#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} -period {5.0} -waveform {0 2.5} +set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} } +set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} } +#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} } +#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} } +###==== END Clocks +###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) +###==== END "Generated Clocks" +###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) +###==== END Inputs/Outputs +###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +###==== END "Delay Paths" +###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) +###==== END Attributes +###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) +###==== END "I/O Standards" +###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) +###==== END "Compile Points" + diff --git a/source/soda_tx_control.vhd b/source/soda_tx_control.vhd new file mode 100644 index 0000000..b36b9bd --- /dev/null +++ b/source/soda_tx_control.vhd @@ -0,0 +1,515 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; +use work.soda_components.all; + +entity soda_tx_control is + port( + CLK_200 : in std_logic; + CLK_100 : in std_logic; + RESET_IN : in std_logic; + + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; + + TX_DATA_OUT : out std_logic_vector( 7 downto 0); + TX_K_OUT : out std_logic; + + REQUEST_RETRANSMIT_IN : in std_logic := '0'; + REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + + START_RETRANSMIT_IN : in std_logic := '0'; + START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM + TX_DLM_PREVIEW_IN : in std_logic := '0'; + SEND_DLM : in std_logic := '0'; + SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0'); + + SEND_LINK_RESET_IN : in std_logic := '0'; + TX_ALLOW_IN : in std_logic := '0'; + RX_ALLOW_IN : in std_logic := '0'; + LINK_PHASE_OUT : out std_logic := '0'; + + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture arch of soda_tx_control is + + + type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H, + SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H, + SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10 + signal current_state : state_t; + + type ram_t is array(0 to 255) of std_logic_vector(17 downto 0); + signal ram : ram_t; + + signal link_phase_S : std_logic := '0'; + + signal ram_write : std_logic := '0'; + signal ram_write_addr : unsigned(7 downto 0) := (others => '0'); + signal ram_read : std_logic := '0'; + signal ram_read_addr : unsigned(7 downto 0) := (others => '0'); + signal ram_dout : std_logic_vector(17 downto 0); + signal next_ram_dout : std_logic_vector(17 downto 0); + signal ram_fill_level : unsigned(7 downto 0); + signal ram_empty : std_logic; + signal ram_afull : std_logic; + + signal request_position_q : std_logic_vector( 7 downto 0); + signal restart_position_q : std_logic_vector( 7 downto 0); + signal request_position_i : std_logic_vector( 7 downto 0); + signal restart_position_i : std_logic_vector( 7 downto 0); + signal make_request_i : std_logic; + signal make_restart_i : std_logic; + signal load_read_pointer_i : std_logic; +-- signal SEND_DLM : std_logic; + signal send_dlm_word_S : std_logic_vector( 7 downto 0); --PL! + signal send_dlm_i : std_logic; + signal start_retransmit_i : std_logic; + signal request_retransmit_i : std_logic; + + signal buf_tx_read_out : std_logic; + signal tx_data_200 : std_logic_vector(17 downto 0); + signal tx_allow_qtx : std_logic; + signal rx_allow_qtx : std_logic; + signal tx_allow_q : std_logic; + signal send_link_reset_qtx : std_logic; + signal ct_fifo_empty : std_logic; + signal ct_fifo_write : std_logic := '0'; + signal ct_fifo_read : std_logic := '0'; + signal ct_fifo_full : std_logic; + signal ct_fifo_afull : std_logic; + signal ct_fifo_reset : std_logic; + signal last_ct_fifo_empty : std_logic; + signal last_ct_fifo_read : std_logic; + signal debug_sending_dlm : std_logic; + + -- gk 05.10.10 + signal save_sop : std_logic; + signal save_eop : std_logic; + signal load_sop : std_logic; + signal load_eop : std_logic; + signal crc_reset : std_logic; + signal crc_q : std_logic_vector(7 downto 0); + signal crc_en : std_logic; + signal crc_data : std_logic_vector(7 downto 0); + +begin + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- +-- gk 05.10.10 + THE_CT_FIFO : lattice_ecp3_fifo_18x16_dualport_oreg + port map( + Data(15 downto 0) => TX_DATA_IN, + Data(16) => save_sop, + Data(17) => save_eop, + WrClock => CLK_100, + RdClock => CLK_200, + WrEn => ct_fifo_write, + RdEn => ct_fifo_read, + Reset => ct_fifo_reset, + RPReset => ct_fifo_reset, + Q(17 downto 0) => tx_data_200, + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => ct_fifo_afull + ); + + THE_RD_PROC : process(CLK_100) + begin + if rising_edge(CLK_100) then + buf_tx_read_out <= tx_allow_q and not ct_fifo_afull ; + end if; + end process; + + ct_fifo_reset <= not tx_allow_qtx; + TX_READ_OUT <= buf_tx_read_out; + + ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN; + ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty; + + last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_200); + last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_200); + + save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0'; + save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0'; + +---------------------------------------------------------------------- +-- RAM +---------------------------------------------------------------------- + + + THE_RAM_WR_PROC : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + ram_write <= '0'; + elsif rising_edge(CLK_200) then + ram_write <= last_ct_fifo_read and not last_ct_fifo_empty; + end if; + end process; + +--RAM + THE_RAM_PROC : process(CLK_200) + begin + if rising_edge(CLK_200) then + if ram_write = '1' then + ram((to_integer(ram_write_addr))) <= tx_data_200; + end if; + next_ram_dout <= ram(to_integer(ram_read_addr)); + ram_dout <= next_ram_dout; + end if; + end process; + +--RAM read pointer + THE_READ_CNT : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + ram_read_addr <= (others => '0'); + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + ram_read_addr <= (others => '0'); + elsif load_read_pointer_i = '1' then + ram_read_addr <= unsigned(restart_position_i); + elsif ram_read = '1' then + ram_read_addr <= ram_read_addr + to_unsigned(1,1); + end if; + end if; + end process; + +--RAM write pointer + THE_WRITE_CNT : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + ram_write_addr <= (others => '0'); + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + ram_write_addr <= (others => '0'); + elsif ram_write = '1' then + ram_write_addr <= ram_write_addr + to_unsigned(1,1); + end if; + end if; + end process; + + +--RAM fill level counter + THE_FILL_CNT : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + ram_fill_level <= (others => '0'); + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + ram_fill_level <= (others => '0'); + else + ram_fill_level <= ram_write_addr - ram_read_addr; + end if; + end if; + end process; + + +--RAM empty +-- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN; + ram_empty <= '1' when (ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0'; + ram_afull <= '1' when ram_fill_level >= 4 else '0'; + + + +---------------------------------------------------------------------- +-- TX control state machine +---------------------------------------------------------------------- + + THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN) + begin + if rising_edge(CLK_200) then + TX_K_OUT <= '0'; + debug_sending_dlm <= '0'; + case current_state is + when SEND_IDLE_L => + TX_DATA_OUT <= K_IDLE; + TX_K_OUT <= '1'; + current_state <= SEND_IDLE_H; + + when SEND_IDLE_H => + if rx_allow_qtx = '1' then + TX_DATA_OUT <= D_IDLE1; + else + TX_DATA_OUT <= D_IDLE0; + end if; + + when SEND_DATA_L => + TX_DATA_OUT <= ram_dout(7 downto 0); + load_sop <= ram_dout(16); + load_eop <= ram_dout(17); + current_state <= SEND_DATA_H; + + when SEND_DATA_H => + TX_DATA_OUT <= ram_dout(15 downto 8); + + when SEND_CHKSUM_L => + TX_DATA_OUT <= K_EOP; + TX_K_OUT <= '1'; + load_sop <= '0'; + load_eop <= '0'; + current_state <= SEND_CHKSUM_H; + + when SEND_CHKSUM_H => + TX_DATA_OUT <= crc_q; + + when SEND_START_L => + TX_DATA_OUT <= K_BGN; + TX_K_OUT <= '1'; + current_state <= SEND_START_H; + + when SEND_START_H => + TX_DATA_OUT <= std_logic_vector(ram_read_addr); + + when SEND_REQUEST_L => + TX_DATA_OUT <= K_REQ; + TX_K_OUT <= '1'; + current_state <= SEND_REQUEST_H; + + when SEND_DLM_L => + TX_DATA_OUT <= K_DLM; + TX_K_OUT <= '1'; + current_state <= SEND_DLM_H; + debug_sending_dlm <= '1'; + send_dlm_word_S <= SEND_DLM_WORD; --PL! + + when SEND_DLM_H => + TX_DATA_OUT <= send_dlm_word_S; --SEND_DLM_WORD; + debug_sending_dlm <= '1'; + + when SEND_REQUEST_H => + TX_DATA_OUT <= request_position_i; + + when SEND_RESET => + TX_DATA_OUT <= K_RST; + TX_K_OUT <= '1'; + if send_link_reset_qtx = '0' then + current_state <= SEND_IDLE_L; + end if; + + when others => + current_state <= SEND_IDLE_L; + end case; + + if current_state = SEND_START_H or current_state = SEND_IDLE_H or + current_state = SEND_DATA_H or current_state = SEND_DLM_H or + current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H + then + link_phase_S <= c_PHASE_L; + if tx_allow_qtx = '0' then + current_state <= SEND_IDLE_L; + elsif send_link_reset_qtx = '1' then + current_state <= SEND_RESET; + elsif make_request_i = '1' then + current_state <= SEND_REQUEST_L; + elsif make_restart_i = '1' then + current_state <= SEND_START_L; + -- elsif send_dlm_i = '1' then + elsif (TX_DLM_PREVIEW_IN='1') then --PL! + current_state <= SEND_DLM_L; + elsif ram_empty = '0' then + current_state <= SEND_DATA_L; + else + current_state <= SEND_IDLE_L; + end if; + else + link_phase_S <= c_PHASE_H; + end if; + end if; +-------------------------- +--async because of oreg.-- +-------------------------- + if (current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or + current_state = SEND_DLM_H or current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H) and + ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0' and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' then + ram_read <= '1'; + else + ram_read <= '0'; + end if; + + if RESET_IN = '1' then + ram_read <= '0'; + end if; +end process; + +LINK_PHASE_OUT <= link_phase_S; +---------------------------------------------------------------------- +-- +---------------------------------------------------------------------- + +tx_allow_qtx <= TX_ALLOW_IN when rising_edge(CLK_200); +rx_allow_qtx <= RX_ALLOW_IN when rising_edge(CLK_200); + +send_link_reset_qtx <= SEND_LINK_RESET_IN when rising_edge(CLK_200); +tx_allow_q <= tx_allow_qtx when rising_edge(CLK_100); + + THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync + port map( + CLK_A_IN => CLK_100, + RESET_A_IN => RESET_IN, + PULSE_A_IN => REQUEST_RETRANSMIT_IN, + CLK_B_IN => CLK_200, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => request_retransmit_i + ); + + THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync + port map( + CLK_A_IN => CLK_100, + RESET_A_IN => RESET_IN, + PULSE_A_IN => START_RETRANSMIT_IN, + CLK_B_IN => CLK_200, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => start_retransmit_i + ); + +-- THE_RETRANSMIT_PULSE_SYNC_3 : pulse_sync +-- port map( +-- CLK_A_IN => CLK_100, +-- RESET_A_IN => RESET_IN, +-- PULSE_A_IN => SEND_DLM, +-- CLK_B_IN => CLK_200, +-- RESET_B_IN => RESET_IN, +-- PULSE_B_OUT => SEND_DLM +-- ); +-- SEND_DLM <= SEND_DLM; + + THE_POSITION_REG : process(CLK_100) + begin + if rising_edge(CLK_100) then + if REQUEST_RETRANSMIT_IN = '1' then + request_position_q <= REQUEST_POSITION_IN; + end if; + if START_RETRANSMIT_IN = '1' then + restart_position_q <= START_POSITION_IN; + end if; + end if; + end process; + + +--Store Request Retransmit position + THE_STORE_REQUEST_PROC : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + make_request_i <= '0'; + request_position_i <= (others => '0'); + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + make_request_i <= '0'; + request_position_i <= (others => '0'); + elsif request_retransmit_i = '1' then + make_request_i <= '1'; + request_position_i <= request_position_q; + elsif current_state = SEND_REQUEST_L then + make_request_i <= '0'; + elsif current_state = SEND_REQUEST_H then + request_position_i <= (others => '0'); + end if; + end if; + end process; + + +--Store Restart position + THE_STORE_RESTART_PROC : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + make_restart_i <= '0'; + restart_position_i <= (others => '0'); + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + make_restart_i <= '0'; + restart_position_i <= (others => '0'); + elsif start_retransmit_i = '1' then + make_restart_i <= '1'; + restart_position_i <= restart_position_q; + elsif current_state = SEND_START_L then + make_restart_i <= '0'; + elsif current_state = SEND_START_H then + restart_position_i <= (others => '0'); + end if; + end if; + end process; + +--Store DLM position + THE_STORE_DLM_PROC : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + send_dlm_i <= '0'; + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + send_dlm_i <= '0'; + elsif SEND_DLM = '1' then + send_dlm_i <= '1'; +-- elsif current_state = SEND_DLM_L then -- PL! + else + send_dlm_i <= '0'; + end if; + end if; + end process; + + load_read_pointer_i <= '1' when current_state = SEND_START_L else '0'; + + -- gk 05.10.10 + crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0'; + crc_en <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0'; + crc_data <= ram_dout(15 downto 8) when (current_state = SEND_DATA_H) else ram_dout(7 downto 0); + + -- gk 05.10.10 + CRC_CALC : trb_net_CRC8 + port map( + CLK => CLK_200, + RESET => crc_reset, + CLK_EN => crc_en, + DATA_IN => crc_data, + CRC_OUT => crc_q, + CRC_match => open + ); + + +---------------------------------------------------------------------- +-- Debug +---------------------------------------------------------------------- + DEBUG_OUT(0) <= ram_read; + DEBUG_OUT(1) <= ct_fifo_write; + DEBUG_OUT(2) <= ct_fifo_read; + DEBUG_OUT(3) <= tx_allow_qtx; + DEBUG_OUT(4) <= ram_empty; + DEBUG_OUT(5) <= ram_afull; + DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200); + DEBUG_OUT(31 downto 7) <= (others => '0'); + + process(CLK_100) + begin + if rising_edge(CLK_100) then + STAT_REG_OUT(7 downto 0) <= std_logic_vector(ram_fill_level); + STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr); + STAT_REG_OUT(16) <= ram_afull; + STAT_REG_OUT(17) <= ram_empty; + STAT_REG_OUT(18) <= tx_allow_qtx; + STAT_REG_OUT(19) <= TX_ALLOW_IN; + STAT_REG_OUT(20) <= make_restart_i; + STAT_REG_OUT(21) <= make_request_i; + STAT_REG_OUT(22) <= load_eop; + STAT_REG_OUT(31 downto 23) <= (others => '0'); + end if; + end process; + + + + +end architecture; \ No newline at end of file diff --git a/source/trb3_periph_sodahub.vhd b/source/trb3_periph_sodahub.vhd new file mode 100644 index 0000000..2ccab92 --- /dev/null +++ b/source/trb3_periph_sodahub.vhd @@ -0,0 +1,784 @@ +--------------- +-- TOP LEVEL -- +--------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.trb3_components.all; +use work.soda_components.all; +use work.med_sync_define.all; +use work.version.all; + +entity trb3_periph_sodahub is + generic( + SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests! + USE_125_MHZ : integer := c_NO; + CLOCK_FREQUENCY : integer := 100; + NUM_INTERFACES : integer := 6 + 1 -- This is the number of SERDES's in use: 1 copper trb-upstream + 6 to ADDONboard + ); + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + + + --serdes I/O - connect as you like, no real use + SERDES_ADDON_TX : out std_logic_vector(15 downto 0); + SERDES_ADDON_RX : in std_logic_vector(15 downto 0); + + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --others yet undefined + --Connection to AddOn + LED_LINKOK : out std_logic_vector(6 downto 1); + LED_RX : out std_logic_vector(6 downto 1); + LED_TX : out std_logic_vector(6 downto 1); + SFP_MOD0 : in std_logic_vector(6 downto 1); + SFP_TXDIS : out std_logic_vector(6 downto 1); + SFP_LOS : in std_logic_vector(6 downto 1); + SFP_MOD1 : inout std_logic_vector(6 downto 1); --H! + SFP_MOD2 : inout std_logic_vector(6 downto 1); --H! + --SFP_RATESEL : out std_logic_vector(6 downto 1); + --SFP_TXFAULT : in std_logic_vector(6 downto 1); + + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); +end entity trb3_periph_sodahub; + + +architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 2; --0; H! + constant REGIO_NUM_CTRL_REGS : integer := 2; + + + constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa + + --Clock / Reset + -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + signal clk_sys_internal : std_logic; + signal clk_raw_internal : std_logic; + signal clk_tdc : std_logic; + signal time_counter, time_counter2 : unsigned(31 downto 0); + --Media Interface + signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); + signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); + signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0'); + signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0'); + signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); + signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0'); + signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); + signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); + signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); + signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0'); + signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); + signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal my_address : std_logic_vector (15 downto 0); + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(8 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_dataready_out : std_logic; + signal spimem_no_more_data_out : std_logic; + signal spimem_unknown_addr_out : std_logic; + signal spimem_write_ack_out : std_logic; + + --media interface + signal sci1_ack : std_logic; + signal sci1_write : std_logic; + signal sci1_read : std_logic; + signal sci1_data_in : std_logic_vector(7 downto 0); + signal sci1_data_out : std_logic_vector(7 downto 0); + signal sci1_addr : std_logic_vector(8 downto 0); + signal sci1_nack : std_logic; + + signal sci2_ack : std_logic; + signal sci2_nack : std_logic; + signal sci2_write : std_logic; + signal sci2_read : std_logic; + signal sci2_data_in : std_logic_vector(7 downto 0); + signal sci2_data_out : std_logic_vector(7 downto 0); + signal sci2_addr : std_logic_vector(8 downto 0); + + signal sfp_mod0_B : t_QUAD_BIT := (others => '0'); + signal sfp_los_B : t_QUAD_BIT := (others => '0'); + signal sfp_txdis_B : t_QUAD_BIT := (others => '0'); + + + --SODA +-- signal soda_rxup_clock_half : std_logic; + signal soda_rxup_clock_full : std_logic; +-- signal soda_rxdn_clock_half : t_HUB_BIT; + signal soda_rxdn_clock_full : t_HUB_BIT; + signal make_reset : std_logic; + + --SODA uplink + signal txup_dlm_i : std_logic; + signal rxup_dlm_i : std_logic; + signal txup_dlm_word : std_logic_vector(7 downto 0); + signal rxup_dlm_word : std_logic_vector(7 downto 0); + signal txup_dlm_preview_S : std_logic; --PL! + signal uplink_phase_S : std_logic; --PL! + signal uplink_disable_S : std_logic; + + --SODA downlink + signal txdn_dlm_i : t_HUB_BIT; + signal rxdn_dlm_i : t_HUB_BIT; + signal txdn_dlm_word : t_HUB_BYTE; + signal rxdn_dlm_word : t_HUB_BYTE; + signal txdn_dlm_preview_S : t_HUB_BIT; --PL! + signal dnlink_phase_S : t_HUB_BIT; --PL! + + -- SODA slow controll + signal soda_ack : std_logic; +-- signal soda_nack : std_logic; + signal soda_write : std_logic; + signal soda_read : std_logic; + signal soda_data_in : std_logic_vector(31 downto 0); + signal soda_data_out : std_logic_vector(31 downto 0); + signal soda_addr : std_logic_vector(3 downto 0); + signal soda_leds : std_logic_vector(3 downto 0); + + signal link_debug_in_S : std_logic_vector(31 downto 0); + signal general_reset_i : std_logic := '1'; + + signal soda_counter_i : unsigned(3 downto 0); + +-- attribute syn_useioff : boolean; +-- --no IO-FF for LEDs relaxes timing constraints +-- attribute syn_useioff of LED_GREEN : signal is false; +-- attribute syn_useioff of LED_ORANGE : signal is false; +-- attribute syn_useioff of LED_RED : signal is false; +-- attribute syn_useioff of LED_YELLOW : signal is false; +-- attribute syn_useioff of TEMPSENS : signal is false; +-- attribute syn_useioff of PROGRAMN : signal is false; +-- attribute syn_useioff of CODE_LINE : signal is false; +-- attribute syn_useioff of LED_LINKOK : signal is false; +-- attribute syn_useioff of LED_TX : signal is false; +-- attribute syn_useioff of LED_RX : signal is false; +-- attribute syn_useioff of SFP_MOD0 : signal is false; +-- attribute syn_useioff of SFP_TXDIS : signal is false; +-- attribute syn_useioff of SFP_LOS : signal is false; +-- attribute syn_useioff of TEST_LINE : signal is false; --H! + +-- --important signals _with_ IO-FF +-- attribute syn_useioff of FLASH_CLK : signal is true; +-- attribute syn_useioff of FLASH_CS : signal is true; +-- attribute syn_useioff of FLASH_DIN : signal is true; +-- attribute syn_useioff of FLASH_DOUT : signal is true; +-- attribute syn_useioff of FPGA5_COMM : signal is true; + + attribute syn_keep of soda_counter_i : signal is true; + -- fix signal names for constraining + attribute syn_preserve of soda_rxup_clock_full : signal is true; + attribute syn_keep of soda_rxup_clock_full : signal is true; + + attribute syn_preserve of clk_sys_internal : signal is true; + attribute syn_keep of clk_sys_internal : signal is true; + attribute syn_preserve of clk_raw_internal : signal is true; + attribute syn_keep of clk_raw_internal : signal is true; + attribute syn_preserve of clk_soda_i : signal is true; + attribute syn_keep of clk_soda_i : signal is true; + attribute syn_preserve of txup_dlm_i : signal is true; + attribute syn_keep of txup_dlm_i : signal is true; + attribute syn_preserve of rxup_dlm_i : signal is true; + attribute syn_keep of rxup_dlm_i : signal is true; + attribute syn_preserve of txdn_dlm_i : signal is true; + attribute syn_keep of txdn_dlm_i : signal is true; + attribute syn_preserve of rxdn_dlm_i : signal is true; + attribute syn_keep of rxdn_dlm_i : signal is true; + + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + + TEST_LINE <= (others => '0'); -- otherwise it is floating + LED_RX <= (others => '0'); -- otherwise it is floating + LED_TX <= (others => '0'); -- otherwise it is floating + LED_LINKOK <= (others => '0'); -- otherwise it is floating + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + process(clk_sys_internal) + begin + if rising_edge(clk_sys_internal) then + general_reset_i <= not SFP_LOS(1); + end if; + end process; + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- +gen_200_PLL : if USE_125_MHZ = c_NO generate + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_sys_internal, + CLKOK => clk_raw_internal, + LOCK => pll_lock + ); +end generate; + +gen_125 : if USE_125_MHZ = c_YES generate + clk_sys_internal <= CLK_GPLL_LEFT; + clk_raw_internal <= CLK_GPLL_LEFT; +end generate; + +gen_sync_clocks : if SYNC_MODE = c_YES generate + clk_soda_i <= soda_rxup_clock_full; +end generate; + +gen_local_clocks : if SYNC_MODE = c_NO generate + clk_soda_i <= clk_raw_internal; +end generate; + + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0) + ) + port map( + CLK => clk_sys_internal, --clk_sys_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + BUS_READ_ENABLE_OUT(0) => spimem_read_en, + BUS_READ_ENABLE_OUT(1) => sci1_read, + BUS_READ_ENABLE_OUT(2) => sci2_read, + BUS_READ_ENABLE_OUT(3) => soda_read, + + BUS_WRITE_ENABLE_OUT(0) => spimem_write_en, + BUS_WRITE_ENABLE_OUT(1) => sci1_write, + BUS_WRITE_ENABLE_OUT(2) => sci2_write, + BUS_WRITE_ENABLE_OUT(3) => soda_write, + + BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in, + BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in, + BUS_DATA_OUT(1*32+31 downto 1*32+8) => open, + BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in, + BUS_DATA_OUT(2*32+31 downto 2*32+8) => open, + BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in, + + BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open, + BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open, + BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open, + BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open, + + BUS_TIMEOUT_OUT(0) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_TIMEOUT_OUT(3) => open, + + BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out, + BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out, + BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'), + BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out, + BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'), + BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out, + + BUS_DATAREADY_IN(0) => spimem_dataready_out, + BUS_DATAREADY_IN(1) => sci1_ack, + BUS_DATAREADY_IN(2) => sci2_ack, + BUS_DATAREADY_IN(3) => soda_ack, + + BUS_WRITE_ACK_IN(0) => spimem_write_ack_out, + BUS_WRITE_ACK_IN(1) => sci1_ack, + BUS_WRITE_ACK_IN(2) => sci2_ack, + BUS_WRITE_ACK_IN(3) => soda_ack, + + BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_NO_MORE_DATA_IN(2) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + + BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out, + BUS_UNKNOWN_ADDR_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(2) => sci2_nack, + BUS_UNKNOWN_ADDR_IN(3) => '0', + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + +THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch + port map( + CLK_IN => clk_sys_internal, --clk_sys_i, + RESET_IN => reset_i, + + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_DATAREADY_OUT => spimem_dataready_out, + BUS_WRITE_ACK_OUT => spimem_write_ack_out, + BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out, + BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + + DO_REBOOT_IN => common_ctrl_reg(15), + PROGRAMN => PROGRAMN, + + SPI_CS_OUT => FLASH_CS, + SPI_SCK_OUT => FLASH_CLK, + SPI_SDO_OUT => FLASH_DIN, + SPI_SDI_IN => FLASH_DOUT + ); + + + +--------------------------------------------------------------------------- +-- The synchronous interface for Soda tests +--------------------------------------------------------------------------- + +THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up + generic map( + SERDES_NUM => 0, --number of serdes in quad + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK => clk_raw_internal, --clk_200_i, + SYSCLK => clk_sys_internal, --clk_sys_i, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection for TrbNet data -> not used a.t.m. + MED_DATA_IN => med_data_out(15 downto 0), + MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(15 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + CLK_RX_HALF_OUT => open, --soda_rxup_clock_half, + CLK_RX_FULL_OUT => soda_rxup_clock_full, + + RX_DLM => rxup_dlm_i, + RX_DLM_WORD => rxup_dlm_word, + TX_DLM => txup_dlm_i, + TX_DLM_WORD => txup_dlm_word, + TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL! + LINK_PHASE_OUT => uplink_phase_S, --PL! + --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting + SD_RXD_P_IN => SERDES_ADDON_RX(8), + SD_RXD_N_IN => SERDES_ADDON_RX(9), + SD_TXD_P_OUT => SERDES_ADDON_TX(8), + SD_TXD_N_OUT => SERDES_ADDON_TX(9), + SD_REFCLK_P_IN => '0', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => SFP_MOD0(3), -- = A3, was 1 = B0 + SD_LOS_IN => SFP_LOS(3), + SD_TXDIS_OUT => uplink_disable_S, --SFP_TXDIS(3), this signal is now used to release downlinks + + SCI_DATA_IN => sci1_data_in, + SCI_DATA_OUT => sci1_data_out, + SCI_ADDR => sci1_addr, + SCI_READ => sci1_read, + SCI_WRITE => sci1_write, + SCI_ACK => sci1_ack, + SCI_NACK => sci1_nack, + -- Status and control port + STAT_OP => med_stat_op(15 downto 0), + CTRL_OP => med_ctrl_op(15 downto 0), + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + SFP_TXDIS(3) <= uplink_disable_S; + +--------------------------------------------------------------------------- +-- The Soda Central +--------------------------------------------------------------------------- + + A_SODA_HUB : soda_hub + port map( + SYSCLK => clk_sys_internal, --clk_sys_i, + SODACLK => clk_soda_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + + -- SINGLE DUBPLEX UP-LINK TO THE TOP + RXUP_DLM_WORD_IN => rxup_dlm_word, + RXUP_DLM_IN => rxup_dlm_i, + TXUP_DLM_OUT => txup_dlm_i, + TXUP_DLM_WORD_OUT => txup_dlm_word, + TXUP_DLM_PREVIEW_OUT => txup_dlm_preview_S, + UPLINK_PHASE_IN => uplink_phase_S, + -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM + RXDN_DLM_WORD_IN => rxdn_dlm_word, + RXDN_DLM_IN => rxdn_dlm_i, + TXDN_DLM_OUT => txdn_dlm_i, + TXDN_DLM_WORD_OUT => txdn_dlm_word, + TXDN_DLM_PREVIEW_OUT => txdn_dlm_preview_S, + DNLINK_PHASE_IN => dnlink_phase_S, + + SODA_DATA_IN => soda_data_in, + SODA_DATA_OUT => soda_data_out, + SODA_ADDR_IN => soda_addr, + SODA_READ_IN => soda_read, + SODA_WRITE_IN => soda_write, + SODA_ACK_OUT => soda_ack, + LEDS_OUT => soda_leds, + LINK_DEBUG_IN => link_debug_in_S + ); + + + + + + THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down + generic map( + SERDES_NUM => 0, --number of serdes in quad + IS_SYNC_SLAVE => c_NO + ) + port map( + CLK => clk_soda_i, --clk_raw_internal, --clk_200_i, + SYSCLK => clk_sys_internal, --clk_sys_i, + RESET => reset_i, + CLEAR => clear_i, + --------------------------------------------------------------------------------------------------------------------------------------------------------- + LINK_DISABLE_IN => uplink_disable_S,-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. + --------------------------------------------------------------------------------------------------------------------------------------------------------- +-- MED_DATA_IN(0*16+15 downto 0*16) => med_data_out(1*16+15 downto 1*16), + MED_DATA_IN(0) => med_data_out(1*16+15 downto 1*16), + MED_DATA_IN(1) => med_data_out(6*16+15 downto 6*16), + MED_DATA_IN(2) => med_data_out(4*16+15 downto 4*16), + MED_DATA_IN(3) => med_data_out(2*16+15 downto 2*16), + +-- MED_PACKET_NUM_IN(0*3+2 downto 0*3) => med_packet_num_out(1*3+2 downto 1*3), + MED_PACKET_NUM_IN(0) => med_packet_num_out(1*3+2 downto 1*3), + MED_PACKET_NUM_IN(1) => med_packet_num_out(6*3+2 downto 6*3), + MED_PACKET_NUM_IN(2) => med_packet_num_out(2*3+2 downto 2*3), + MED_PACKET_NUM_IN(3) => med_packet_num_out(4*3+2 downto 4*3), + + MED_DATAREADY_IN(0) => med_dataready_out(1), + MED_DATAREADY_IN(1) => med_dataready_out(6), + MED_DATAREADY_IN(2) => med_dataready_out(2), + MED_DATAREADY_IN(3) => med_dataready_out(4), + + MED_READ_OUT(0) => med_read_in(1), + MED_READ_OUT(1) => med_read_in(6), + MED_READ_OUT(2) => med_read_in(2), + MED_READ_OUT(3) => med_read_in(4), + +-- MED_DATA_OUT(0*16+15 downto 0*16) => med_data_in(1*16+15 downto 1*16), + MED_DATA_OUT(0) => med_data_in(1*16+15 downto 1*16), + MED_DATA_OUT(1) => med_data_in(6*16+15 downto 6*16), + MED_DATA_OUT(2) => med_data_in(2*16+15 downto 2*16), + MED_DATA_OUT(3) => med_data_in(4*16+15 downto 4*16), + +-- MED_PACKET_NUM_OUT(0*3+2 downto 0*3) => med_packet_num_in(1*3+2 downto 1*3), + MED_PACKET_NUM_OUT(0) => med_packet_num_in(1*3+2 downto 1*3), + MED_PACKET_NUM_OUT(1) => med_packet_num_in(6*3+2 downto 6*3), + MED_PACKET_NUM_OUT(2) => med_packet_num_in(2*3+2 downto 2*3), + MED_PACKET_NUM_OUT(3) => med_packet_num_in(4*3+2 downto 4*3), + + MED_DATAREADY_OUT(0) => med_dataready_in(1), + MED_DATAREADY_OUT(1) => med_dataready_in(6), + MED_DATAREADY_OUT(2) => med_dataready_in(2), + MED_DATAREADY_OUT(3) => med_dataready_in(4), + + MED_READ_IN(0) => med_read_out(1), + MED_READ_IN(1) => med_read_out(6), + MED_READ_IN(2) => med_read_out(2), + MED_READ_IN(3) => med_read_out(4), + + CLK_RX_FULL_OUT(0) => soda_rxdn_clock_full(0), -- needed for sync replies i.e. calibration + CLK_RX_FULL_OUT(1) => soda_rxdn_clock_full(1), -- needed for sync replies i.e. calibration + CLK_RX_FULL_OUT(2) => soda_rxdn_clock_full(2), -- needed for sync replies i.e. calibration + CLK_RX_FULL_OUT(3) => soda_rxdn_clock_full(3), -- needed for sync replies i.e. calibration + + RX_DLM(0) => rxdn_dlm_i(0), + RX_DLM(1) => rxdn_dlm_i(1), + RX_DLM(2) => rxdn_dlm_i(2), + RX_DLM(3) => rxdn_dlm_i(3), + +-- RX_DLM_WORD(0*8+7 downto 0*8) => rxdn_dlm_word(1), + RX_DLM_WORD(0) => rxdn_dlm_word(0), + RX_DLM_WORD(1) => rxdn_dlm_word(1), + RX_DLM_WORD(2) => rxdn_dlm_word(2), + RX_DLM_WORD(3) => rxdn_dlm_word(3), + + TX_DLM(0) => txdn_dlm_i(0), + TX_DLM(1) => txdn_dlm_i(1), + TX_DLM(2) => txdn_dlm_i(2), + TX_DLM(3) => txdn_dlm_i(3), + +-- TX_DLM_WORD(0*8+7 downto 0*8) => txdn_dlm_word(1), + TX_DLM_WORD(0) => txdn_dlm_word(0), + TX_DLM_WORD(1) => txdn_dlm_word(1), + TX_DLM_WORD(2) => txdn_dlm_word(2), + TX_DLM_WORD(3) => txdn_dlm_word(3), + + TX_DLM_PREVIEW_IN(0) => txdn_dlm_preview_S(0), --PL! + TX_DLM_PREVIEW_IN(1) => txdn_dlm_preview_S(1), --PL! + TX_DLM_PREVIEW_IN(2) => txdn_dlm_preview_S(2), --PL! + TX_DLM_PREVIEW_IN(3) => txdn_dlm_preview_S(3), --PL! + + LINK_PHASE_OUT(0) => dnlink_phase_S(0), --PL! + LINK_PHASE_OUT(1) => dnlink_phase_S(1), --PL! + LINK_PHASE_OUT(2) => dnlink_phase_S(2), --PL! + LINK_PHASE_OUT(3) => dnlink_phase_S(3), --PL! + + --SFP Connection + SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0 + SD_RXD_P_IN(1) => SERDES_ADDON_RX(1), + SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1 + SD_RXD_P_IN(3) => SERDES_ADDON_RX(11), + SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2 + SD_RXD_N_IN(1) => SERDES_ADDON_RX(3), + SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3 + SD_RXD_N_IN(3) => SERDES_ADDON_RX(7), + SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0 + SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1), + SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1 + SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11), + SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2 + SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3), + SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3 + SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7), + SD_REFCLK_P_IN => (others => '0'), + SD_REFCLK_N_IN => ('0','0','0','0'), + SD_PRSNT_N_IN(0) => SFP_MOD0(1), + SD_PRSNT_N_IN(1) => SFP_MOD0(6), + SD_PRSNT_N_IN(2) => SFP_MOD0(2), + SD_PRSNT_N_IN(3) => SFP_MOD0(4), + SD_LOS_IN(0) => SFP_LOS(1), + SD_LOS_IN(1) => SFP_LOS(6), + SD_LOS_IN(2) => SFP_LOS(2), + SD_LOS_IN(3) => SFP_LOS(4), + SD_TXDIS_OUT(0) => SFP_TXDIS(1), + SD_TXDIS_OUT(1) => SFP_TXDIS(6), + SD_TXDIS_OUT(2) => SFP_TXDIS(2), + SD_TXDIS_OUT(3) => SFP_TXDIS(4), + + SCI_DATA_IN => sci2_data_in, + SCI_DATA_OUT => sci2_data_out, + SCI_ADDR => sci2_addr, + SCI_READ => sci2_read, + SCI_WRITE => sci2_write, + SCI_ACK => sci2_ack, + SCI_NACK => sci2_nack, + + --Status and control port +-- STAT_OP(0*16+15 downto 0*16) => med_stat_op(1*16+15 downto 1*16), + STAT_OP(0) => med_stat_op(1*16+15 downto 1*16), + STAT_OP(1) => med_stat_op(6*16+15 downto 6*16), + STAT_OP(2) => med_stat_op(2*16+15 downto 2*16), + STAT_OP(3) => med_stat_op(4*16+15 downto 4*16), + +-- CTRL_OP(0*16+15 downto 0*16) => med_ctrl_op(1*16+15 downto 1*16), + CTRL_OP(0) => med_ctrl_op(1*16+15 downto 1*16), + CTRL_OP(1) => med_ctrl_op(6*16+15 downto 6*16), + CTRL_OP(2) => med_ctrl_op(2*16+15 downto 2*16), + CTRL_OP(3) => med_ctrl_op(4*16+15 downto 4*16), + + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + +--------------------------------------------------------------------------- +-- TRB-Hub +--------------------------------------------------------------------------- + + TRB_HUB : trb_net16_hub_base + generic map ( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + MII_NUMBER => 7, + MII_IS_UPLINK => (0 => 1, others => 0), + MII_IS_DOWNLINK => (0 => 0, others => 1), + MII_IS_UPLINK_ONLY => (0 => 1, others => 0), + INT_NUMBER => 0, + -- INT_CHANNELS => (0,1,3,3,3,3,3,3), + USE_ONEWIRE => c_YES, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + HARDWARE_VERSION => x"91003200", + INIT_ENDPOINT_ID => x"0000", + INIT_ADDRESS => x"F357", + USE_VAR_ENDPOINT_ID => c_YES, + BROADCAST_SPECIAL_ADDR => x"45", + CLOCK_FREQUENCY => CLOCK_FREQUENCY + ) + port map ( + CLK => clk_sys_internal, + RESET => reset_i, + CLK_EN => '1', + + --Media interfacces + MED_DATAREADY_OUT(7*1-1 downto 0) => med_dataready_out, + MED_DATA_OUT(7*16-1 downto 0) => med_data_out, + MED_PACKET_NUM_OUT(7*3-1 downto 0) => med_packet_num_out, + MED_READ_IN(7*1-1 downto 0) => med_read_in, + MED_DATAREADY_IN(7*1-1 downto 0) => med_dataready_in, + MED_DATA_IN(7*16-1 downto 0) => med_data_in, + MED_PACKET_NUM_IN(7*3-1 downto 0) => med_packet_num_in, + MED_READ_OUT(7*1-1 downto 0) => med_read_out, + MED_STAT_OP(7*16-1 downto 0) => med_stat_op, + MED_CTRL_OP(7*16-1 downto 0) => med_ctrl_op, + + COMMON_STAT_REGS => common_stat_reg, + COMMON_CTRL_REGS => common_ctrl_reg, + MY_ADDRESS_OUT => my_address, + --REGIO INTERFACE + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + ONEWIRE => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_ORANGE <= '1'; --med_stat_op(8); + LED_YELLOW <= '0'; --med_stat_op(10); + LED_GREEN <= '0'; --med_stat_op(9); + LED_RED <= '1'; --med_stat_op(6); + +--------------------------------------------------------------------------- +-- DEBUG +--------------------------------------------------------------------------- + link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0); + link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0'); +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + clock_counter_proc : process(clk_sys_internal) + begin + if rising_edge(clk_sys_internal) then + time_counter <= time_counter + 1; + end if; + end process; + + process(clk_soda_i) + begin + if rising_edge(clk_soda_i) then + soda_counter_i <= soda_counter_i+1; + end if; + end process; + + +end trb3_periph_sodahub_arch; \ No newline at end of file diff --git a/source/trb_net_CRC.vhd b/source/trb_net_CRC.vhd new file mode 100644 index 0000000..7bf2d5c --- /dev/null +++ b/source/trb_net_CRC.vhd @@ -0,0 +1,74 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +library work; +use work.trb_net_std.all; + + +--this implementation uses IBM-CRC-16, i.e. x16 + x15 + x2 + 1 + + +entity trb_net_CRC is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + CRC_OUT : out std_logic_vector(15 downto 0); + CRC_match : out std_logic + ); +end entity; + + +architecture trb_net_CRC_arch of trb_net_CRC is +signal D,C, next_CRC_OUT, CRC : std_logic_vector(15 downto 0) := x"0000"; + +begin + D <= DATA_IN; + C <= CRC; + CRC_OUT <= CRC; + CRC_match <= not or_all(CRC); + + next_CRC_OUT(0) <= D(15) xor D(13) xor D(12) xor D(11) xor D(10) xor D(9) xor + D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor + D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor + C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor + C(9) xor C(10) xor C(11) xor C(12) xor C(13) xor C(15); + next_CRC_OUT(1) <= D(14) xor D(13) xor D(12) xor D(11) xor D(10) xor D(9) xor + D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor + D(2) xor D(1) xor C(1) xor C(2) xor C(3) xor C(4) xor + C(5) xor C(6) xor C(7) xor C(8) xor C(9) xor C(10) xor + C(11) xor C(12) xor C(13) xor C(14); + next_CRC_OUT(2) <= D(14) xor D(1) xor D(0) xor C(0) xor C(1) xor C(14); + next_CRC_OUT(3) <= D(15) xor D(2) xor D(1) xor C(1) xor C(2) xor C(15); + next_CRC_OUT(4) <= D(3) xor D(2) xor C(2) xor C(3); + next_CRC_OUT(5) <= D(4) xor D(3) xor C(3) xor C(4); + next_CRC_OUT(6) <= D(5) xor D(4) xor C(4) xor C(5); + next_CRC_OUT(7) <= D(6) xor D(5) xor C(5) xor C(6); + next_CRC_OUT(8) <= D(7) xor D(6) xor C(6) xor C(7); + next_CRC_OUT(9) <= D(8) xor D(7) xor C(7) xor C(8); + next_CRC_OUT(10) <= D(9) xor D(8) xor C(8) xor C(9); + next_CRC_OUT(11) <= D(10) xor D(9) xor C(9) xor C(10); + next_CRC_OUT(12) <= D(11) xor D(10) xor C(10) xor C(11); + next_CRC_OUT(13) <= D(12) xor D(11) xor C(11) xor C(12); + next_CRC_OUT(14) <= D(13) xor D(12) xor C(12) xor C(13); + next_CRC_OUT(15) <= D(15) xor D(14) xor D(12) xor D(11) xor D(10) xor D(9) xor + D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor + D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor + C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor + C(9) xor C(10) xor C(11) xor C(12) xor C(14) xor C(15); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + CRC <= (others => '0'); + elsif CLK_EN = '1' then + CRC <= next_CRC_OUT; + end if; + end if; + end process; + +end architecture; + diff --git a/source/trb_net_CRC8.vhd b/source/trb_net_CRC8.vhd new file mode 100644 index 0000000..3ae8474 --- /dev/null +++ b/source/trb_net_CRC8.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------- +-- Copyright (C) 2009 OutputLogic.com +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains the original copyright notice +-- and the associated disclaimer. +-- +-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +------------------------------------------------------------------------------- +-- CRC module for data(7:0) +-- lfsr(7:0)=1+x^4+x^5+x^8; +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.trb_net_std.all; + +entity trb_net_CRC8 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + CRC_OUT : out std_logic_vector(7 downto 0); + CRC_match : out std_logic + ); +end entity; + +architecture imp_crc of trb_net_CRC8 is + + signal lfsr_q: std_logic_vector (7 downto 0); + signal lfsr_c: std_logic_vector (7 downto 0); + + begin + + CRC_OUT <= lfsr_q; + CRC_match <= not or_all(lfsr_c); + + lfsr_c(0) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor data_in(0) xor data_in(3) xor data_in(4) xor data_in(6); + lfsr_c(1) <= lfsr_q(1) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor data_in(1) xor data_in(4) xor data_in(5) xor data_in(7); + lfsr_c(2) <= lfsr_q(2) xor lfsr_q(5) xor lfsr_q(6) xor data_in(2) xor data_in(5) xor data_in(6); + lfsr_c(3) <= lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(3) xor data_in(6) xor data_in(7); + lfsr_c(4) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(0) xor data_in(3) xor data_in(6) xor data_in(7); + lfsr_c(5) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(0) xor data_in(1) xor data_in(3) xor data_in(6) xor data_in(7); + lfsr_c(6) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(7) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(7); + lfsr_c(7) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor data_in(2) xor data_in(3) xor data_in(5); + + + process (CLK) begin + if rising_edge(CLK) then + if (RESET = '1') then + lfsr_q <= b"00000000"; + elsif (CLK_EN = '1') then + lfsr_q <= lfsr_c; + end if; + end if; + end process; +end architecture imp_crc; \ No newline at end of file -- 2.43.0