From e86b7881a694cbbf1738fd8c1f0963519e7dc281 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 14 Dec 2017 13:23:34 +0100 Subject: [PATCH] changed some media interface timing for control, fixed sensitivity lists, added med_control testbench. --- media_interfaces/sync/med_sync_control.vhd | 4 +- media_interfaces/sync/rx_reset_fsm.vhd | 2 +- media_interfaces/sync/tb/med_sync_tb.vhd | 236 +++++++++++++++++++++ media_interfaces/sync/tx_control.vhd | 9 +- media_interfaces/sync/tx_reset_fsm.vhd | 2 +- 5 files changed, 245 insertions(+), 8 deletions(-) create mode 100644 media_interfaces/sync/tb/med_sync_tb.vhd diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index 715b236..d2deaa9 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -63,7 +63,7 @@ architecture med_sync_control_arch of med_sync_control is signal rx_fsm_state : std_logic_vector(3 downto 0); signal tx_fsm_state : std_logic_vector(3 downto 0); signal wa_position_rx : std_logic_vector(3 downto 0); -signal start_timer : unsigned(20 downto 0) := (others => '0'); +signal start_timer : unsigned(11 downto 0) := (others => '0'); --FIXME SIMULATION 20 signal request_retr_i : std_logic; signal start_retr_i : std_logic; @@ -294,7 +294,7 @@ STAT_RESET(16) <= RX_CDR_LOL; STAT_RESET(17) <= RX_LOS; STAT_RESET(18) <= '0'; --RX_PCS_RST; STAT_RESET(19) <= '0'; -STAT_RESET(31 downto 20) <= start_timer(start_timer'left downto start_timer'left - 11); +STAT_RESET(31 downto 20) <= std_logic_vector(start_timer(start_timer'left downto start_timer'left - 11)); gen_link_reset : if IS_SYNC_SLAVE = 1 generate diff --git a/media_interfaces/sync/rx_reset_fsm.vhd b/media_interfaces/sync/rx_reset_fsm.vhd index 7fc3aec..4adfe86 100644 --- a/media_interfaces/sync/rx_reset_fsm.vhd +++ b/media_interfaces/sync/rx_reset_fsm.vhd @@ -24,7 +24,7 @@ end entity ; architecture rx_reset_fsm_arch of rx_reset_fsm is -constant count_index : integer := 19; +constant count_index : integer := 9; --FIXME SIMULATION 19 type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_timer1, CHECK_LOL_LOS, WAIT_FOR_timer2, NORMAL); signal cs: statetype; -- current state of lsm diff --git a/media_interfaces/sync/tb/med_sync_tb.vhd b/media_interfaces/sync/tb/med_sync_tb.vhd new file mode 100644 index 0000000..f6fea96 --- /dev/null +++ b/media_interfaces/sync/tb/med_sync_tb.vhd @@ -0,0 +1,236 @@ + +LIBRARY ieee ; +LIBRARY work ; +USE ieee.NUMERIC_STD.all ; +USE ieee.std_logic_1164.all ; +USE work.med_sync_define.all ; +USE work.trb_net_components.all ; +USE work.trb_net_std.all ; + +entity med_sync_tb is +end entity; + +architecture arch of med_sync_tb is + + + +component med_sync_control is + generic( + IS_SYNC_SLAVE : integer := 1; + IS_TX_RESET : integer := 1 + ); + port( + CLK_SYS : in std_logic; + CLK_RXI : in std_logic; + CLK_RXHALF : in std_logic; + CLK_TXI : in std_logic; + CLK_REF : in std_logic; + RESET : in std_logic; + CLEAR : in std_logic; + + SFP_LOS : in std_logic; + TX_LOL : in std_logic; + RX_CDR_LOL : in std_logic; + RX_LOS : in std_logic; + WA_POSITION : in std_logic_vector(3 downto 0); + + RX_SERDES_RST : out std_logic; + RX_PCS_RST : out std_logic; + QUAD_RST : out std_logic; + TX_PCS_RST : out std_logic; + + MEDIA_MED2INT : out MED2INT; + MEDIA_INT2MED : in INT2MED; + + TX_DATA : out std_logic_vector(7 downto 0); + TX_K : out std_logic; + RX_DATA : in std_logic_vector(7 downto 0); + RX_K : in std_logic; + + TX_DLM_WORD : in std_logic_vector(7 downto 0); + TX_DLM : in std_logic; + RX_DLM_WORD : out std_logic_vector(7 downto 0); + RX_DLM : out std_logic; + + SERDES_RX_READY_IN : in std_logic := '1'; + SERDES_TX_READY_IN : in std_logic := '1'; + + STAT_TX_CONTROL : out std_logic_vector(31 downto 0); + STAT_RX_CONTROL : out std_logic_vector(31 downto 0); + DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); + DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); + STAT_RESET : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end component; + + +signal clk_100_m, clk_100_s : std_logic := '1'; +signal clk_200_m, clk_200_s : std_logic := '1'; + +signal reset_m : std_logic := '1'; +signal clear_m : std_logic := '1'; +signal reset_s : std_logic := '1'; +signal clear_s : std_logic := '1'; + + +signal med2int_m, med2int_s : MED2INT; +signal int2med_m, int2med_s : INT2MED; + +signal tx_data_m, tx_data_s, rx_data_m, rx_data_s : std_logic_vector(7 downto 0); +signal tx_k_m, tx_k_s, rx_k_m, rx_k_s : std_logic; + + +begin + +reset_m <= '0' after 201 ns; +clear_m <= '0' after 51 ns; +reset_s <= '0' after 201 ns; +clear_s <= '0' after 51 ns; + +rx_data_s <= transport tx_data_m after 250 ns; +rx_data_m <= transport tx_data_s after 250 ns; +rx_k_s <= transport tx_k_m after 250 ns; +rx_k_m <= transport tx_k_s after 250 ns; + +clk_100_m <= not clk_100_m after 5 ns; +clk_200_m <= not clk_200_m after 2.5 ns; +clk_100_s <= not clk_100_s after 5 ns; +clk_200_s <= not clk_200_s after 2.5 ns; + + + + +process begin + int2med_m.ctrl_op <= x"0000"; + int2med_s.ctrl_op <= x"0000"; + int2med_m.data <= x"0000"; + int2med_m.packet_num <= "000"; + int2med_m.dataready <= '0'; + wait for 50 us; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"1122"; + int2med_m.packet_num <= "100"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"3344"; + int2med_m.packet_num <= "000"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"5566"; + int2med_m.packet_num <= "001"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"7788"; + int2med_m.packet_num <= "010"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"9900"; + int2med_m.packet_num <= "011"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.dataready <= '0'; + +end process; + + + +THE_MASTER : med_sync_control + generic map( + IS_SYNC_SLAVE => 0, + IS_TX_RESET => 0 + ) + port map( + CLK_SYS => clk_100_m, + CLK_RXI => clk_200_s, + CLK_RXHALF => clk_100_s, + CLK_TXI => clk_200_m, + CLK_REF => clk_200_m, + RESET => reset_m, + CLEAR => clear_m, + + SFP_LOS => '0', + TX_LOL => '0', + RX_CDR_LOL => '0', + RX_LOS => '0', + WA_POSITION => x"0", + + RX_SERDES_RST=> open, + RX_PCS_RST => open, + QUAD_RST => open, + TX_PCS_RST => open, + + MEDIA_MED2INT => med2int_m, + MEDIA_INT2MED => int2med_m, + + TX_DATA => tx_data_m, + TX_K => tx_k_m, + RX_DATA => rx_data_m, + RX_K => rx_k_m, + + TX_DLM_WORD => x"00", + TX_DLM => '0', + RX_DLM_WORD => open, + RX_DLM => open, + + SERDES_RX_READY_IN => '1', + SERDES_TX_READY_IN => '1', + STAT_TX_CONTROL => open, + STAT_RX_CONTROL => open, + DEBUG_TX_CONTROL => open, + DEBUG_RX_CONTROL => open, + STAT_RESET => open, + DEBUG_OUT => open + ); + + + +THE_SLAVE : med_sync_control + generic map( + IS_SYNC_SLAVE => 1, + IS_TX_RESET => 0 + ) + port map( + CLK_SYS => clk_100_s, + CLK_RXI => clk_200_m, + CLK_RXHALF => clk_100_m, + CLK_TXI => clk_200_s, + CLK_REF => clk_200_s, + RESET => reset_s, + CLEAR => clear_s, + + SFP_LOS => '0', + TX_LOL => '0', + RX_CDR_LOL => '0', + RX_LOS => '0', + WA_POSITION => x"0", + + RX_SERDES_RST=> open, + RX_PCS_RST => open, + QUAD_RST => open, + TX_PCS_RST => open, + + MEDIA_MED2INT => med2int_s, + MEDIA_INT2MED => int2med_s, + + TX_DATA => tx_data_s, + TX_K => tx_k_s, + RX_DATA => rx_data_s, + RX_K => rx_k_s, + + TX_DLM_WORD => x"00", + TX_DLM => '0', + RX_DLM_WORD => open, + RX_DLM => open, + + SERDES_RX_READY_IN => '1', + SERDES_TX_READY_IN => '1', + STAT_TX_CONTROL => open, + STAT_RX_CONTROL => open, + DEBUG_TX_CONTROL => open, + DEBUG_RX_CONTROL => open, + STAT_RESET => open, + DEBUG_OUT => open + ); + +end architecture; diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index 41b26db..220d45d 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -231,7 +231,8 @@ begin -- TX control state machine ---------------------------------------------------------------------- - THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN) + THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN, current_state, ram_empty, tx_allow_qtx, + send_link_reset_qtx, make_request_i, make_restart_i, send_dlm_i) begin if rising_edge(CLK_200) then -- ram_read <= '0'; @@ -322,8 +323,8 @@ begin current_state <= SEND_START_L; elsif send_dlm_i = '1' then current_state <= SEND_DLM_L; --- elsif (load_eop = '1') then --- current_state <= SEND_CHKSUM_L; + elsif (load_eop = '1') then + current_state <= SEND_CHKSUM_L; elsif ram_empty = '0' then -- ram_read <= '1'; current_state <= SEND_DATA_L; @@ -452,7 +453,7 @@ begin end if; end process; ---Store Restart position +--Store DLM send THE_STORE_DLM_PROC : process(CLK_200, RESET_IN) begin if RESET_IN = '1' then diff --git a/media_interfaces/sync/tx_reset_fsm.vhd b/media_interfaces/sync/tx_reset_fsm.vhd index b10d8e1..aef6db6 100644 --- a/media_interfaces/sync/tx_reset_fsm.vhd +++ b/media_interfaces/sync/tx_reset_fsm.vhd @@ -21,7 +21,7 @@ end entity; architecture tx_reset_fsm_arch of tx_reset_fsm is -constant count_index : integer := 19; +constant count_index : integer := 9; --FIXME SIMULATION 19 type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL); signal cs: statetype; -- current state of lsm -- 2.43.0