From e928e6755d92cb919e29b98ddf2d07ec5c79a931 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 22 Jun 2010 12:37:30 +0000 Subject: [PATCH] *** empty log message *** --- lattice/scm/pll_in200_out100.lpc | 58 +++++++++++ lattice/scm/pll_in200_out100.vhd | 167 +++++++++++++++++++++++++++++++ pinout/cts_fpga1.lpf | 11 +- trb_net_components.vhd | 1 + trb_net_std.vhd | 4 +- 5 files changed, 235 insertions(+), 6 deletions(-) create mode 100644 lattice/scm/pll_in200_out100.lpc create mode 100644 lattice/scm/pll_in200_out100.vhd diff --git a/lattice/scm/pll_in200_out100.lpc b/lattice/scm/pll_in200_out100.lpc new file mode 100644 index 0000000..81b334c --- /dev/null +++ b/lattice/scm/pll_in200_out100.lpc @@ -0,0 +1,58 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-6FC1152C +SpeedGrade=-6 +Package=FCBGA1152 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.1 +ModuleName=pll_in200_out100 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=06/22/2010 +Time=13:23:32 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Clki_freq=200 +U_OFrq=100 +OP_Tol=0.0 +ClkOP_Freq= 100.000000 +U_SFrq=100 +OS_Tol=0.0 +ClkOS_Freq= 100.000000 +Phase=0 +FineDelay=0 +FeedbackClk=CLKOP +Frequency= 100.000000 +enSpectrum=0 +smiport=0 +enRSTN=0 +Clki_boosting=DEL0 +Clkfb_boosting=DEL0 +Clki_fine=0 +Clkfb_fine=0 +enSpread=0 +modulation=1 +Desired=30 +Actual=30 +lock=Frequency +enGSR=0 +VcoRate= 600.000000 +Bandwidth= 5.262395 +enHighBand=0 +enBypassP=0 +enBypassS=0 diff --git a/lattice/scm/pll_in200_out100.vhd b/lattice/scm/pll_in200_out100.vhd new file mode 100644 index 0000000..ff4c4c5 --- /dev/null +++ b/lattice/scm/pll_in200_out100.vhd @@ -0,0 +1,167 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.1 +--/d/sugar/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 200 -mfreq 100 -nfreq 100 -tap 0 -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e + +-- Tue Jun 22 13:23:33 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library SCM; +use SCM.COMPONENTS.all; +-- synopsys translate_on + +entity pll_in200_out100 is + generic ( + SMI_OFFSET : in String := "0x410" + ); + port ( + clk: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in200_out100 : entity is true; +end pll_in200_out100; + +architecture Structure of pll_in200_out100 is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal clkos_t: std_logic; + signal clkop_t: std_logic; + signal clk_t: std_logic; + + attribute module_type : string; + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component EHXPLLA + generic (SMI_OFFSET : in String + -- synopsys translate_off + ; GSR : in String; CLKOS_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; CLKOS_FDEL : in Integer; + CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer; + CLKOS_MODE : in String; CLKOP_MODE : in String; + PHASEADJ : in Integer; CLKOS_VCODEL : in Integer + -- synopsys translate_on + ); + port (SMIADDR9: in std_logic; SMIADDR8: in std_logic; + SMIADDR7: in std_logic; SMIADDR6: in std_logic; + SMIADDR5: in std_logic; SMIADDR4: in std_logic; + SMIADDR3: in std_logic; SMIADDR2: in std_logic; + SMIADDR1: in std_logic; SMIADDR0: in std_logic; + SMIRD: in std_logic; SMIWR: in std_logic; + SMICLK: in std_logic; SMIWDATA: in std_logic; + SMIRSTN: in std_logic; CLKI: in std_logic; + CLKFB: in std_logic; RSTN: in std_logic; + CLKOS: out std_logic; CLKOP: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic; + SMIRDATA: out std_logic); + end component; + attribute module_type of EHXPLLA : component is "EHXPLLA"; + attribute ip_type : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute VCO_LOWERFREQ : string; + attribute GMCFREQSEL : string; + attribute GSR : string; + attribute SPREAD_DIV2 : string; + attribute SPREAD_DIV1 : string; + attribute SPREAD_DRIFT : string; + attribute SPREAD : string; + attribute CLKFB_FDEL : string; + attribute CLKI_FDEL : string; + attribute CLKFB_PDEL : string; + attribute CLKI_PDEL : string; + attribute LF_RESISTOR : string; + attribute LF_IX5UA : string; + attribute CLKOS_FDEL : string; + attribute CLKOS_VCODEL : string; + attribute PHASEADJ : string; + attribute CLKOS_MODE : string; + attribute CLKOP_MODE : string; + attribute CLKOS_DIV : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute ip_type of pll_in200_out100_0_0 : label is "EHXPLLA"; + attribute FREQUENCY_PIN_CLKOS of pll_in200_out100_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKOP of pll_in200_out100_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKI of pll_in200_out100_0_0 : label is "200.000000"; + attribute VCO_LOWERFREQ of pll_in200_out100_0_0 : label is "DISABLED"; + attribute GMCFREQSEL of pll_in200_out100_0_0 : label is "HIGH"; + attribute GSR of pll_in200_out100_0_0 : label is "ENABLED"; + attribute SPREAD_DIV2 of pll_in200_out100_0_0 : label is "2"; + attribute SPREAD_DIV1 of pll_in200_out100_0_0 : label is "2"; + attribute SPREAD_DRIFT of pll_in200_out100_0_0 : label is "1"; + attribute SPREAD of pll_in200_out100_0_0 : label is "DISABLED"; + attribute CLKFB_FDEL of pll_in200_out100_0_0 : label is "0"; + attribute CLKI_FDEL of pll_in200_out100_0_0 : label is "0"; + attribute CLKFB_PDEL of pll_in200_out100_0_0 : label is "DEL0"; + attribute CLKI_PDEL of pll_in200_out100_0_0 : label is "DEL0"; + attribute LF_RESISTOR of pll_in200_out100_0_0 : label is "0b111010"; + attribute LF_IX5UA of pll_in200_out100_0_0 : label is "31"; + attribute CLKOS_FDEL of pll_in200_out100_0_0 : label is "0"; + attribute CLKOS_VCODEL of pll_in200_out100_0_0 : label is "0"; + attribute PHASEADJ of pll_in200_out100_0_0 : label is "0"; + attribute CLKOS_MODE of pll_in200_out100_0_0 : label is "DIV"; + attribute CLKOP_MODE of pll_in200_out100_0_0 : label is "DIV"; + attribute CLKOS_DIV of pll_in200_out100_0_0 : label is "6"; + attribute CLKOP_DIV of pll_in200_out100_0_0 : label is "6"; + attribute CLKFB_DIV of pll_in200_out100_0_0 : label is "1"; + attribute CLKI_DIV of pll_in200_out100_0_0 : label is "2"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + pll_in200_out100_0_0: EHXPLLA + generic map (SMI_OFFSET=> SMI_OFFSET + -- synopsys translate_off + , GSR=> "ENABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0, + CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV", + CLKOP_MODE=> "DIV", CLKOS_DIV=> 6, CLKOP_DIV=> 6, CLKFB_DIV=> 1, + CLKI_DIV=> 2 + -- synopsys translate_on + ) + port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, + SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, + SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, + SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, + SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, + SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, + SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t, + RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, + CLKINTFB=>open, SMIRDATA=>open); + + clkos <= clkos_t; + clkop <= clkop_t; + clk_t <= clk; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of pll_in200_out100 is + for Structure + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:EHXPLLA use entity SCM.EHXPLLA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/pinout/cts_fpga1.lpf b/pinout/cts_fpga1.lpf index 0b30406..4adeeb6 100644 --- a/pinout/cts_fpga1.lpf +++ b/pinout/cts_fpga1.lpf @@ -12,10 +12,10 @@ IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ; # Clock I/O ################################################################# LOCATE COMP "ADO_CLKOUT" SITE "L29"; -LOCATE COMP "CLK200_IN" SITE "L1"; +LOCATE COMP "CLK_200_IN" SITE "L1"; IOBUF PORT "ADO_CLKOUT" IO_TYPE=LVDS25 ; -IOBUF PORT "CLK200_IN" IO_TYPE=LVDS25 ; +IOBUF PORT "CLK_200_IN" IO_TYPE=LVDS25 ; ################################################################# # Reset @@ -154,9 +154,12 @@ LOCATE COMP "FFC_19" SITE "AD17"; #"FFC_N__9" LOCATE COMP "FFC_20" SITE "AL17"; #"FFC_P__10" LOCATE COMP "FFC_21" SITE "AM17"; #"FFC_N__10" LOCATE COMP "FFC_22" SITE "AE17"; #"FFC_P__11" -LOCATE COMP "FFC_23" SITE "AF17"; #"FFC_N__11" +#LOCATE COMP "FFC_23" SITE "AF17"; #"FFC_N__11" +LOCATE COMP "ONEWIRE_MONITOR_IN" SITE "AF17"; #"FFC_N__11" + DEFINE PORT GROUP "FFC_group" "FFC*" ; -IOBUF GROUP "FFC_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; +IOBUF GROUP "FFC_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; +IOBUF PORT "ONEWIRE_MONITOR_IN" IO_TYPE=LVCMOS25 PULLMODE=UP ; ################################################################# # Display / LED diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 3c7068e..119aaee 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -1922,6 +1922,7 @@ package trb_net_components is port ( CLK: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; LOCK: out std_logic ); end component; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index e08020f..7356a16 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -75,8 +75,8 @@ package trb_net_std is constant std_TERM_SECURE_MODE : integer := c_YES; constant std_MUX_SECURE_MODE : integer := c_NO; constant std_FORCE_REPLY : integer := c_YES; - constant cfg_USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); - constant cfg_USE_ACKNOWLEDGE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + constant cfg_USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_NO,c_YES); + constant cfg_USE_ACKNOWLEDGE : channel_config_t := (c_YES,c_YES,c_NO,c_YES); constant cfg_FORCE_REPLY : channel_config_t := (c_YES,c_YES,c_YES,c_YES); constant cfg_USE_REPLY_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); constant c_MAX_IDLE_TIME_PER_PACKET : integer := 24; -- 2.43.0