From e9305ec0670ba0573d8921a4a635bf463bd71531 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 4 Oct 2010 11:55:55 +0000 Subject: [PATCH] *** empty log message *** --- testbenches/tb_trb_net16_rxtx_control.vhd | 393 ++++++++++++++++------ 1 file changed, 282 insertions(+), 111 deletions(-) diff --git a/testbenches/tb_trb_net16_rxtx_control.vhd b/testbenches/tb_trb_net16_rxtx_control.vhd index 57f19e2..a83111c 100644 --- a/testbenches/tb_trb_net16_rxtx_control.vhd +++ b/testbenches/tb_trb_net16_rxtx_control.vhd @@ -1,10 +1,11 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.numeric_std.all; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.trb_net_std.all; ---use work.trb_net_components.all; +use work.trb_net_components.all; entity rxtxtb is end entity; @@ -47,6 +48,7 @@ architecture arch of rxtxtb is RX_DATA_IN : in std_logic_vector(7 downto 0); RX_K_IN : in std_logic; RX_CV_IN : in std_logic; + RX_DISP_ERR_IN : in std_logic; RX_ALLOW_IN : in std_logic; -- media interface SYSCLK_IN : in std_logic; -- 100MHz master clock @@ -65,6 +67,7 @@ architecture arch of rxtxtb is MAKE_TRBNET_RESET_OUT : out std_logic; -- Status signals PACKET_TIMEOUT_OUT : out std_logic; + ENABLE_CORRECTION_IN : in std_logic; -- Debugging DEBUG_OUT : out std_logic_vector(31 downto 0) ); @@ -112,9 +115,28 @@ architecture arch of rxtxtb is signal tx1_allow_in : std_logic := '0'; signal tx2_allow_in : std_logic := '0'; + signal toggle1 : std_logic; + signal counter1 : std_logic_vector(11 downto 0); + signal read1 : std_logic; + signal dataready1 : std_logic; + signal number1 : std_logic_vector(2 downto 0); + signal data1 : std_logic_vector(15 downto 0); + + signal toggle2 : std_logic; + signal counter2 : std_logic_vector(11 downto 0); + signal read2 : std_logic; + signal dataready2 : std_logic; + signal number2 : std_logic_vector(2 downto 0); + signal data2 : std_logic_vector(15 downto 0); + signal dummy : std_logic_vector(31 downto 0); + begin +--------------------------------------------------------------------- +--Clock & Reset +--------------------------------------------------------------------- + proc_clk251 : process begin wait for 20 ns; @@ -144,6 +166,33 @@ begin wait; end process; + +--------------------------------------------------------------------- +--control from LSM +--------------------------------------------------------------------- + process + begin + tx1_allow_in <= '0'; + tx2_allow_in <= '0'; + rx1_allow_in <= '0'; + rx2_allow_in <= '0'; + tx1_send_link_reset_in<= '0'; + wait for 200 ns; + wait until rising_edge(clk); wait for 1 ns; + rx1_allow_in <= '1'; + rx2_allow_in <= '1'; + wait for 2050 ns; + wait until rising_edge(clk); wait for 1 ns; + tx1_allow_in <= '1'; + tx2_allow_in <= '1'; + wait; + end process; + + +--------------------------------------------------------------------- +-- TX control +--------------------------------------------------------------------- + uut_tx1 : trb_net16_tx_control port map( TXCLK_IN => clk251, @@ -196,6 +245,11 @@ begin DEBUG_OUT => open ); + + +--------------------------------------------------------------------- +--RX control +--------------------------------------------------------------------- uut_rx1 : trb_net16_rx_control port map( RESET_IN => reset, @@ -205,6 +259,7 @@ begin RX_DATA_IN => rx1_data_in, RX_K_IN => rx1_k_in, RX_CV_IN => rx1_cv_in, + RX_DISP_ERR_IN => '0', RX_ALLOW_IN => rx1_allow_in, -- media interface SYSCLK_IN => clk, @@ -223,6 +278,7 @@ begin MAKE_TRBNET_RESET_OUT => open, -- Status signals PACKET_TIMEOUT_OUT => open, + ENABLE_CORRECTION_IN => '1', -- Debugging DEBUG_OUT => open ); @@ -236,6 +292,7 @@ begin RX_DATA_IN => rx2_data_in, RX_K_IN => rx2_k_in, RX_CV_IN => rx2_cv_in, + RX_DISP_ERR_IN => '0', RX_ALLOW_IN => rx2_allow_in, -- media interface SYSCLK_IN => clk, @@ -254,10 +311,14 @@ begin MAKE_TRBNET_RESET_OUT => open, -- Status signals PACKET_TIMEOUT_OUT => open, + ENABLE_CORRECTION_IN => '1', -- Debugging DEBUG_OUT => open ); +--------------------------------------------------------------------- +--Media Simulation +--------------------------------------------------------------------- rx1_data_in <= transport tx2_data_out after 200 ns; rx1_k_in <= transport tx2_k_out after 200 ns; @@ -268,124 +329,234 @@ rx2_k_in <= transport tx1_k_out after 200 ns; rx2_cv_in <= '0', '1' after 4400 ns, '0' after 4440 ns; ---Data 1 input - process +--------------------------------------------------------------------- +--Data input 1 +--------------------------------------------------------------------- + + process(clk) begin - tx1_data_in <= (others => '0'); - tx1_write_in <= '0'; - wait for 2300 ns; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"1001"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"2002"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_write_in <= '0'; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"3003"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"4004"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_write_in <= '0'; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"5005"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"6006"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"7007"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"8008"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"9009"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"a00a"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_write_in <= '0'; - wait for 1500 ns; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"b00b"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"c00c"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"d00d"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"e00e"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= x"f00f"; - tx1_write_in <= '1'; - if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx1_data_in <= (others => '0'); - tx1_write_in <= '0'; - wait; + if rising_edge(clk) then + if reset = '1' then + number1 <= "100"; + dataready1 <= '0'; + toggle1 <= '0'; + counter1 <= (others => '0'); + else + if ((counter1 < 19 and toggle1 = '1') or (counter1 < 14 and toggle1 = '0')) or + (((counter1 < 20 and toggle1 = '1') or (counter1 < 15 and toggle1 = '0')) and read1 = '0') then + dataready1 <= '1'; + if read1 = '1' and dataready1 = '1' then + counter1 <= counter1 + 1; + end if; + else + dataready1 <= '0'; + if counter1 = 2046 then + counter1 <= (others => '0'); + toggle1 <= not toggle1; + else + counter1 <= counter1 + 1; + end if; + end if; + if read1 = '1' and dataready1 = '1' then + if number1 = "100" then + number1 <= "000"; + else + number1 <= number1 + 1; + end if; + end if; + end if; + end if; end process; + data1 <= (counter1(7 downto 0)) & (counter1(7 downto 0)); - process - begin - tx2_data_in <= (others => '0'); - tx2_write_in <= '0'; - wait for 2300 ns; - wait until rising_edge(clk); wait for 1 ns; - tx2_data_in <= x"1001"; - tx2_write_in <= '1'; - if tx2_read_out = '0' then wait until tx2_read_out = '1'; end if; - wait until rising_edge(clk); wait for 1 ns; - tx2_data_in <= (others => '0'); - tx2_write_in <= '0'; - wait; - end process; ---control from LSM - process +--------------------------------------------------------------------- +-- Data input 2 +--------------------------------------------------------------------- + + data2 <= (counter2(7 downto 0)) & (counter2(7 downto 0)); + + process(clk) begin - tx1_allow_in <= '0'; - tx2_allow_in <= '0'; - rx1_allow_in <= '0'; - rx2_allow_in <= '0'; - tx1_send_link_reset_in<= '0'; - wait for 200 ns; - wait until rising_edge(clk); wait for 1 ns; - rx1_allow_in <= '1'; - rx2_allow_in <= '1'; - wait for 2050 ns; - wait until rising_edge(clk); wait for 1 ns; - tx1_allow_in <= '1'; - tx2_allow_in <= '1'; - wait for 15 us; - tx1_send_link_reset_in <= '1'; - wait for 1 us; - tx1_send_link_reset_in <= '0'; + if rising_edge(clk) then + if reset = '1' then + number2 <= "100"; + dataready2 <= '0'; + toggle2 <= '0'; + counter2 <= (others => '0'); + else + if ((counter2 < 23 and toggle2 = '1') or (counter2 < 18 and toggle2 = '0')) or + (((counter2 < 24 and toggle2 = '1') or (counter2 < 19 and toggle2 = '0')) and read2 = '0') or + (counter2 = 30 and (dataready2 = '0' or read2 = '0')) then + dataready2 <= '1'; + if read2 = '1' and dataready2 = '1' then + counter2 <= counter2 + 1; + end if; + else + dataready2 <= '0'; + if counter2 = 2047 then + counter2 <= (others => '0'); + toggle2 <= not toggle2; + else + counter2 <= counter2 + 1; + end if; + end if; + if read2 = '1' and dataready2 = '1' then + if number2 = "100" then + number2 <= "000"; + else + number2 <= number2 + 1; + end if; + end if; + end if; + end if; end process; +--------------------------------------------------------------------- +--Multiplexer +--------------------------------------------------------------------- + + the_test_mux : trb_net16_io_multiplexer + generic map ( + USE_INPUT_SBUF => (others => c_NO) + ) + port map( + -- Misc + CLK => clk, + RESET => reset, + CLK_EN => '1', + -- Media direction port + MED_DATAREADY_IN => '0', + MED_DATA_IN => (others => '0'), + MED_PACKET_NUM_IN => (others => '0'), + MED_READ_OUT => open, + MED_DATAREADY_OUT => tx1_write_in, + MED_DATA_OUT => tx1_data_in, + MED_PACKET_NUM_OUT => open, + MED_READ_IN => tx1_read_out, + -- Internal direction port + INT_DATA_OUT => open, + INT_PACKET_NUM_OUT => open, + INT_DATAREADY_OUT => open, + INT_READ_IN => (others => '1'), + INT_DATAREADY_IN(0) => dataready1, + INT_DATAREADY_IN(1) => '0', + INT_DATAREADY_IN(2) => dataready2, + INT_DATAREADY_IN(7 downto 3) => (others => '0'), + INT_DATA_IN(15 downto 0) => data1, + INT_DATA_IN(31 downto 16) => (others => '0'), + INT_DATA_IN(47 downto 32) => data2, + INT_DATA_IN(127 downto 48) => (others => '0'), + INT_PACKET_NUM_IN(2 downto 0) => number1, + INT_PACKET_NUM_IN(5 downto 3) => "000", + INT_PACKET_NUM_IN(8 downto 6) => number2, + INT_PACKET_NUM_IN(23 downto 9)=> (others => '0'), + INT_READ_OUT(0) => read1, + INT_READ_OUT(1) => dummy(0), + INT_READ_OUT(2) => read2, + INT_READ_OUT(3) => dummy(1), + INT_READ_OUT(7 downto 4) => dummy(6 downto 3), + ctrl => (others => '0') + ); + + + +-- --Data 1 input +-- process +-- begin +-- tx1_data_in <= (others => '0'); +-- tx1_write_in <= '0'; +-- wait for 2300 ns; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"1001"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"2002"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_write_in <= '0'; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"3003"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"4004"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_write_in <= '0'; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"5005"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"6006"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"7007"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"8008"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"9009"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"a00a"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_write_in <= '0'; +-- wait for 1500 ns; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"b00b"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"c00c"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"d00d"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"e00e"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= x"f00f"; +-- tx1_write_in <= '1'; +-- if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx1_data_in <= (others => '0'); +-- tx1_write_in <= '0'; +-- wait; +-- end process; +-- +-- +-- process +-- begin +-- tx2_data_in <= (others => '0'); +-- tx2_write_in <= '0'; +-- wait for 2300 ns; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx2_data_in <= x"1001"; +-- tx2_write_in <= '1'; +-- if tx2_read_out = '0' then wait until tx2_read_out = '1'; end if; +-- wait until rising_edge(clk); wait for 1 ns; +-- tx2_data_in <= (others => '0'); +-- tx2_write_in <= '0'; +-- wait; +-- end process; end architecture; -- 2.43.0