From e9d2a6972d4708e325d5c6d4cdfee51858c366a7 Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Mon, 6 Jan 2014 15:55:41 +0100 Subject: [PATCH] Back a few steps. This is compiled including: - several syn_keep and syn_preserve attributes to keep signal names transparent - synthesis constraints to get more control of clock resources. This version has BOTH transmit and receive buffers and is therefore not synchronous. However: The source-transmiter is clocked from the GPLL. The client-receiver is clocked from rx_full (as it should be) The client-transmiter is clocked from rx_full (max synch. with receiver) The source-receiver is also clocked with (source-)rx_full. This seems to work ok. Next step is to remove the rx_fifo. As rxiclk_ch0 is clocked with rx_full aswell, this should not make any difference. Will try first for the source, second for the client aswell. This should then be really synchronous, as Lattice claims that the TX-fifo has a fixed latency. Seeing is believing. --- soda_client.ldf | 18 +- soda_client.lpf | 377 ++++++++---------- soda_source.ldf | 13 +- soda_source.lpf | 36 +- soda_source/soda_source_syn.prj | 39 +- source/med_ecp3_sfp_sync_down.vhd | 25 +- source/med_ecp3_sfp_sync_up.vhd | 42 +- source/serdes_sync_downstream.ipx | 14 +- source/serdes_sync_downstream.lpc | 12 +- source/serdes_sync_downstream.txt | 6 +- source/serdes_sync_downstream.vhd | 10 +- source/serdes_sync_upstream.ipx | 14 +- source/serdes_sync_upstream.lpc | 26 +- source/serdes_sync_upstream.txt | 12 +- source/serdes_sync_upstream.vhd | 23 +- source/soda_client.vhd | 4 +- source/soda_client_synconstraints.fdc | 66 +++ source/soda_components.vhd | 16 +- source/soda_packet_builder.vhd | 6 +- source/soda_packet_handler.vhd | 160 ++++---- .../soda_source_synconstraints.fdc | 19 +- source/trb3_periph_sodaclient.vhd | 77 ++-- source/trb3_periph_sodasource.vhd | 195 +++++---- 23 files changed, 687 insertions(+), 523 deletions(-) create mode 100644 source/soda_client_synconstraints.fdc rename {soda_source => source}/soda_source_synconstraints.fdc (56%) diff --git a/soda_client.ldf b/soda_client.ldf index 91c2d36..4e37427 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -50,6 +50,12 @@ + + + + + + @@ -65,12 +71,6 @@ - - - - - - @@ -92,9 +92,6 @@ - - - @@ -323,6 +320,9 @@ + + + diff --git a/soda_client.lpf b/soda_client.lpf index 33939f2..6be6dfb 100644 --- a/soda_client.lpf +++ b/soda_client.lpf @@ -1,268 +1,223 @@ -rvl_alias "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0"; +rvl_alias "clk_raw_internal" "clk_raw_internal"; +RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; - ################################################################# # Basic Settings ################################################################# - # SYSCONFIG MCCLK_FREQ = 2.5; - - FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; - FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; - FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; - +# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Clock I/O ################################################################# LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; -LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; -LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; -LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";s LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; -LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; - +#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; DEFINE PORT GROUP "CLK_group" "CLK*" ; -IOBUF GROUP "CLK_group" IO_TYPE=LVDS25; - - +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; ################################################################# # Trigger I/O ################################################################# - #Trigger from fan-out -LOCATE COMP "TRIGGER_LEFT" SITE "V3"; -LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; -IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; -IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; - - - - +#LOCATE COMP "TRIGGER_LEFT" SITE "V3"; +#LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; +#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; +#IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; ################################################################# # To central FPGA ################################################################# - -LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; -LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; -LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; -LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; -LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; -LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; -LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; -LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; -LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; -LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; -LOCATE COMP "FPGA5_COMM_10" SITE "V10"; -LOCATE COMP "FPGA5_COMM_11" SITE "W10"; -DEFINE PORT GROUP "FPGA_group" "FPGA*" ; -IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; - -LOCATE COMP "TEST_LINE_0" SITE "A5"; -LOCATE COMP "TEST_LINE_1" SITE "A6"; -LOCATE COMP "TEST_LINE_2" SITE "G8"; -LOCATE COMP "TEST_LINE_3" SITE "F9"; -LOCATE COMP "TEST_LINE_4" SITE "D9"; -LOCATE COMP "TEST_LINE_5" SITE "D10"; -LOCATE COMP "TEST_LINE_6" SITE "F10"; -LOCATE COMP "TEST_LINE_7" SITE "E10"; -LOCATE COMP "TEST_LINE_8" SITE "A8"; -LOCATE COMP "TEST_LINE_9" SITE "B8"; -LOCATE COMP "TEST_LINE_10" SITE "G10"; -LOCATE COMP "TEST_LINE_11" SITE "G9"; -LOCATE COMP "TEST_LINE_12" SITE "C9"; -LOCATE COMP "TEST_LINE_13" SITE "C10"; -LOCATE COMP "TEST_LINE_14" SITE "H10"; -LOCATE COMP "TEST_LINE_15" SITE "H11"; +#LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +#LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +#LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +#LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +#LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +#LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +#LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +#LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +#LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +#LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +#LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +#LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +#DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +#IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +LOCATE COMP "TEST_LINE[0]" SITE "A5" ; +LOCATE COMP "TEST_LINE[1]" SITE "A6" ; +LOCATE COMP "TEST_LINE[2]" SITE "G8" ; +LOCATE COMP "TEST_LINE[3]" SITE "F9" ; +LOCATE COMP "TEST_LINE[4]" SITE "D9" ; +LOCATE COMP "TEST_LINE[5]" SITE "D10" ; +LOCATE COMP "TEST_LINE[6]" SITE "F10" ; +LOCATE COMP "TEST_LINE[7]" SITE "E10" ; +LOCATE COMP "TEST_LINE[8]" SITE "A8" ; +LOCATE COMP "TEST_LINE[9]" SITE "B8" ; +LOCATE COMP "TEST_LINE[10]" SITE "G10" ; +LOCATE COMP "TEST_LINE[11]" SITE "G9" ; +LOCATE COMP "TEST_LINE[12]" SITE "C9" ; +LOCATE COMP "TEST_LINE[13]" SITE "C10" ; +LOCATE COMP "TEST_LINE[14]" SITE "H10" ; +LOCATE COMP "TEST_LINE[15]" SITE "H11" ; DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; - +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; ################################################################# # Connection to AddOn ################################################################# - -LOCATE COMP "LED_LINKOK_1" SITE "P1"; #DQLL0_0 #1 -LOCATE COMP "LED_RX_1" SITE "P2"; #DQLL0_1 #3 -LOCATE COMP "LED_TX_1" SITE "T2"; #DQLL0_2 #5 -LOCATE COMP "SFP_MOD0_1" SITE "U3"; #DQLL0_3 #7 -LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9 -LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11 -LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13 -LOCATE COMP "SFP_TXDIS_1" SITE "P3"; #DQSLL0_C #15 -LOCATE COMP "SFP_LOS_1" SITE "P5"; #DQLL0_6 #17 -LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19 - -LOCATE COMP "LED_LINKOK_2" SITE "N5"; #DQLL0_8 #21 -LOCATE COMP "LED_RX_2" SITE "N6"; #DQLL0_9 #23 -LOCATE COMP "LED_TX_2" SITE "AC2"; #DQLL2_0 #25 -LOCATE COMP "SFP_MOD0_2" SITE "AC3"; #DQLL2_1 #27 -LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29 -LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31 -LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33 -LOCATE COMP "SFP_TXDIS_2" SITE "AA2"; #DQLL2_5 #35 -LOCATE COMP "SFP_LOS_2" SITE "W7"; #DQLL2_T #37 #should be DQSLL2 -LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 - -LOCATE COMP "LED_LINKOK_3" SITE "AD1"; #DQLL3_0 #2 -LOCATE COMP "LED_RX_3" SITE "AD2"; #DQLL3_1 #4 -LOCATE COMP "LED_TX_3" SITE "AB5"; #DQLL3_2 #6 -LOCATE COMP "SFP_MOD0_3" SITE "AB6"; #DQLL3_3 #8 -LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10 -LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12 -LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 -LOCATE COMP "SFP_TXDIS_3" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3 -LOCATE COMP "SFP_LOS_3" SITE "AA3"; #DQLL3_6 #18 -LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20 - -LOCATE COMP "LED_LINKOK_4" SITE "W8"; #DQLL3_8 #22 -LOCATE COMP "LED_RX_4" SITE "W9"; #DQLL3_9 #24 -LOCATE COMP "LED_TX_4" SITE "V1"; #DQLL1_0 #26 -LOCATE COMP "SFP_MOD0_4" SITE "U2"; #DQLL1_1 #28 -LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30 -LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32 -LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34 -LOCATE COMP "SFP_TXDIS_4" SITE "R3"; #DQLL1_5 #36 -LOCATE COMP "SFP_LOS_4" SITE "T3"; #DQSLL1_T #38 -LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40 - - - -LOCATE COMP "LED_LINKOK_5" SITE "W23"; #DQLR1_0 #169 -LOCATE COMP "LED_RX_5" SITE "W22"; #DQLR1_1 #171 -LOCATE COMP "LED_TX_5" SITE "AA25"; #DQLR1_2 #173 -LOCATE COMP "SFP_MOD0_5" SITE "Y24"; #DQLR1_3 #175 -LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177 -LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179 -LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181 -LOCATE COMP "SFP_TXDIS_5" SITE "W20"; #DQSLR1_C #183 -LOCATE COMP "SFP_LOS_5" SITE "AA24"; #DQLR1_6 #185 -LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187 - -LOCATE COMP "LED_LINKOK_6" SITE "R25"; #DQLR2_0 #170 -LOCATE COMP "LED_RX_6" SITE "R26"; #DQLR2_1 #172 -LOCATE COMP "LED_TX_6" SITE "T25"; #DQLR2_2 #174 -LOCATE COMP "SFP_MOD0_6" SITE "T24"; #DQLR2_3 #176 -LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178 -LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180 -LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182 -LOCATE COMP "SFP_TXDIS_6" SITE "V22"; #DQSLR2_C #184 -LOCATE COMP "SFP_LOS_6" SITE "U24"; #DQLR2_6 #186 -LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188 - - +LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 +LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 +LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 +LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 +#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9 +#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11 +#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13 +LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 +LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 +#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19 +LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 +LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 +LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 +LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 +#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29 +#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31 +#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33 +LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 +LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 +#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 +LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 +LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 +LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 +LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 +#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10 +#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12 +#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 +LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 +#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20 +LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 +LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 +LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 +LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 +#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30 +#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32 +#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34 +LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 +LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 +#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40 +LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 +LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 +LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 +LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 +#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177 +#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179 +#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181 +LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 +LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 +#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187 +LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 +LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 +LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 +LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 +#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178 +#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180 +#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182 +LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 +LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 +#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188 DEFINE PORT GROUP "SFP_group" "SFP*" ; -IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP; - - +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; ################################################################# # Additional Lines to AddOn ################################################################# - #Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 #all lines are input only #line 4/5 go to PLL input -LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 -LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 -LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 -LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 -LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 - +#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 +#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 ################################################################# # Flash ROM and Reboot ################################################################# - -LOCATE COMP "FLASH_CLK" SITE "B12"; -LOCATE COMP "FLASH_CS" SITE "E11"; -LOCATE COMP "FLASH_DIN" SITE "E12"; -LOCATE COMP "FLASH_DOUT" SITE "A12"; - +LOCATE COMP "FLASH_CLK" SITE "B12" ; +LOCATE COMP "FLASH_CS" SITE "E11" ; +LOCATE COMP "FLASH_DIN" SITE "E12" ; +LOCATE COMP "FLASH_DOUT" SITE "A12" ; DEFINE PORT GROUP "FLASH_group" "FLASH*" ; -IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; - -LOCATE COMP "PROGRAMN" SITE "B11"; -IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; - - +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "PROGRAMN" SITE "B11" ; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; ################################################################# # Misc ################################################################# -LOCATE COMP "TEMPSENS" SITE "A13"; -IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; - +LOCATE COMP "TEMPSENS" SITE "A13" ; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; #coding of FPGA number -LOCATE COMP "CODE_LINE_1" SITE "AA20"; -LOCATE COMP "CODE_LINE_0" SITE "Y21"; -IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; -IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; - +LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; +LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; +IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; #terminated differential pair to pads -LOCATE COMP "SUPPL" SITE "C14"; -IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; - - +LOCATE COMP "SUPPL" SITE "C14" ; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25; ################################################################# # LED ################################################################# -LOCATE COMP "LED_GREEN" SITE "F12"; -LOCATE COMP "LED_ORANGE" SITE "G13"; -LOCATE COMP "LED_RED" SITE "A15"; -LOCATE COMP "LED_YELLOW" SITE "A16"; +LOCATE COMP "LED_GREEN" SITE "F12" ; +LOCATE COMP "LED_ORANGE" SITE "G13" ; +LOCATE COMP "LED_RED" SITE "A15" ; +LOCATE COMP "LED_YELLOW" SITE "A16" ; DEFINE PORT GROUP "LED_group" "LED*" ; -IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; - +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; - ################################################################# # Basic Settings ################################################################# - - SYSCONFIG MCCLK_FREQ = 20; - - FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; - FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; - FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; - FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; - +SYSCONFIG MCCLK_FREQ=20 ; +# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ; +# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Reset Nets ################################################################# -GSR_NET NET "GSR_N"; - - - - +#GSR_NET NET "GSR_N"; ################################################################# # Locate Serdes and media interfaces ################################################################# -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ; - -LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; - - -REGION "MEDIA_UPLINK" "R90C95D" 13 25; -REGION "MEDIA_DOWNLINK" "R90C120D" 25 35; -REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE; -REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE; - -LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; -LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; - -LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; -LOCATE UGROUP "THE_SYNC_LINK/media_interface_group" REGION "MEDIA_DOWNLINK" ; - - -MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns; -MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20 ns; -MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20 ns; -MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20 ns; -MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20 ns; - -MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -BLOCK JTAGPATHS; +#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; +#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; +#REGION "UPLINK_REGION" "R90C45D" 25 35 DEVSIZE; # Uplink is now fiber ! +#REGION "SPI_REGION" "R3C77D" 15 16 DEVSIZE; #"R13C150D" 15 18 DEVSIZE; +#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE; +#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ; +#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ; +#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ; No longer present in copper +#LOCATE UGROUP "THE_SYNC_LINK/media_uplink_group" REGION "UPLINK_REGION" ; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20.000000 ns ; +#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +BLOCK JTAGPATHS ; +## IOBUF ALLPORTS ; +#USE SECONDARY NET "reveal_ist_260" ; +USE PRIMARY NET "clk_raw_internal" ; +USE PRIMARY NET "clk_sys_internal" ; +#USE SECONDARY NET "THE_SYNC_LINK/sci_read_i" ; +#USE SECONDARY NET "THE_SYNC_LINK/sci_write_i" ; +USE PRIMARY PURE NET "CLK_PCLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; +USE PRIMARY PURE NET "GPLL_CLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; +USE PRIMARY NET "soda_rx_clock_full" ; +USE PRIMARY NET "soda_rx_clock_half" ; diff --git a/soda_source.ldf b/soda_source.ldf index 5e001a3..d3f2bf9 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -155,22 +155,22 @@ - + - + - + - + - + @@ -323,6 +323,9 @@ + + + diff --git a/soda_source.lpf b/soda_source.lpf index 1d28f36..bb301ca 100644 --- a/soda_source.lpf +++ b/soda_source.lpf @@ -1,6 +1,4 @@ -RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; -RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; -RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; +rvl_alias "clk_raw_internal" "clk_raw_internal"; RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; @@ -15,14 +13,16 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# # Clock I/O ################################################################# -#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; -#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; #LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +#LOCATE COMP "PCSA_REFCLKP" SITE "AC17"; +#LOCATE COMP "PCSA_REFCLKN" SITE "AC18"; #LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; -LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? -#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; -DEFINE PORT GROUP "CLK_group" "CLK*" ; +#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL! +DEFINE PORT GROUP "CLK_group" "*CLK*" ; IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; ################################################################# # Trigger I/O @@ -202,8 +202,8 @@ LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; #REGION "MEDIA_UPLINK_REGION" "R90C95D" 20 25 DEVSIZE; #REGION "MEDIA_DOWNLINK_REGION" "R90C45D" 25 35 DEVSIZE; -#REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE; #REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE; +#REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE; #LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ; #LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ; #LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ; @@ -212,9 +212,19 @@ LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ; MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; -MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ; MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20.000000 ns ; MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; BLOCK JTAGPATHS ; -USE PRIMARY NET "CLK_GPLL_RIGHT_c" ; -FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ; +## IOBUF ALLPORTS ; +#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; + +FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ; +FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ; +FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" 200.000000 MHz ; +FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" 100.000000 MHz ; +USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" ; +USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" ; +USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" ; +USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" ; + diff --git a/soda_source/soda_source_syn.prj b/soda_source/soda_source_syn.prj index 315b355..0eba5b7 100644 --- a/soda_source/soda_source_syn.prj +++ b/soda_source/soda_source_syn.prj @@ -1,20 +1,28 @@ #-- Synopsys, Inc. -#-- Version G-2012.09L-1 +#-- Version G-2012.09L-SP1 #-- Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj -#-- Written on Tue Sep 3 13:13:24 2013 +#-- Written on Mon Dec 23 12:02:08 2013 #project files -add_file -vhdl -lib work "/usr/local/diamond/2.1_x64/cae_library/synthesis/vhdl/ecp3.vhd" +add_file -constraint "/local/lemmens/lattice/soda/source/soda_source_clock_constraints.sdc" +add_file -vhdl -lib work "/usr/local/diamond/2.2_x64/cae_library/synthesis/vhdl/ecp3.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/version.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_components.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_source.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_d8crc8.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_builder.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_handler.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_superburst_gen.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_builder.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_cmd_window_generator.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_d8crc8.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/med_ecp3_sfp_sync_down.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/serdes_sync_downstream.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_SOB_faker.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_calibration_timer.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_reply_handler.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/posedge_to_pulse.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_tx_control.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_components.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC8.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_onewire.vhd" @@ -27,7 +35,6 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_trigger_ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/fpga_reboot.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_slim.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_master.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_ltc2600.vhd" @@ -48,12 +55,12 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_sbuf.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf5.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf6.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_encoder.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regIO.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regio_bus_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_encoder.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_dummy_fifo.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_dummy_fifo.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_dummy_fifo.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_arbiter.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_pattern_gen.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_obuf.vhd" @@ -89,21 +96,20 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/med_sync_define.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_control.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_reset_fsm.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/tx_control.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/tx_reset_fsm.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_base.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/trb3_periph_sodasource.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -fpga_constraint "./FDC_constraints/soda_source/soda_source_syn_translated.fdc" #implementation: "soda_source" @@ -115,6 +121,9 @@ impl -add soda_source -type fpga set_option -vlog_std v2001 set_option -project_relative_includes 1 +#set constraint files +set_option -constraint -clear + #device options set_option -technology LATTICE-ECP3 set_option -part LFE3_150EA @@ -126,7 +135,7 @@ set_option -part_companion "" set_option -top_module "trb3_periph_sodasource" # mapper_options -set_option -frequency auto +set_option -frequency 200 set_option -write_verilog 0 set_option -write_vhdl 0 set_option -srs_instrumentation 1 @@ -136,7 +145,7 @@ set_option -maxfan 1000 set_option -disable_io_insertion 0 set_option -retiming 0 set_option -pipe 1 -set_option -forcegsr false +set_option -forcegsr auto set_option -fix_gated_and_generated_clocks 1 set_option -RWCheckOnRam 1 set_option -update_models_cp 0 diff --git a/source/med_ecp3_sfp_sync_down.vhd b/source/med_ecp3_sfp_sync_down.vhd index 081b957..7c60bff 100644 --- a/source/med_ecp3_sfp_sync_down.vhd +++ b/source/med_ecp3_sfp_sync_down.vhd @@ -19,6 +19,9 @@ entity med_ecp3_sfp_sync_down is SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset + -- +-- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes PL! +-- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes PL! --Internal Connection TX MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -31,6 +34,8 @@ entity med_ecp3_sfp_sync_down is MED_READ_IN : in std_logic; CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz + CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz + CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz --Sync operation RX_DLM : out std_logic := '0'; @@ -95,6 +100,10 @@ end component; +--signal refclk_p_in_S : std_logic; --PL! +--signal refclk_n_in_S : std_logic; --PL! +--signal refclk2core_S : std_logic; --PL! + signal clk_200_i : std_logic; signal clk_200_internal : std_logic; signal clk_rx_full : std_logic; @@ -165,9 +174,12 @@ signal start_timer : unsigned(18 downto 0) := (others => '0'); begin -clk_200_internal <= CLK; -CLK_RX_HALF_OUT <= clk_rx_half; -CLK_RX_FULL_OUT <= clk_rx_full; +clk_200_internal <= CLK; + +CLK_RX_HALF_OUT <= clk_rx_half; +CLK_RX_FULL_OUT <= clk_rx_full; +CLK_TX_HALF_OUT <= clk_tx_half; +CLK_TX_FULL_OUT <= clk_tx_full; @@ -193,11 +205,13 @@ end generate; ------------------------------------------------- THE_SERDES : entity work.serdes_sync_downstream port map( +-- refclkp => PCSA_REFCLKP, -- external refclock straight into serdes PL! +-- refclkn => PCSA_REFCLKN, -- external refclock straight into serdes PL! hdinp_ch0 => SD_RXD_P_IN, hdinn_ch0 => SD_RXD_N_IN, hdoutp_ch0 => SD_TXD_P_OUT, hdoutn_ch0 => SD_TXD_N_OUT, --- rxiclk_ch0 => clk_200_i, + rxiclk_ch0 => clk_200_i, txiclk_ch0 => clk_200_i, rx_full_clk_ch0 => clk_rx_full, rx_half_clk_ch0 => clk_rx_half, @@ -223,7 +237,8 @@ THE_SERDES : entity work.serdes_sync_downstream lsm_status_ch0_s => lsm_status, rx_cdr_lol_ch0_s => rx_cdr_lol, tx_div2_mode_ch0_c => '0', - rx_div2_mode_ch0_c => '0', + rx_div2_mode_ch0_c => '0', + refclk2fpga => open, --refclk2core_S, SCI_WRDATA => sci_data_in_i, SCI_RDDATA => sci_data_out_i, diff --git a/source/med_ecp3_sfp_sync_up.vhd b/source/med_ecp3_sfp_sync_up.vhd index b479536..80c333e 100644 --- a/source/med_ecp3_sfp_sync_up.vhd +++ b/source/med_ecp3_sfp_sync_up.vhd @@ -70,14 +70,13 @@ end entity; architecture med_ecp3_sfp_sync_up_arch of med_ecp3_sfp_sync_up is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of med_ecp3_sfp_sync_up_arch : architecture is "media_interface_group"; - attribute syn_sharing : string; - attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off"; +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of med_ecp3_sfp_sync_up_arch : architecture is "media_uplink_group"; +attribute syn_sharing : string; +attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off"; - component DCS -- synthesis translate_off @@ -134,6 +133,30 @@ signal sci_write_i : std_logic; signal sci_write_shift_i : std_logic_vector(2 downto 0); signal sci_read_shift_i : std_logic_vector(2 downto 0); +-- fix signal names for constraining +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_preserve of sci_ch_i : signal is true; +attribute syn_keep of sci_ch_i : signal is true; +attribute syn_preserve of sci_qd_i : signal is true; +attribute syn_keep of sci_qd_i : signal is true; +attribute syn_preserve of sci_reg_i : signal is true; +attribute syn_keep of sci_reg_i : signal is true; +attribute syn_preserve of sci_addr_i : signal is true; +attribute syn_keep of sci_addr_i : signal is true; +attribute syn_preserve of sci_data_in_i : signal is true; +attribute syn_keep of sci_data_in_i : signal is true; +attribute syn_preserve of sci_data_out_i : signal is true; +attribute syn_keep of sci_data_out_i : signal is true; +attribute syn_preserve of sci_read_i : signal is true; +attribute syn_keep of sci_read_i : signal is true; +attribute syn_preserve of sci_write_i : signal is true; +attribute syn_keep of sci_write_i : signal is true; +attribute syn_preserve of sci_write_shift_i : signal is true; +attribute syn_keep of sci_write_shift_i : signal is true; +attribute syn_preserve of sci_read_shift_i : signal is true; +attribute syn_keep of sci_read_shift_i : signal is true; + signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; signal tx_allow : std_logic; @@ -197,6 +220,7 @@ THE_SERDES : entity work.serdes_sync_upstream hdinn_ch0 => SD_RXD_N_IN, hdoutp_ch0 => SD_TXD_P_OUT, hdoutn_ch0 => SD_TXD_N_OUT, + rxiclk_ch0 => clk_200_i, txiclk_ch0 => clk_200_i, rx_full_clk_ch0 => clk_rx_full, rx_half_clk_ch0 => clk_rx_half, @@ -246,7 +270,7 @@ THE_SERDES : entity work.serdes_sync_upstream THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n, - RX_REFCLK => clk_200_internal, -- allways running PL! + RX_REFCLK => clk_200_i, --nternal, -- allways running PL! TX_PLL_LOL_QD_S => tx_pll_lol, RX_SERDES_RST_CH_C => rx_serdes_rst, RX_CDR_LOL_CH_S => rx_cdr_lol, @@ -259,7 +283,7 @@ THE_RX_FSM : rx_reset_fsm THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n, - TX_REFCLK => clk_200_internal, -- allways running PL! + TX_REFCLK => clk_200_i, --nternal, -- allways running PL! TX_PLL_LOL_QD_S => tx_pll_lol, RST_QD_C => rst_qd, TX_PCS_RST_CH_C => tx_pcs_rst, diff --git a/source/serdes_sync_downstream.ipx b/source/serdes_sync_downstream.ipx index 3a9db77..220861b 100644 --- a/source/serdes_sync_downstream.ipx +++ b/source/serdes_sync_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/source/serdes_sync_downstream.lpc b/source/serdes_sync_downstream.lpc index 687f5e4..1b33f89 100644 --- a/source/serdes_sync_downstream.lpc +++ b/source/serdes_sync_downstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=10/02/2013 -Time=10:05:42 +Date=12/23/2013 +Time=10:40:48 [Parameters] Verilog=0 @@ -91,7 +91,7 @@ _rx_data_width0=8 _rx_data_width1=8 _rx_data_width2=8 _rx_data_width3=8 -_rx_fifo0=DISABLED +_rx_fifo0=ENABLED _rx_fifo1=ENABLED _rx_fifo2=ENABLED _rx_fifo3=ENABLED @@ -243,11 +243,11 @@ _rx_los_port1=Internal _rx_los_port2=Internal _rx_los_port3=Internal _sci_ports=ENABLED -_sci_int_port=ENABLED -_refck2core=DISABLED +_sci_int_port=DISABLED +_refck2core=ENABLED Regen=auto PAR1=0 -PARTrace1=0 +PARTrace1=1 PAR3=0 PARTrace3=0 diff --git a/source/serdes_sync_downstream.txt b/source/serdes_sync_downstream.txt index 5883a95..42ee441 100644 --- a/source/serdes_sync_downstream.txt +++ b/source/serdes_sync_downstream.txt @@ -20,7 +20,7 @@ CH0_TX_DATA_RATE "FULL" CH0_TX_DATA_WIDTH "8" CH0_RX_DATA_WIDTH "8" CH0_TX_FIFO "ENABLED" -CH0_RX_FIFO "DISABLED" +CH0_RX_FIFO "ENABLED" CH0_TDRV "0" #CH0_TX_FICLK_RATE 200 #CH0_RXREFCLK_RATE "200" @@ -52,7 +52,7 @@ CCLMARK "7" CH0_SSLB "DISABLED" CH0_SPLBPORTS "DISABLED" CH0_PCSLBPORTS "DISABLED" -INT_ALL "ENABLED" -QD_REFCK2CORE "DISABLED" +INT_ALL "DISABLED" +QD_REFCK2CORE "ENABLED" diff --git a/source/serdes_sync_downstream.vhd b/source/serdes_sync_downstream.vhd index 7070523..301b2c5 100644 --- a/source/serdes_sync_downstream.vhd +++ b/source/serdes_sync_downstream.vhd @@ -1538,6 +1538,7 @@ entity serdes_sync_downstream is hdinp_ch0, hdinn_ch0 : in std_logic; hdoutp_ch0, hdoutn_ch0 : out std_logic; sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; txiclk_ch0 : in std_logic; rx_full_clk_ch0 : out std_logic; rx_half_clk_ch0 : out std_logic; @@ -1574,11 +1575,11 @@ entity serdes_sync_downstream is sci_sel_quad : in std_logic; sci_rd : in std_logic; sci_wrn : in std_logic; - sci_int : out std_logic; fpga_txrefclk : in std_logic; tx_serdes_rst_c : in std_logic; tx_pll_lol_qd_s : out std_logic; rst_qd_c : in std_logic; + refclk2fpga : out std_logic; serdes_rst_qd_c : in std_logic); end serdes_sync_downstream; @@ -2136,6 +2137,8 @@ end component; attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_REFCK2CORE: string; + attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200"; attribute black_box_pad_pin: string; attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; @@ -2166,6 +2169,7 @@ begin vlo_inst : VLO port map(Z => fpsc_vlo); vhi_inst : VHI port map(Z => fpsc_vhi); + refclk2fpga <= refclk2fpga_sig; rx_los_low_ch0_s <= rx_los_low_ch0_sig; rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; @@ -2198,7 +2202,7 @@ port map ( PCIE_PHYSTATUS_0 => open, SCISELCH0 => sci_sel_ch0, SCIENCH0 => fpsc_vhi, - FF_RXI_CLK_0 => fpsc_vlo, + FF_RXI_CLK_0 => rxiclk_ch0, FF_TXI_CLK_0 => txiclk_ch0, FF_EBRD_CLK_0 => fpsc_vlo, FF_RX_F_CLK_0 => rx_full_clk_ch0, @@ -2636,7 +2640,7 @@ port map ( SCIRD => sci_rd, SCIWSTN => sci_wrn, CYAWSTN => fpsc_vlo, - SCIINT => sci_int, + SCIINT => open, FFC_CK_CORE_TX => fpga_txrefclk, FFC_MACRO_RST => serdes_rst_qd_c, FFC_QUAD_RST => rst_qd_c, diff --git a/source/serdes_sync_upstream.ipx b/source/serdes_sync_upstream.ipx index 0148d22..026cff9 100644 --- a/source/serdes_sync_upstream.ipx +++ b/source/serdes_sync_upstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/source/serdes_sync_upstream.lpc b/source/serdes_sync_upstream.lpc index 6abc82d..7526f9f 100644 --- a/source/serdes_sync_upstream.lpc +++ b/source/serdes_sync_upstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_upstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=10/02/2013 -Time=09:44:23 +Date=12/24/2013 +Time=11:32:48 [Parameters] Verilog=0 @@ -39,10 +39,10 @@ _ldr0=DISABLED _ldr1=DISABLED _ldr2=DISABLED _ldr3=DISABLED -_datarange=2 +_datarange=2.0 _pll_txsrc=INTERNAL _refclk_mult=10X -_refclk_rate=200 +_refclk_rate=200.0 _tx_protocol0=G8B10B _tx_protocol1=DISABLED _tx_protocol2=DISABLED @@ -59,10 +59,10 @@ _tx_fifo0=ENABLED _tx_fifo1=ENABLED _tx_fifo2=ENABLED _tx_fifo3=ENABLED -_tx_ficlk_rate0=200 -_tx_ficlk_rate1=200 -_tx_ficlk_rate2=200 -_tx_ficlk_rate3=200 +_tx_ficlk_rate0=200.0 +_tx_ficlk_rate1=200.0 +_tx_ficlk_rate2=200.0 +_tx_ficlk_rate3=200.0 _pll_rxsrc0=INTERNAL _pll_rxsrc1=EXTERNAL _pll_rxsrc2=EXTERNAL @@ -71,7 +71,7 @@ Multiplier0= Multiplier1= Multiplier2= Multiplier3= -_rx_datarange0=2 +_rx_datarange0=2.0 _rx_datarange1=2.5 _rx_datarange2=2.5 _rx_datarange3=2.5 @@ -83,7 +83,7 @@ _rx_data_rate0=FULL _rx_data_rate1=FULL _rx_data_rate2=FULL _rx_data_rate3=FULL -_rxrefclk_rate0=200 +_rxrefclk_rate0=200.0 _rxrefclk_rate1=250.0 _rxrefclk_rate2=250.0 _rxrefclk_rate3=250.0 @@ -91,11 +91,11 @@ _rx_data_width0=8 _rx_data_width1=8 _rx_data_width2=8 _rx_data_width3=8 -_rx_fifo0=DISABLED +_rx_fifo0=ENABLED _rx_fifo1=ENABLED _rx_fifo2=ENABLED _rx_fifo3=ENABLED -_rx_ficlk_rate0=200 +_rx_ficlk_rate0=200.0 _rx_ficlk_rate1=250.0 _rx_ficlk_rate2=250.0 _rx_ficlk_rate3=250.0 @@ -119,7 +119,7 @@ _rterm_rx0=50 _rterm_rx1=50 _rterm_rx2=50 _rterm_rx3=50 -_rx_dcc0=DC +_rx_dcc0=AC _rx_dcc1=AC _rx_dcc2=AC _rx_dcc3=AC diff --git a/source/serdes_sync_upstream.txt b/source/serdes_sync_upstream.txt index 5883a95..e488a33 100644 --- a/source/serdes_sync_upstream.txt +++ b/source/serdes_sync_upstream.txt @@ -14,22 +14,22 @@ PLL_SRC "REFCLK_CORE" TX_DATARATE_RANGE "MEDHIGH" CH0_RX_DATARATE_RANGE "MEDHIGH" REFCK_MULT "10X" -#REFCLK_RATE 200 +#REFCLK_RATE 200.0 CH0_RX_DATA_RATE "FULL" CH0_TX_DATA_RATE "FULL" CH0_TX_DATA_WIDTH "8" CH0_RX_DATA_WIDTH "8" CH0_TX_FIFO "ENABLED" -CH0_RX_FIFO "DISABLED" +CH0_RX_FIFO "ENABLED" CH0_TDRV "0" -#CH0_TX_FICLK_RATE 200 -#CH0_RXREFCLK_RATE "200" -#CH0_RX_FICLK_RATE 200 +#CH0_TX_FICLK_RATE 200.0 +#CH0_RXREFCLK_RATE "200.0" +#CH0_RX_FICLK_RATE 200.0 CH0_TX_PRE "DISABLED" CH0_RTERM_TX "50" CH0_RX_EQ "DISABLED" CH0_RTERM_RX "50" -CH0_RX_DCC "DC" +CH0_RX_DCC "AC" CH0_LOS_THRESHOLD_LO "2" PLL_TERM "50" PLL_DCC "AC" diff --git a/source/serdes_sync_upstream.vhd b/source/serdes_sync_upstream.vhd index af538de..539e0c5 100644 --- a/source/serdes_sync_upstream.vhd +++ b/source/serdes_sync_upstream.vhd @@ -1538,6 +1538,7 @@ entity serdes_sync_upstream is hdinp_ch0, hdinn_ch0 : in std_logic; hdoutp_ch0, hdoutn_ch0 : out std_logic; sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; txiclk_ch0 : in std_logic; rx_full_clk_ch0 : out std_logic; rx_half_clk_ch0 : out std_logic; @@ -2105,7 +2106,7 @@ end component; attribute CH0_CDR_SRC: string; attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200.000"; attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; @@ -2113,7 +2114,7 @@ end component; attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000"; attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100.000"; attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; @@ -2121,21 +2122,21 @@ end component; attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000"; attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200.000"; attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200.000"; attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200.000"; attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200.000"; attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100.000"; attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100.000"; attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100.000"; attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100.000"; attribute black_box_pad_pin: string; attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; @@ -2198,7 +2199,7 @@ port map ( PCIE_PHYSTATUS_0 => open, SCISELCH0 => sci_sel_ch0, SCIENCH0 => fpsc_vhi, - FF_RXI_CLK_0 => fpsc_vlo, + FF_RXI_CLK_0 => rxiclk_ch0, FF_TXI_CLK_0 => txiclk_ch0, FF_EBRD_CLK_0 => fpsc_vlo, FF_RX_F_CLK_0 => rx_full_clk_ch0, diff --git a/source/soda_client.vhd b/source/soda_client.vhd index fcae1d3..782a6ba 100644 --- a/source/soda_client.vhd +++ b/source/soda_client.vhd @@ -78,8 +78,8 @@ begin SUPER_BURST_NR_OUT => super_burst_nr_S, SODA_CMD_VALID_OUT => soda_cmd_valid_S, SODA_CMD_WORD_OUT => soda_cmd_word_S, - CRC_VALID_OUT => crc_valid_S, - CRC_DATA_OUT => crc_data_S, +-- CRC_VALID_OUT => crc_valid_S, +-- CRC_DATA_OUT => crc_data_S, RX_DLM_IN => RX_DLM_IN, RX_DLM_WORD_IN => RX_DLM_WORD_IN ); diff --git a/source/soda_client_synconstraints.fdc b/source/soda_client_synconstraints.fdc new file mode 100644 index 0000000..e9ff28d --- /dev/null +++ b/source/soda_client_synconstraints.fdc @@ -0,0 +1,66 @@ +################################################################################ +#### This file contains constraints from Synplicity SDC files that have been +#### translated into Synopsys FPGA Design Constraints (FDC). +#### Translated FDC output file: +#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc +#### client SDC files to the translation: +#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc +################################################################################ + + +###==== BEGIN Header + +# Synopsys, Inc. constraint file +# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc +# Written on Wed Dec 18 11:52:15 2013 +# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor + +# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. +# These sections are generated from SCOPE spreadsheet tabs. + +###==== END Header + + +################################################################################ +#### The following Synplicity constraints from file: +#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc +#### are disabled and have not been translated. +############################################################################## +# FDC constraints translated from Synplify Legacy Timing & Design Constraints +############################################################################## + +set_rtl_ff_names {} +###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) +define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable +define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable +define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable +define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable +###==== END Collections +###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) +create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0} +create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} +create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} +create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} +create_clock -name {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5} + + +#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} -period {10.0} -waveform {0 5.0} +#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} -period {5.0} -waveform {0 2.5} +set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} } +set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} } +#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} } +#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} } +###==== END Clocks +###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) +###==== END "Generated Clocks" +###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) +###==== END Inputs/Outputs +###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +###==== END "Delay Paths" +###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) +###==== END Attributes +###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) +###==== END "I/O Standards" +###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) +###==== END "Compile Points" + diff --git a/source/soda_components.vhd b/source/soda_components.vhd index d785556..67f81df 100644 --- a/source/soda_components.vhd +++ b/source/soda_components.vhd @@ -6,10 +6,14 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb_net16_hub_func.all; -use work.soda_components.all; + package soda_components is + attribute syn_useioff : boolean; + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + constant c_PHASE_L : std_logic := '0'; -- byt2word allignment of soda constant c_PHASE_H : std_logic := '1'; -- byt2word allignment of soda constant c_HUB_CHILDREN : natural range 1 to 4 := 2; -- number of children per soda-hub @@ -70,9 +74,9 @@ package soda_components is SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0'); SODA_CMD_VALID_OUT : out std_logic := '0'; SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0'); - EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - CRC_VALID_OUT : out std_logic := '0'; - CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); +-- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); +-- CRC_VALID_OUT : out std_logic := '0'; +-- CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); RX_DLM_IN : in std_logic; RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') ); @@ -271,6 +275,8 @@ component med_ecp3_sfp_sync_down is SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset +-- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes +-- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes --Internal Connection TX MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -283,6 +289,8 @@ component med_ecp3_sfp_sync_down is MED_READ_IN : in std_logic; CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz + CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz + CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz --Sync operation RX_DLM : out std_logic := '0'; diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd index 296afe7..7d31f23 100644 --- a/source/soda_packet_builder.vhd +++ b/source/soda_packet_builder.vhd @@ -142,7 +142,8 @@ begin when c_BST6 => packet_state_S <= c_BST7; soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= SUPER_BURST_NR_IN(7 downto 0); + soda_pkt_word_S <= SUPER_BURST_NR_IN(7 downto 0); + EXPECTED_REPLY_OUT <= SUPER_BURST_NR_IN(7 downto 0); when c_BST7 => packet_state_S <= c_BST8; soda_dlm_preview_S <= '0'; @@ -183,7 +184,8 @@ begin when c_CMD6 => packet_state_S <= c_CMD7; soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= soda_cmd_word_S(7 downto 0); + soda_pkt_word_S <= soda_cmd_word_S(7 downto 0); + EXPECTED_REPLY_OUT <= soda_cmd_word_S(7 downto 0); when c_CMD7 => if (crc_valid_S = '0') then packet_state_S <= c_ERROR; diff --git a/source/soda_packet_handler.vhd b/source/soda_packet_handler.vhd index 3b61b22..c070bc1 100644 --- a/source/soda_packet_handler.vhd +++ b/source/soda_packet_handler.vhd @@ -19,7 +19,7 @@ entity soda_packet_handler is SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0'); SODA_CMD_VALID_OUT : out std_logic := '0'; SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0'); - EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); +-- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); CRC_VALID_OUT : out std_logic := '0'; CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); RX_DLM_IN : in std_logic; @@ -38,14 +38,14 @@ architecture Behavioral of soda_packet_handler is ); signal packet_state_S : packet_state_type := c_IDLE; -- crc-checker signals -- - signal soc_S : std_logic; - signal eoc_S : std_logic; - signal crc_valid_in_s : std_logic; - signal crc_datain_S : std_logic_vector(7 downto 0) := (others => '0'); - signal crc_tmp_S : std_logic_vector(7 downto 0) := (others => '0'); - signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0'); - signal crc_valid_out_S : std_logic; - signal crc_check_ok_s : std_logic; +-- signal soc_S : std_logic; +-- signal eoc_S : std_logic; +-- signal crc_valid_in_s : std_logic; +-- signal crc_datain_S : std_logic_vector(7 downto 0) := (others => '0'); +-- signal crc_tmp_S : std_logic_vector(7 downto 0) := (others => '0'); +-- signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0'); +-- signal crc_valid_out_S : std_logic; +-- signal crc_check_ok_s : std_logic; begin @@ -158,7 +158,6 @@ begin soda_pkt_word_S(7 downto 0) <= RX_DLM_WORD_IN; -- get transmitted CRC when c_SODA_PKT8 => soda_pkt_valid_S <= '1'; - EXPECTED_REPLY_OUT <= soda_pkt_word_S(7 downto 0); if (soda_pkt_word_S(31)= '1') then START_OF_SUPERBURST_OUT <= '1'; SUPER_BURST_NR_OUT <= soda_pkt_word_S(30 downto 0); @@ -177,76 +176,75 @@ begin end if; end process; - crc_check_proc : process(SODACLK, packet_state_S) - begin - if rising_edge(SODACLK) then - case packet_state_S is - when c_RST=> - CRC_VALID_OUT <= '0'; - CRC_DATA_OUT<= (others => '0'); - soc_S <= '1'; - eoc_S <= '0'; - CRC_VALID_OUT <= '0'; - when c_IDLE => - CRC_VALID_OUT <= '0'; - CRC_DATA_OUT<= (others => '0'); - crc_valid_in_S<= '0'; - crc_datain_S<= (others=>'0'); - soc_S <= '1'; - eoc_S <= '0'; - when c_SODA_PKT1=> - crc_valid_in_S<= '1'; - crc_datain_S<=RX_DLM_WORD_IN; - if (RX_DLM_WORD_IN(7)='0') then -- only calculate crc if it's a command packet - soc_S <= '0'; - end if; - when c_SODA_PKT2=> - crc_valid_in_S<= '0'; - crc_datain_S<= (others=>'0'); - when c_SODA_PKT3=> - crc_valid_in_S<= '1'; - crc_datain_S<= RX_DLM_WORD_IN; - when c_SODA_PKT4=> - crc_valid_in_S<= '0'; - crc_datain_S<= (others=>'0'); - when c_SODA_PKT5=> - crc_valid_in_S<= '1'; - crc_datain_S<= RX_DLM_WORD_IN; - if (soc_S='0') then -- only terminate crc claculation if it is running - eoc_S <= '1'; - end if; - when c_SODA_PKT6=> - crc_valid_in_S<= '0'; - crc_datain_S<= (others=>'0'); - eoc_S <= '0'; - when c_SODA_PKT7=> - crc_valid_in_S<= '0'; - crc_datain_S<= (others=>'0'); - if ((crc_valid_out_S = '1') and (crc_out_S = RX_DLM_WORD_IN)) then - crc_check_ok_S<= '1'; - else - crc_check_ok_S<= '0'; - end if; - CRC_VALID_OUT <= '1'; - when c_SODA_PKT8=> - CRC_VALID_OUT <= crc_valid_out_S; - CRC_DATA_OUT<= crc_out_S; - crc_valid_in_S<= '0'; - crc_datain_S<= (others=>'0'); ---soc_S <= '0'; - eoc_S <= '0'; - crc_check_ok_S<= '0'; - CRC_VALID_OUT <= '0'; - when others => - CRC_VALID_OUT <= '0'; - CRC_DATA_OUT<= (others => '0'); - crc_valid_in_S<= '0'; - crc_datain_S<= (others=>'0'); - soc_S <= '0'; - eoc_S <= '0'; - CRC_VALID_OUT <= '0'; - end case; - end if; - end process; + --crc_check_proc : process(SODACLK, packet_state_S) + --begin + --if rising_edge(SODACLK) then + --case packet_state_S is + --when c_RST=> + --CRC_VALID_OUT <= '0'; + --CRC_DATA_OUT<= (others => '0'); + --soc_S <= '1'; + --eoc_S <= '0'; + --CRC_VALID_OUT <= '0'; + --when c_IDLE => + --CRC_VALID_OUT <= '0'; + --CRC_DATA_OUT<= (others => '0'); + --crc_valid_in_S<= '0'; + --crc_datain_S<= (others=>'0'); + --soc_S <= '1'; + --eoc_S <= '0'; + --when c_SODA_PKT1=> + --crc_valid_in_S<= '1'; + --crc_datain_S<=RX_DLM_WORD_IN; + --if (RX_DLM_WORD_IN(7)='0') then -- only calculate crc if it's a command packet + --soc_S <= '0'; + --end if; + --when c_SODA_PKT2=> + --crc_valid_in_S<= '0'; + --crc_datain_S<= (others=>'0'); + --when c_SODA_PKT3=> + --crc_valid_in_S<= '1'; + --crc_datain_S<= RX_DLM_WORD_IN; + --when c_SODA_PKT4=> + --crc_valid_in_S<= '0'; + --crc_datain_S<= (others=>'0'); + --when c_SODA_PKT5=> + --crc_valid_in_S<= '1'; + --crc_datain_S<= RX_DLM_WORD_IN; + --if (soc_S='0') then -- only terminate crc calculation if it is running + --eoc_S <= '1'; + --end if; + --when c_SODA_PKT6=> + --crc_valid_in_S<= '0'; + --crc_datain_S<= (others=>'0'); + --eoc_S <= '0'; + --when c_SODA_PKT7=> + --crc_valid_in_S<= '0'; + --crc_datain_S<= (others=>'0'); + --if ((crc_valid_out_S = '1') and (crc_out_S = RX_DLM_WORD_IN)) then + --crc_check_ok_S<= '1'; + --else + --crc_check_ok_S<= '0'; + --end if; + --CRC_VALID_OUT <= '1'; + --when c_SODA_PKT8=> + --CRC_VALID_OUT <= crc_valid_out_S; + --CRC_DATA_OUT<= crc_out_S; + --crc_valid_in_S<= '0'; + --crc_datain_S<= (others=>'0'); + --eoc_S <= '0'; + --crc_check_ok_S<= '0'; + --CRC_VALID_OUT <= '0'; + --when others => + --CRC_VALID_OUT <= '0'; + --CRC_DATA_OUT<= (others => '0'); + --crc_valid_in_S<= '0'; + --crc_datain_S<= (others=>'0'); + --soc_S <= '0'; + --eoc_S <= '0'; + --CRC_VALID_OUT <= '0'; + --end case; + --end if; + --end process; end architecture; \ No newline at end of file diff --git a/soda_source/soda_source_synconstraints.fdc b/source/soda_source_synconstraints.fdc similarity index 56% rename from soda_source/soda_source_synconstraints.fdc rename to source/soda_source_synconstraints.fdc index 9d02335..d1ccd96 100644 --- a/soda_source/soda_source_synconstraints.fdc +++ b/source/soda_source_synconstraints.fdc @@ -15,15 +15,16 @@ ###==== END Collections ###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock -name {clk_raw_internal} {n:gen_200_PLL\.THE_MAIN_PLL.CLKOK} -period {5} - -create_clock -name {clk_sys_internal} {n:gen_200_PLL\.THE_MAIN_PLL.CLKOP} -period {10} -create_clock -name {serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} -period {10} -create_clock -name {serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} -period {5} -set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_0} -group { {c:serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} } -set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_1} -group { {c:serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} } -set_clock_groups -derive -asynchronous -name {raw_internal} -group { {c:clk_raw_internal} } -set_clock_groups -derive -asynchronous -name {sys_internal} -group { {c:clk_sys_internal} } +create_clock -name {rx_clk_half} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10} +create_clock -name {rx_clk_full} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5} + +#create_clock -name {clk_sys_internal} {n:gen_200_PLL\.THE_MAIN_PLL.CLKOP} -period {10} +#create_clock -name {serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} -period {10} +#create_clock -name {serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} -period {5} +#set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_0} -group { {c:serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} } +#set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_1} -group { {c:serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} } +#set_clock_groups -derive -asynchronous -name {raw_internal} -group { {c:clk_raw_internal} } +#set_clock_groups -derive -asynchronous -name {sys_internal} -group { {c:clk_sys_internal} } ###==== END Clocks ###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) diff --git a/source/trb3_periph_sodaclient.vhd b/source/trb3_periph_sodaclient.vhd index b3350f2..3625782 100644 --- a/source/trb3_periph_sodaclient.vhd +++ b/source/trb3_periph_sodaclient.vhd @@ -1,3 +1,7 @@ +--------------- +-- TOP LEVEL -- +--------------- + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -106,13 +110,11 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is constant REGIO_NUM_STAT_REGS : integer := 0; constant REGIO_NUM_CTRL_REGS : integer := 2; - attribute syn_keep : boolean; - attribute syn_preserve : boolean; constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa --Clock / Reset - signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL +-- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. @@ -207,18 +209,42 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is signal soda_addr : std_logic_vector(3 downto 0); signal soda_leds : std_logic_vector(3 downto 0); - signal link_debug_in_S : std_logic_vector(31 downto 0); - signal general_reset_i : std_logic := '1'; + signal link_debug_in_S : std_logic_vector(31 downto 0); + signal general_reset_i : std_logic := '1'; - signal soda_counter_i : unsigned(3 downto 0); - attribute syn_keep of soda_counter_i : signal is true; + signal soda_counter_i : unsigned(3 downto 0); + attribute syn_keep of soda_counter_i : signal is true; + -- fix signal names for constraining + attribute syn_preserve of soda_rx_clock_full : signal is true; + attribute syn_keep of soda_rx_clock_full : signal is true; + attribute syn_preserve of soda_rx_clock_half : signal is true; + attribute syn_keep of soda_rx_clock_half : signal is true; +-- attribute syn_preserve of soda_tx_clock_full : signal is true; +-- attribute syn_keep of soda_tx_clock_full : signal is true; +-- attribute syn_preserve of soda_tx_clock_half : signal is true; +-- attribute syn_keep of soda_tx_clock_half : signal is true; + attribute syn_preserve of clk_sys_internal : signal is true; + attribute syn_keep of clk_sys_internal : signal is true; + attribute syn_preserve of clk_raw_internal : signal is true; + attribute syn_keep of clk_raw_internal : signal is true; + attribute syn_preserve of tx_dlm_i : signal is true; + attribute syn_keep of tx_dlm_i : signal is true; + attribute syn_preserve of rx_dlm_i : signal is true; + attribute syn_keep of rx_dlm_i : signal is true; + begin --------------------------------------------------------------------------- -- Reset Generation --------------------------------------------------------------------------- - - GSR_N <= pll_lock; + + + TEST_LINE <= (others => '0'); -- otherwise it is floating + LED_RX <= (others => '0'); -- otherwise it is floating + LED_TX <= (others => '0'); -- otherwise it is floating + LED_LINKOK <= (others => '0'); -- otherwise it is floating + + GSR_N <= pll_lock; THE_RESET_HANDLER : trb_net_reset_handler generic map( @@ -228,7 +254,7 @@ begin CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_sys_i, -- PLL/DLL remastered clock + SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) @@ -237,9 +263,9 @@ begin DEBUG_OUT => open ); - process(clk_sys_i) + process(clk_sys_internal) begin - if rising_edge(clk_sys_i) then + if rising_edge(clk_sys_internal) then general_reset_i <= not SFP_LOS(1); end if; end process; @@ -263,14 +289,14 @@ gen_125 : if USE_125_MHZ = c_YES generate end generate; gen_sync_clocks : if SYNC_MODE = c_YES generate - clk_sys_i <= clk_sys_internal; +-- clk_sys_i <= clk_sys_internal; clk_soda_i <= soda_rx_clock_full; -- clk_200_i <= soda_rx_clock_full; end generate; gen_local_clocks : if SYNC_MODE = c_NO generate - clk_sys_i <= clk_sys_internal; - clk_soda_i <= clk_sys_internal; +-- clk_sys_i <= clk_sys_internal; + clk_soda_i <= clk_raw_internal; -- clk_200_i <= clk_raw_internal; end generate; @@ -302,7 +328,7 @@ end generate; HEADER_BUFFER_FULL_THRESH => 256 ) port map( - CLK => clk_sys_i, + CLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, CLK_EN => '1', MED_DATAREADY_OUT => med_dataready_out(0), @@ -346,7 +372,7 @@ end generate; FEE_DATA_ALMOST_FULL_OUT(0) => open, -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, @@ -398,7 +424,7 @@ end generate; PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 4, others => 0) ) port map( - CLK => clk_sys_i, + CLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, DAT_ADDR_IN => regio_addr_out, @@ -466,7 +492,7 @@ end generate; THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch port map( - CLK_IN => clk_sys_i, + CLK_IN => clk_sys_internal, --clk_sys_i, RESET_IN => reset_i, BUS_ADDR_IN => spimem_addr, @@ -500,7 +526,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up ) port map( CLK => clk_raw_internal, --clk_200_i, - SYSCLK => clk_sys_i, + SYSCLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, CLEAR => clear_i, --Internal Connection for TrbNet data -> not used a.t.m. @@ -551,7 +577,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up A_SODA_CLIENT : soda_client port map( - SYSCLK => clk_sys_i, + SYSCLK => clk_sys_internal, --clk_sys_i, SODACLK => clk_soda_i, RESET => reset_i, CLEAR => clear_i, @@ -597,10 +623,11 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- - process - begin - wait until rising_edge(clk_sys_internal); - time_counter <= time_counter + 1; + clock_counter_proc : process(clk_sys_internal) + begin + if rising_edge(clk_sys_internal) then + time_counter <= time_counter + 1; + end if; end process; process(clk_soda_i) diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd index 639e5c0..22c620e 100644 --- a/source/trb3_periph_sodasource.vhd +++ b/source/trb3_periph_sodasource.vhd @@ -30,7 +30,10 @@ entity trb3_periph_sodasource is --TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out --Serdes Clocks - do not use --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible - --CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + --CLK_SERDES_INT_RIGHT_P : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + --CLK_SERDES_INT_RIGHT_N : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + -- PCSA_REFCLKP : in std_logic; -- PL! external refclock straight into serdes + -- PCSA_REFCLKN : in std_logic; -- PL! external refclock straight into serdes --serdes I/O - connect as you like, no real use SERDES_ADDON_TX : out std_logic_vector(15 downto 0); @@ -112,8 +115,8 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is constant USE_200_MHZ : integer := 1 - USE_125_MHZ; --Clock / Reset - signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL --- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL +-- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL +-- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -209,6 +212,8 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is signal soda_rx_clock_half : std_logic; signal soda_rx_clock_full : std_logic; + signal soda_tx_clock_half : std_logic; + signal soda_tx_clock_full : std_logic; signal tx_dlm_i : std_logic; signal rx_dlm_i : std_logic; signal tx_dlm_word : std_logic_vector(7 downto 0); @@ -218,6 +223,36 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is --SODA signal SOB_S : std_logic := '0'; + -- fix signal names for constraining + attribute syn_preserve of CLK_GPLL_LEFT : signal is true; + attribute syn_keep of CLK_GPLL_LEFT : signal is true; +-- attribute syn_noprune of CLK_GPLL_LEFT : signal is true; + attribute syn_preserve of CLK_GPLL_RIGHT : signal is true; + attribute syn_keep of CLK_GPLL_RIGHT : signal is true; +-- attribute syn_noprune of CLK_GPLL_RIGHT : signal is true; + attribute syn_preserve of CLK_PCLK_LEFT : signal is true; + attribute syn_keep of CLK_PCLK_LEFT : signal is true; +-- attribute syn_noprune of CLK_PCLK_LEFT : signal is true; + attribute syn_preserve of CLK_PCLK_RIGHT : signal is true; + attribute syn_keep of CLK_PCLK_RIGHT : signal is true; +-- attribute syn_noprune of CLK_PCLK_RIGHT : signal is true; + +attribute syn_preserve of soda_rx_clock_full : signal is true; + attribute syn_keep of soda_rx_clock_full : signal is true; + attribute syn_preserve of soda_rx_clock_half : signal is true; + attribute syn_keep of soda_rx_clock_half : signal is true; + attribute syn_preserve of soda_tx_clock_full : signal is true; + attribute syn_keep of soda_tx_clock_full : signal is true; + attribute syn_preserve of soda_tx_clock_half : signal is true; + attribute syn_keep of soda_tx_clock_half : signal is true; + attribute syn_preserve of clk_sys_internal : signal is true; + attribute syn_keep of clk_sys_internal : signal is true; + attribute syn_preserve of clk_raw_internal : signal is true; + attribute syn_keep of clk_raw_internal : signal is true; + attribute syn_preserve of tx_dlm_i : signal is true; + attribute syn_keep of tx_dlm_i : signal is true; + attribute syn_preserve of rx_dlm_i : signal is true; + attribute syn_keep of rx_dlm_i : signal is true; begin @@ -235,7 +270,7 @@ begin CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_sys_i, -- PLL/DLL remastered clock + SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) @@ -249,13 +284,13 @@ begin -- Clock Handling --------------------------------------------------------------------------- gen_200_PLL : if USE_125_MHZ = c_NO generate - THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => CLK_GPLL_RIGHT, - CLKOP => clk_sys_internal, - CLKOK => clk_raw_internal, - LOCK => pll_lock - ); + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_sys_internal, + CLKOK => clk_raw_internal, + LOCK => pll_lock + ); end generate; gen_125 : if USE_125_MHZ = c_YES generate @@ -263,15 +298,17 @@ gen_125 : if USE_125_MHZ = c_YES generate clk_raw_internal <= CLK_GPLL_LEFT; end generate; -gen_sync_clocks : if SYNC_MODE = c_YES generate - clk_sys_i <= rx_clock_half; --- clk_200_i <= rx_clock_full; -end generate; +--gen_sync_clocks : if SYNC_MODE = c_YES generate +-- clk_sys_i <= soda_tx_clock_half; +-- clk_200_i <= soda_tx_clock_full; +-- clk_sys_internal <= soda_tx_clock_half; +-- clk_raw_internal <= soda_tx_clock_full; +--end generate; -gen_local_clocks : if SYNC_MODE = c_NO generate - clk_sys_i <= clk_sys_internal; --- clk_200_i <= clk_raw_internal; -end generate; +--gen_local_clocks : if SYNC_MODE = c_NO generate +-- clk_sys_i <= clk_sys_internal; +-- clk_200_i <= clk_raw_internal; +--end generate; --------------------------------------------------------------------------- @@ -288,7 +325,7 @@ end generate; ) port map( CLK => clk_raw_internal, - SYSCLK => clk_sys_i, + SYSCLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -304,7 +341,7 @@ end generate; REFCLK2CORE_OUT => open, CLK_RX_HALF_OUT => rx_clock_half, CLK_RX_FULL_OUT => rx_clock_full, - + --SFP Connection SD_RXD_P_IN => SERDES_ADDON_RX(2), SD_RXD_N_IN => SERDES_ADDON_RX(3), @@ -354,7 +391,7 @@ THE_HUB : trb_net16_hub_base CLOCK_FREQUENCY => CLOCK_FREQUENCY ) port map ( - CLK => clk_sys_i, + CLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, CLK_EN => '1', @@ -406,7 +443,7 @@ THE_HUB : trb_net16_hub_base PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0) ) port map( - CLK => clk_sys_i, + CLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, DAT_ADDR_IN => regio_addr_out, @@ -487,7 +524,7 @@ THE_HUB : trb_net16_hub_base THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch port map( - CLK_IN => clk_sys_i, + CLK_IN => clk_sys_internal, --clk_sys_i, RESET_IN => reset_i, BUS_ADDR_IN => spimem_addr, @@ -515,57 +552,61 @@ THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch --------------------------------------------------------------------------- THE_SYNC_LINK : med_ecp3_sfp_sync_down - generic map( - SERDES_NUM => 0, --number of serdes in quad - IS_SYNC_SLAVE => c_NO - ) - port map( - CLK => clk_raw_internal, --clk_200_i, - SYSCLK => clk_sys_i, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection for TrbNet data -> not used a.t.m. - MED_DATA_IN => med_data_out(31 downto 16), - MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3), - MED_DATAREADY_IN => med_dataready_out(1), - MED_READ_OUT => med_read_in(1), - MED_DATA_OUT => med_data_in(31 downto 16), - MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3), - MED_DATAREADY_OUT => med_dataready_in(1), - MED_READ_IN => med_read_out(1), - CLK_RX_HALF_OUT => soda_rx_clock_half, - CLK_RX_FULL_OUT => soda_rx_clock_full, - - RX_DLM => rx_dlm_i, - RX_DLM_WORD => rx_dlm_word, - TX_DLM => tx_dlm_i, - TX_DLM_WORD => tx_dlm_word, - TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL! - LINK_PHASE_OUT => link_phase_S, --PL! - --SFP Connection - SD_RXD_P_IN => SERDES_ADDON_RX(0), - SD_RXD_N_IN => SERDES_ADDON_RX(1), - SD_TXD_P_OUT => SERDES_ADDON_TX(0), - SD_TXD_N_OUT => SERDES_ADDON_TX(1), - SD_REFCLK_P_IN => '0', - SD_REFCLK_N_IN => '0', - SD_PRSNT_N_IN => SFP_MOD0(1), - SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => SFP_TXDIS(1), - - SCI_DATA_IN => sci2_data_in, - SCI_DATA_OUT => sci2_data_out, - SCI_ADDR => sci2_addr, - SCI_READ => sci2_read, - SCI_WRITE => sci2_write, - SCI_ACK => sci2_ack, - SCI_NACK => sci2_nack, - -- Status and control port - STAT_OP => med_stat_op(31 downto 16), - CTRL_OP => med_ctrl_op(31 downto 16), - STAT_DEBUG => open, - CTRL_DEBUG => (others => '0') - ); + generic map( + SERDES_NUM => 0, --number of serdes in quad + IS_SYNC_SLAVE => c_NO + ) + port map( + CLK => clk_raw_internal, --clk_200_i, + SYSCLK => clk_sys_internal, --clk_sys_i, + RESET => reset_i, + CLEAR => clear_i, +-- PCSA_REFCLKP => PCSA_REFCLKP, -- external refclock straight into serdes PL! +-- PCSA_REFCLKN => PCSA_REFCLKN, -- external refclock straight into serdes PL! + --Internal Connection for TrbNet data -> not used a.t.m. + MED_DATA_IN => med_data_out(31 downto 16), + MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3), + MED_DATAREADY_IN => med_dataready_out(1), + MED_READ_OUT => med_read_in(1), + MED_DATA_OUT => med_data_in(31 downto 16), + MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3), + MED_DATAREADY_OUT => med_dataready_in(1), + MED_READ_IN => med_read_out(1), + CLK_RX_HALF_OUT => soda_rx_clock_half, + CLK_RX_FULL_OUT => soda_rx_clock_full, + CLK_TX_HALF_OUT => soda_tx_clock_half, + CLK_TX_FULL_OUT => soda_tx_clock_full, + + RX_DLM => rx_dlm_i, + RX_DLM_WORD => rx_dlm_word, + TX_DLM => tx_dlm_i, + TX_DLM_WORD => tx_dlm_word, + TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL! + LINK_PHASE_OUT => link_phase_S, --PL! + --SFP Connection + SD_RXD_P_IN => SERDES_ADDON_RX(0), + SD_RXD_N_IN => SERDES_ADDON_RX(1), + SD_TXD_P_OUT => SERDES_ADDON_TX(0), + SD_TXD_N_OUT => SERDES_ADDON_TX(1), + SD_REFCLK_P_IN => '0', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => SFP_MOD0(1), + SD_LOS_IN => SFP_LOS(1), + SD_TXDIS_OUT => SFP_TXDIS(1), + + SCI_DATA_IN => sci2_data_in, + SCI_DATA_OUT => sci2_data_out, + SCI_ADDR => sci2_addr, + SCI_READ => sci2_read, + SCI_WRITE => sci2_write, + SCI_ACK => sci2_ack, + SCI_NACK => sci2_nack, + -- Status and control port + STAT_OP => med_stat_op(31 downto 16), + CTRL_OP => med_ctrl_op(31 downto 16), + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); --------------------------------------------------------------------------- @@ -574,7 +615,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down THE_SOB_SOURCE : soda_start_of_burst_faker port map( - SYSCLK => soda_rx_clock_half, --clk_raw_internal, + SYSCLK => clk_raw_internal, --soda_rx_clock_half, -- RESET => reset_i, SODA_BURST_PULSE_OUT => SOB_S ); @@ -583,7 +624,7 @@ THE_SOB_SOURCE : soda_start_of_burst_faker THE_SODA_SOURCE : soda_source port map( - SYSCLK => clk_sys_i, + SYSCLK => clk_sys_internal, --clk_sys_i, SODACLK => clk_raw_internal, RESET => reset_i, --Internal Connection -- 2.43.0