From eb4a4d43957f7cc3304e6d371c1cf2a5ad2ebc9e Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 30 Nov 2010 17:25:54 +0000 Subject: [PATCH] *** empty log message *** --- etrax_interface.vhd | 4 +- special/handler_lvl1.vhd | 16 ++++---- special/handler_trigger_and_data.vhd | 47 +++++++++++------------ special/trb2_control_endpoint_tlk.vhd | 22 ++++++++++- trb_net16_endpoint_hades_full_handler.vhd | 14 ++++--- trb_net_components.vhd | 3 ++ 6 files changed, 64 insertions(+), 42 deletions(-) diff --git a/etrax_interface.vhd b/etrax_interface.vhd index 9ebed91..3137620 100644 --- a/etrax_interface.vhd +++ b/etrax_interface.vhd @@ -80,7 +80,7 @@ begin MAKE_RESET: process (CLK) begin if rising_edge(CLK) then - if (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + if (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') or RESET = '1' then internal_reset_i <= '1'; else internal_reset_i <= '0'; @@ -107,7 +107,7 @@ begin DEPTH => 4 ) port map( - RESET => RESET, + RESET => '0', CLK0 => CLK, CLK1 => CLK, D_IN(0) => internal_reset_i, diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd index 26b565f..7586d8a 100644 --- a/special/handler_lvl1.vhd +++ b/special/handler_lvl1.vhd @@ -321,7 +321,7 @@ begin val_trg <= '0'; val_ttl_trg <= '0'; invalid_trg <= '0'; - data_valid <= '0'; + data_valid <= '0'; spurious_trg <= '0'; -- gk 11.09.10 missing_tmg <= '0'; -- gk 11.09.10 else @@ -334,7 +334,7 @@ begin val_trg <= next_val_trg; val_ttl_trg <= next_val_ttl_trg; invalid_trg <= next_invalid_trg; - data_valid <= next_data_valid; + data_valid <= next_data_valid; spurious_trg <= next_spurious_trg; -- gk 11.09.10 missing_tmg <= next_missing_tmg; -- gk 11.09.10 end if; @@ -365,21 +365,21 @@ begin -- timing trigger has a rising edge and valid length NEXT_STATE <= TRGFND; next_toc_rst <= '1'; - next_val_trg <= '1'; + next_val_trg <= '1'; elsif( (timing_trg_found = '0') and (LVL1_TRG_RECEIVED_IN = '1') and (LVL1_TRG_TYPE_IN(3) = '1') and (LVL1_TRG_INFORMATION_IN(7) = '1')) then -- timingtriggerless trigger found NEXT_STATE <= LVL1FND; next_toc_rst <= '1'; next_val_ttl_trg <= '1'; - next_data_valid <= '1'; + next_data_valid <= '1'; elsif( (timing_trg_found = '0') and (LVL1_TRG_RECEIVED_IN = '1') and ((LVL1_TRG_TYPE_IN(3) = '0') or (LVL1_TRG_INFORMATION_IN(7) = '0')) ) then -- missing timing trigger NEXT_STATE <= LVL1FND; --BADTRG; -- gk 11.09.10 next_invalid_trg <= '1'; next_missing_tmg <= '1'; - next_data_valid <= '1'; -- gk 11.09.10 + next_data_valid <= '1'; -- gk 11.09.10 else NEXT_STATE <= IDLE; end if; @@ -388,7 +388,7 @@ begin if (LVL1_TRG_RECEIVED_IN = '1') then -- suitable LVL1 information has arrived NEXT_STATE <= LVL1FND; - next_data_valid <= '1'; + next_data_valid <= '1'; next_toc_save <= '1'; next_toc_rst <= '1'; -- gk 11.09.10 @@ -435,7 +435,7 @@ begin when DONE => bsm_x <= x"7"; if( LVL1_TRG_RECEIVED_IN = '0' ) then NEXT_STATE <= IDLE; - next_data_valid <= '0'; + next_data_valid <= '0'; next_spurious_trg <= '0'; -- gk 11.09.10 next_missing_tmg <= '0'; -- gk 11.09.10 next_trg_rst <= '1'; -- gk 21.09.10 @@ -556,7 +556,7 @@ begin STATUS_OUT(11) <= timeout_found; STATUS_OUT(10 downto 8) <= (others => '0'); STATUS_OUT(3 downto 0) <= bsm_x; - + if (RESET = '1') or (RESET_STATS_IN = '1') then STATUS_OUT(7 downto 4) <= (others => '0'); STATUS_OUT(13) <= '0'; diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd index 5dfa2ac..58e94b9 100644 --- a/special/handler_trigger_and_data.vhd +++ b/special/handler_trigger_and_data.vhd @@ -69,7 +69,6 @@ entity handler_trigger_and_data is STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0); STATISTICS_READY_OUT : out std_logic; STATISTICS_READ_IN : in std_logic; - STATISTICS_ADDR_IN : in std_logic; STATISTICS_UNKNOWN_OUT : out std_logic; --Debug @@ -95,10 +94,10 @@ architecture handler_trigger_and_data_arch of handler_trigger_and_data is signal timer_fifo_almost_full : cnt24_DAT_t; signal timer_ipu_idle : unsigned(23 downto 0); signal timer_ipu_waiting : unsigned(23 downto 0); - signal timer_ipu_working : unsigned(23 downto 0); - signal timer_lvl1_almost_full : unsigned(23 downto 0); - signal timer_lvl1_idle : unsigned(23 downto 0); - signal timer_lvl1_working : unsigned(23 downto 0); + signal timer_ipu_working : unsigned(23 downto 0); + signal timer_lvl1_almost_full : unsigned(23 downto 0); + signal timer_lvl1_idle : unsigned(23 downto 0); + signal timer_lvl1_working : unsigned(23 downto 0); signal fee_timing_trigger : std_logic; signal fee_trg_received : std_logic; @@ -260,16 +259,16 @@ begin ----------------------------------------------------------------------- -- Statistics ----------------------------------------------------------------------- - the_stat_proc : process(CLK) + the_stat_proc : process(CLOCK) begin - if rising_edge(CLK) then + if rising_edge(CLOCK) then gen_buffer_stat : for i in 0 to DATA_INTERFACE_NUMBER-1 loop if STAT_DATA_BUFFER_LEVEL(i*32+17) = '1' and TIMER_TICKS_IN(0) = '1' then timer_fifo_almost_full(i) <= timer_fifo_almost_full(i) + to_unsigned(1,1); end if; end loop; if STAT_HEADER_BUFFER_LEVEL(17) = '1' and TIMER_TICKS_IN(0) = '1' then - timer_lvl1_almost_full <= timer_lvl1_almost_full(0) + to_unsigned(1,1); + timer_lvl1_almost_full <= timer_lvl1_almost_full + to_unsigned(1,1); end if; if STAT_HEADER_BUFFER_LEVEL(20) = '1' and TIMER_TICKS_IN(0) = '1' then timer_lvl1_idle <= timer_lvl1_idle + to_unsigned(1,1); @@ -280,9 +279,9 @@ begin end if; end process; - the_ipu_stat_proc : process(CLK) + the_ipu_stat_proc : process(CLOCK) begin - if rising_edge(CLK) then + if rising_edge(CLOCK) then if (status_ipu_handler_i(3 downto 0) = x"0") and TIMER_TICKS_IN(0) = '1' then timer_ipu_idle <= timer_ipu_idle + to_unsigned(1,1); @@ -296,26 +295,26 @@ begin timer_ipu_waiting <= timer_ipu_waiting + to_unsigned(1,1); end if; end if; - end process; + end process; - proc_read_stat : process(CLK) + proc_read_stat : process(CLOCK) variable addr : integer range 0 to 31; begin - if rising_edge(CLK) then - addr := integer(to_unsigned(STATISTICS_ADDR_IN)); + if rising_edge(CLOCK) then + addr := to_integer(unsigned(STATISTICS_ADDR_IN)); if STATISTICS_READ_IN = '1' then if addr < DATA_INTERFACE_NUMBER then - STATISTICS_DATA_OUT <= x"00" & timer_fifo_almost_full(addr); + STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_fifo_almost_full(addr)); STATISTICS_READY_OUT <= '1'; STATISTICS_UNKNOWN_OUT <= '0'; elsif addr >= 16 and addr <= 21 then case addr is - when 16 => STATISTICS_DATA_OUT <= x"00" & timer_lvl1_almost_full; - when 17 => STATISTICS_DATA_OUT <= x"00" & timer_lvl1_idle; - when 18 => STATISTICS_DATA_OUT <= x"00" & timer_lvl1_working; - when 19 => STATISTICS_DATA_OUT <= x"00" & timer_ipu_idle; - when 20 => STATISTICS_DATA_OUT <= x"00" & timer_ipu_working; - when 21 => STATISTICS_DATA_OUT <= x"00" & timer_ipu_waiting; + when 16 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_almost_full); + when 17 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_idle); + when 18 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_working); + when 19 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_idle); + when 20 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_working); + when 21 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_waiting); end case; STATISTICS_READY_OUT <= '1'; STATISTICS_UNKNOWN_OUT <= '0'; @@ -328,9 +327,9 @@ begin STATISTICS_UNKNOWN_OUT <= '0'; end if; end if; - end process; - - + end process; + + ----------------------------------------------------------------------- -- Debug ----------------------------------------------------------------------- diff --git a/special/trb2_control_endpoint_tlk.vhd b/special/trb2_control_endpoint_tlk.vhd index db2b095..d074ed1 100644 --- a/special/trb2_control_endpoint_tlk.vhd +++ b/special/trb2_control_endpoint_tlk.vhd @@ -115,6 +115,8 @@ end component; signal last_CTRL_REGS : std_logic_vector(15 downto 14); signal send_reset_counter : std_logic_vector(11 downto 0) := x"FFF"; + signal reset_interface : std_logic; + signal reset_interface_counter : std_logic_vector(31 downto 0); begin CLK <= VIRT_CLK; @@ -129,7 +131,7 @@ begin process(CLK) begin if rising_edge(CLK) then - if RESET_VIRT = '0' or send_reset_counter(10 downto 0) = "01111111111" then + if RESET_VIRT = '0' or send_reset_counter(10 downto 0) = "01111111111" or MED_STAT_OP(13) = '1' then --added trbnet reset RESET <= '1'; RESET_CNT <= "00"; else @@ -219,6 +221,20 @@ begin end process; + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or MED_ERROR_IN /= ERROR_OK then + reset_interface <= '1'; + reset_interface_counter <= (others => '0'); + elsif reset_interface_counter = x"00FFFFFF" then + reset_interface <= '0'; + else + reset_interface_counter <= reset_interface_counter + 1; + end if; + end if; + end process; + --------------------------------------------------------------------- --The Endpoint generating the connection to etrax-read/write/able registers --------------------------------------------------------------------- @@ -266,7 +282,7 @@ begin ) port map ( CLK => CLK, - RESET => RESET, + RESET => reset_interface, ETRAX_DATA_BUS_B => FS_PB, ETRAX_DATA_BUS_C => FS_PC, ETRAX_BUS_BUSY => etrax_state(0), @@ -282,6 +298,8 @@ begin STAT => EI_STAT ); + + --------------------------------------------------------------------- --Debugging Outputs --------------------------------------------------------------------- diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index 8e2b7c4..ec450d0 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -226,8 +226,9 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal stat_buffer_read : std_logic; signal stat_buffer_ready : std_logic; signal stat_buffer_unknown : std_logic; - - + signal stat_buffer_address : std_logic_vector(4 downto 0); + + begin --------------------------------------------------------------------------- -- TrbNet Endpoint @@ -430,7 +431,8 @@ begin BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66), BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78), BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195), - BUS_ADDR_OUT(111 downto 96)=> dummy(259 downto 244), + BUS_ADDR_OUT(100 downto 96)=> stat_buffer_address, + BUS_ADDR_OUT(111 downto 101)=> dummy(259 downto 249), BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT, BUS_TIMEOUT_OUT(1) => dummy(94), BUS_TIMEOUT_OUT(2) => dummy(95), @@ -470,7 +472,7 @@ begin BUS_UNKNOWN_ADDR_IN(3) => last_write_enable(3), BUS_UNKNOWN_ADDR_IN(4) => last_write_enable(4), BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5), - BUS_UNKNOWN_ADDR_IN(6) => stat_buffer_unknown + BUS_UNKNOWN_ADDR_IN(6) => stat_buffer_unknown ); proc_ack_strobes : process(CLK) @@ -541,9 +543,9 @@ begin STATISTICS_UNKNOWN_OUT => stat_buffer_unknown, STATISTICS_READY_OUT => stat_buffer_ready, STATISTICS_READ_IN => stat_buffer_read, - STATISTICS_ADDR_IN => BUS_ADDR_OUT(4 downto 0), + STATISTICS_ADDR_IN => stat_buffer_address, + - --Debug DEBUG_DATA_HANDLER_OUT => debug_data_handler_i, DEBUG_IPU_HANDLER_OUT => debug_ipu_handler_i diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 0e0edbf..11bc957 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -1109,6 +1109,9 @@ end component trb_net16_med_scm_sfp_gbe; TIMER_TICKS_IN : in std_logic_vector(1 downto 0); STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0); STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0); + STATISTICS_READY_OUT : out std_logic; + STATISTICS_READ_IN : in std_logic; + STATISTICS_UNKNOWN_OUT : out std_logic; --Debug DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0); -- 2.43.0