From ebd33565f35db03fb0f51e82323666be5b925c2c Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Mon, 23 Apr 2012 19:01:37 +0000
Subject: [PATCH] *** empty log message ***

---
 trb3/CodeRepository.tex     |  0
 trb3/Trb3GeneralRemarks.tex | 71 +++++++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+)
 create mode 100644 trb3/CodeRepository.tex
 create mode 100644 trb3/Trb3GeneralRemarks.tex

diff --git a/trb3/CodeRepository.tex b/trb3/CodeRepository.tex
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diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
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+\subsubsection{Hardware Information}
+\begin{itemize*}
+ \item Schematics \href{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/trbv3_SCHEMATIC_michael.pdf}{trbv3\_SCHEMATIC\_michael.pdf}
+ \item Pin-out file for the peripheral FPGAs \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph.lpf}{cvsroot/trb3/base/trb3\_periph.lpf}
+ \item Pin-out file for the central FPGAs \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_central.lpf}{cvsroot/trb3/base/trb3\_central.lpf}
+\end{itemize*}
+
+
+
+\subsubsection{Board Identification}
+The TRB3 boards are equipped with 5 temperature sensors, one for each FPGA. They contain a unique ID that is used to identify each FPGA. Additionally, the peripheral FPGAs have to bits identification (endpoint ID) corresponding to their position on the board.
+This information can be read out after the first initial programming of the FPGAs.
+
+The board itself has a sticker with a three-digit serial number to identify it (we are looking into a bright future of the TRB3 ;-)).
+The combination of serial number and unique ids is given in the file \filename{serials\_trb3.db} available in the main directory of the cvs repository. For each board it contains five lines
+
+\begin{verbatim}#SID  Unique ID
+0015  0x08000002e2e22b28
+0010  0xa6000002e2e2df28
+0011  0x51000002e2e22828
+0012  0x72000002e2eb4628
+0013  0xb0000002e311b928
+\end{verbatim}
+
+The first three digits of the SID is the serial number as written on the board, the fourth digit is an identifier for the FPGA number as printed on the PCB (central FPGA is FPGA 5, the others are numbered 1 to 4, but mapped to 0 to 3 in the file). Based on this file, a second file \filename{addresses.db} can be written for each individual set-up to assign each board the necessary network addresses.
+
+
+\subsubsection{Flash Programming}
+Typically only the first programming of a board is done with a JTAG cable, all later upgrades can be done directly via TrbNet to the Flash ROMs. The advantage is the increased speed (about a factor 10) and that no physical access to the board is necessary. The software needs some settings in the FPGA code to function properly:
+
+First, the name of the design has to contain a certain sub-string:
+\begin{description}
+ \item[trb3\_central or trb3\_fpga5] if the design is targeted to the central FPGA
+ \item[trb3\_periph or trb3\_fpga1234] if the design is targeted to either of the peripheral FPGA
+ \item[trb3\_fpgaN] were N is a number between 1 and 4 if the design should be loaded to a special FPGA only
+\end{description}
+
+Second, the TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} that has to be according to the following rules: The lower 16 Bit can be freely assigned, i.e. to mark different software revisions. The upper 16 Bit have to contain one of the following values:
+\begin{itemize*}
+ \item 0x9000 if the design is for the central FPGA
+ \item 0x9100 if the design is for either of the peripheral FPGAs
+ \item 0x9110 if the design is for FPGA 1 only
+ \item 0x9120 if the design is for FPGA 2 only
+ \item 0x9130 if the design is for FPGA 3 only
+ \item 0x9140 if the design is for FPGA 4 only
+\end{itemize*}
+
+These values are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs.
+
+
+\subsubsection{Network Addresses}
+All boards of a given type are accessible by a broadcast address at the same time. This is set by \signal{Broadcast\_Special\_Addr} in the TrbNet endpoint:
+\begin{itemize*}
+ \item 0x40 for the central FPGA
+ \item 0x45 for the peripheral FPGA
+ \item 0x41 for a design for FPGA 1 only
+ \item 0x42 for a design for FPGA 2 only
+ \item 0x43 for a design for FPGA 3 only
+ \item 0x44 for a design for FPGA 4 only
+\end{itemize*}
+
+The initial address set with \signal{Regio\_Init\_Address} can be chosen from the following set:
+\begin{itemize*}
+ \item 0xF300 for the central FPGA
+ \item 0xF305 for the peripheral FPGA
+ \item 0xF301 for a design for FPGA 1 only
+ \item 0xF302 for a design for FPGA 2 only
+ \item 0xF303 for a design for FPGA 3 only
+ \item 0xF304 for a design for FPGA 4 only
+\end{itemize*}
+
-- 
2.43.0