From ec541ea3f0f5c269759fe12aa38c5badff98f7f6 Mon Sep 17 00:00:00 2001 From: hadaq Date: Sun, 24 Mar 2013 22:53:14 +0000 Subject: [PATCH] geht nicht mit adc --- .../{compile_munich.pl => compile_munich2.pl} | 2 +- ...ifo_dc_9to36.vhd => fifo_dc_9to36_dyn.vhd} | 469 +++++++++++------- nxyter/source/nx_timestamp_fifo_read.vhd | 89 ++-- nxyter/source/nxyter.vhd | 92 +++- nxyter/source/nxyter_components.vhd | 70 ++- nxyter/source/registers.txt | 1 + nxyter/trb3_periph.prj | 19 +- nxyter/trb3_periph.vhd | 77 ++- 8 files changed, 568 insertions(+), 251 deletions(-) rename nxyter/{compile_munich.pl => compile_munich2.pl} (99%) rename nxyter/source/{fifo_dc_9to36.vhd => fifo_dc_9to36_dyn.vhd} (83%) diff --git a/nxyter/compile_munich.pl b/nxyter/compile_munich2.pl similarity index 99% rename from nxyter/compile_munich.pl rename to nxyter/compile_munich2.pl index 0be68b6..6b1526c 100755 --- a/nxyter/compile_munich.pl +++ b/nxyter/compile_munich2.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/new'; +my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.0'; my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; diff --git a/nxyter/source/fifo_dc_9to36.vhd b/nxyter/source/fifo_dc_9to36_dyn.vhd similarity index 83% rename from nxyter/source/fifo_dc_9to36.vhd rename to nxyter/source/fifo_dc_9to36_dyn.vhd index b4a3c60..38dc35e 100644 --- a/nxyter/source/fifo_dc_9to36.vhd +++ b/nxyter/source/fifo_dc_9to36_dyn.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) -- Module Version: 5.4 ---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 9 -depth 256 -rdata_width 36 -regout -pe -1 -pf -1 -e +--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 9 -depth 256 -rdata_width 36 -regout -no_enable -pe 0 -pf -1 -e --- Sat Nov 24 15:58:10 2012 +-- Sun Mar 24 00:15:23 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -11,7 +11,7 @@ library ecp3; use ecp3.components.all; -- synopsys translate_on -entity fifo_dc_9to36 is +entity fifo_dc_9to36_dyn is port ( Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; @@ -20,12 +20,14 @@ entity fifo_dc_9to36 is RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + AmEmptyThresh: in std_logic_vector(5 downto 0); Q: out std_logic_vector(35 downto 0); Empty: out std_logic; - Full: out std_logic); -end fifo_dc_9to36; + Full: out std_logic; + AlmostEmpty: out std_logic); +end fifo_dc_9to36_dyn; -architecture Structure of fifo_dc_9to36 is +architecture Structure of fifo_dc_9to36_dyn is -- internal signal declarations signal invout_1: std_logic; @@ -33,6 +35,7 @@ architecture Structure of fifo_dc_9to36 is signal wcount_r1: std_logic; signal wcount_r0: std_logic; signal w_g2b_xor_cluster_1: std_logic; + signal rcnt_reg_5_inv: std_logic; signal w_gdata_0: std_logic; signal w_gdata_1: std_logic; signal w_gdata_2: std_logic; @@ -111,9 +114,10 @@ architecture Structure of fifo_dc_9to36 is signal r_gcount_w5: std_logic; signal r_gcount_w26: std_logic; signal r_gcount_w6: std_logic; + signal rcnt_reg_6: std_logic; signal empty_i: std_logic; - signal rRst: std_logic; signal full_i: std_logic; + signal rRst: std_logic; signal iwcount_0: std_logic; signal iwcount_1: std_logic; signal w_gctr_ci: std_logic; @@ -130,7 +134,6 @@ architecture Structure of fifo_dc_9to36 is signal co4: std_logic; signal wcount_8: std_logic; signal co3: std_logic; - signal scuba_vhi: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; signal r_gctr_ci: std_logic; @@ -144,23 +147,36 @@ architecture Structure of fifo_dc_9to36 is signal co3_1: std_logic; signal rcount_6: std_logic; signal co2_1: std_logic; - signal rden_i: std_logic; + signal rcnt_sub_0: std_logic; + signal scuba_vhi: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_2: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_2: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_2: std_logic; + signal rcnt_sub_msb: std_logic; + signal co3_2d: std_logic; + signal co3_2: std_logic; signal cmp_ci: std_logic; signal wcount_r2: std_logic; signal wcount_r3: std_logic; signal rcount_0: std_logic; signal rcount_1: std_logic; - signal co0_2: std_logic; + signal co0_3: std_logic; signal wcount_r4: std_logic; signal w_g2b_xor_cluster_0: std_logic; signal rcount_2: std_logic; signal rcount_3: std_logic; - signal co1_2: std_logic; + signal co1_3: std_logic; signal wcount_r6: std_logic; signal wcount_r7: std_logic; signal rcount_4: std_logic; signal rcount_5: std_logic; - signal co2_2: std_logic; + signal co2_3: std_logic; signal empty_cmp_clr: std_logic; signal empty_cmp_set: std_logic; signal empty_d: std_logic; @@ -169,26 +185,41 @@ architecture Structure of fifo_dc_9to36 is signal cmp_ci_1: std_logic; signal wcount_0: std_logic; signal wcount_1: std_logic; - signal co0_3: std_logic; + signal co0_4: std_logic; signal rcount_w0: std_logic; signal rcount_w1: std_logic; signal wcount_2: std_logic; signal wcount_3: std_logic; - signal co1_3: std_logic; + signal co1_4: std_logic; signal rcount_w2: std_logic; signal r_g2b_xor_cluster_0: std_logic; signal wcount_4: std_logic; signal wcount_5: std_logic; - signal co2_3: std_logic; + signal co2_4: std_logic; signal rcount_w4: std_logic; signal rcount_w5: std_logic; signal wcount_6: std_logic; signal wcount_7: std_logic; - signal co3_2: std_logic; + signal co3_3: std_logic; signal full_cmp_clr: std_logic; signal full_cmp_set: std_logic; signal full_d: std_logic; signal full_d_c: std_logic; + signal rden_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_5: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_5: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_5: std_logic; + signal ae_clrsig: std_logic; + signal ae_setsig: std_logic; + signal ae_d: std_logic; + signal ae_d_c: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -208,6 +239,11 @@ architecture Structure of fifo_dc_9to36 is B1: in std_logic; CI: in std_logic; COUT: out std_logic; S0: out std_logic; S1: out std_logic); end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; component FD1P3BX port (D: in std_logic; SP: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); @@ -311,15 +347,23 @@ architecture Structure of fifo_dc_9to36 is attribute MEM_INIT_FILE : string; attribute RESETMODE : string; attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "fifo_dc_9to36.lpc"; + attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "fifo_dc_9to36_dyn.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is ""; attribute RESETMODE of pdp_ram_0_0_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "fifo_dc_9to36.lpc"; + attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "fifo_dc_9to36_dyn.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is ""; attribute RESETMODE of pdp_ram_0_1_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "fifo_dc_9to36.lpc"; + attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "fifo_dc_9to36_dyn.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is ""; attribute RESETMODE of pdp_ram_0_2_0 : label is "SYNC"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; attribute GSR of FF_81 : label is "ENABLED"; attribute GSR of FF_80 : label is "ENABLED"; attribute GSR of FF_79 : label is "ENABLED"; @@ -406,61 +450,61 @@ architecture Structure of fifo_dc_9to36 is begin -- component instantiation statements - AND2_t16: AND2 + AND2_t19: AND2 port map (A=>WrEn, B=>invout_1, Z=>wren_i); - INV_1: INV + INV_2: INV port map (A=>full_i, Z=>invout_1); - AND2_t15: AND2 + AND2_t18: AND2 port map (A=>RdEn, B=>invout_0, Z=>rden_i); - INV_0: INV + INV_1: INV port map (A=>empty_i, Z=>invout_0); - OR2_t14: OR2 + OR2_t17: OR2 port map (A=>Reset, B=>RPReset, Z=>rRst); - XOR2_t13: XOR2 + XOR2_t16: XOR2 port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - XOR2_t12: XOR2 + XOR2_t15: XOR2 port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - XOR2_t11: XOR2 + XOR2_t14: XOR2 port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - XOR2_t10: XOR2 + XOR2_t13: XOR2 port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - XOR2_t9: XOR2 + XOR2_t12: XOR2 port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - XOR2_t8: XOR2 + XOR2_t11: XOR2 port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - XOR2_t7: XOR2 + XOR2_t10: XOR2 port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - XOR2_t6: XOR2 + XOR2_t9: XOR2 port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - XOR2_t5: XOR2 + XOR2_t8: XOR2 port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - XOR2_t4: XOR2 + XOR2_t7: XOR2 port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - XOR2_t3: XOR2 + XOR2_t6: XOR2 port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - XOR2_t2: XOR2 + XOR2_t5: XOR2 port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - XOR2_t1: XOR2 + XOR2_t4: XOR2 port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - XOR2_t0: XOR2 + XOR2_t3: XOR2 port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); LUT4_18: ROM16X1A @@ -541,6 +585,9 @@ begin port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0); + XOR2_t2: XOR2 + port map (A=>w_gcount_r28, B=>rcount_6, Z=>rcnt_sub_msb); + LUT4_3: ROM16X1A generic map (initval=> X"0410") port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28, @@ -561,6 +608,15 @@ begin port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>full_cmp_clr); + INV_0: INV + port map (A=>rcnt_reg_5, Z=>rcnt_reg_5_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_6, B=>rcnt_reg_5_inv, Z=>ae_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_6, B=>rcnt_reg_5, Z=>ae_setsig); + pdp_ram_0_0_2: DP16KC generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", @@ -588,17 +644,17 @@ begin ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn, - WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), - DOB3=>Q(3), DOB4=>Q(9), DOB5=>Q(10), DOB6=>Q(11), - DOB7=>Q(12), DOB8=>open, DOB9=>Q(18), DOB10=>Q(19), - DOB11=>Q(20), DOB12=>Q(21), DOB13=>Q(27), DOB14=>Q(28), - DOB15=>Q(29), DOB16=>Q(30), DOB17=>open); + ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, + OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(9), DOB5=>Q(10), + DOB6=>Q(11), DOB7=>Q(12), DOB8=>open, DOB9=>Q(18), + DOB10=>Q(19), DOB11=>Q(20), DOB12=>Q(21), DOB13=>Q(27), + DOB14=>Q(28), DOB15=>Q(29), DOB16=>Q(30), DOB17=>open); pdp_ram_0_1_1: DP16KC generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", @@ -627,17 +683,17 @@ begin ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn, - WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6), - DOB3=>Q(7), DOB4=>Q(13), DOB5=>Q(14), DOB6=>Q(15), - DOB7=>Q(16), DOB8=>open, DOB9=>Q(22), DOB10=>Q(23), - DOB11=>Q(24), DOB12=>Q(25), DOB13=>Q(31), DOB14=>Q(32), - DOB15=>Q(33), DOB16=>Q(34), DOB17=>open); + ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, + OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), + DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>Q(13), DOB5=>Q(14), + DOB6=>Q(15), DOB7=>Q(16), DOB8=>open, DOB9=>Q(22), + DOB10=>Q(23), DOB11=>Q(24), DOB12=>Q(25), DOB13=>Q(31), + DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>open); pdp_ram_0_2_0: DP16KC generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", @@ -666,321 +722,345 @@ begin ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn, - WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>Q(8), DOB1=>open, DOB2=>open, - DOB3=>open, DOB4=>Q(17), DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>Q(26), DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>Q(35), DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_81: FD1P3BX + ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, + OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8), + DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>Q(17), DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>Q(26), DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>Q(35), DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + FF_89: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); - FF_80: FD1P3DX + FF_88: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); - FF_79: FD1P3DX + FF_87: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); - FF_78: FD1P3DX + FF_86: FD1P3DX port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_3); - FF_77: FD1P3DX + FF_85: FD1P3DX port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_4); - FF_76: FD1P3DX + FF_84: FD1P3DX port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_5); - FF_75: FD1P3DX + FF_83: FD1P3DX port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_6); - FF_74: FD1P3DX + FF_82: FD1P3DX port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_7); - FF_73: FD1P3DX + FF_81: FD1P3DX port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_8); - FF_72: FD1P3DX + FF_80: FD1P3DX port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); - FF_71: FD1P3DX + FF_79: FD1P3DX port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); - FF_70: FD1P3DX + FF_78: FD1P3DX port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); - FF_69: FD1P3DX + FF_77: FD1P3DX port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_3); - FF_68: FD1P3DX + FF_76: FD1P3DX port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_4); - FF_67: FD1P3DX + FF_75: FD1P3DX port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_5); - FF_66: FD1P3DX + FF_74: FD1P3DX port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_6); - FF_65: FD1P3DX + FF_73: FD1P3DX port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_7); - FF_64: FD1P3DX + FF_72: FD1P3DX port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_8); - FF_63: FD1P3DX + FF_71: FD1P3DX port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); - FF_62: FD1P3DX + FF_70: FD1P3DX port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); - FF_61: FD1P3DX + FF_69: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); - FF_60: FD1P3DX + FF_68: FD1P3DX port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_3); - FF_59: FD1P3DX + FF_67: FD1P3DX port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_4); - FF_58: FD1P3DX + FF_66: FD1P3DX port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_5); - FF_57: FD1P3DX + FF_65: FD1P3DX port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_6); - FF_56: FD1P3DX + FF_64: FD1P3DX port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_7); - FF_55: FD1P3DX + FF_63: FD1P3DX port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_8); - FF_54: FD1P3BX + FF_62: FD1P3BX port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); - FF_53: FD1P3DX + FF_61: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); - FF_52: FD1P3DX + FF_60: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); - FF_51: FD1P3DX + FF_59: FD1P3DX port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_3); - FF_50: FD1P3DX + FF_58: FD1P3DX port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_4); - FF_49: FD1P3DX + FF_57: FD1P3DX port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_5); - FF_48: FD1P3DX + FF_56: FD1P3DX port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_6); - FF_47: FD1P3DX + FF_55: FD1P3DX port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); - FF_46: FD1P3DX + FF_54: FD1P3DX port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); - FF_45: FD1P3DX + FF_53: FD1P3DX port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); - FF_44: FD1P3DX + FF_52: FD1P3DX port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_3); - FF_43: FD1P3DX + FF_51: FD1P3DX port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_4); - FF_42: FD1P3DX + FF_50: FD1P3DX port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_5); - FF_41: FD1P3DX + FF_49: FD1P3DX port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_6); - FF_40: FD1P3DX + FF_48: FD1P3DX port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); - FF_39: FD1P3DX + FF_47: FD1P3DX port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); - FF_38: FD1P3DX + FF_46: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); - FF_37: FD1P3DX + FF_45: FD1P3DX port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_3); - FF_36: FD1P3DX + FF_44: FD1P3DX port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_4); - FF_35: FD1P3DX + FF_43: FD1P3DX port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_5); - FF_34: FD1P3DX + FF_42: FD1P3DX port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_6); - FF_33: FD1S3DX + FF_41: FD1S3DX port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - FF_32: FD1S3DX + FF_40: FD1S3DX port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - FF_31: FD1S3DX + FF_39: FD1S3DX port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - FF_30: FD1S3DX + FF_38: FD1S3DX port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - FF_29: FD1S3DX + FF_37: FD1S3DX port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - FF_28: FD1S3DX + FF_36: FD1S3DX port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - FF_27: FD1S3DX + FF_35: FD1S3DX port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - FF_26: FD1S3DX + FF_34: FD1S3DX port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - FF_25: FD1S3DX + FF_33: FD1S3DX port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - FF_24: FD1S3DX + FF_32: FD1S3DX port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - FF_23: FD1S3DX + FF_31: FD1S3DX port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - FF_22: FD1S3DX + FF_30: FD1S3DX port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - FF_21: FD1S3DX + FF_29: FD1S3DX port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - FF_20: FD1S3DX + FF_28: FD1S3DX port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - FF_19: FD1S3DX + FF_27: FD1S3DX port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - FF_18: FD1S3DX + FF_26: FD1S3DX port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - FF_17: FD1S3DX + FF_25: FD1S3DX port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); - FF_16: FD1S3DX + FF_24: FD1S3DX port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); - FF_15: FD1S3DX + FF_23: FD1S3DX port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); - FF_14: FD1S3DX + FF_22: FD1S3DX port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r23); - FF_13: FD1S3DX + FF_21: FD1S3DX port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r24); - FF_12: FD1S3DX + FF_20: FD1S3DX port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r25); - FF_11: FD1S3DX + FF_19: FD1S3DX port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r26); - FF_10: FD1S3DX + FF_18: FD1S3DX port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r27); - FF_9: FD1S3DX + FF_17: FD1S3DX port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r28); - FF_8: FD1S3DX + FF_16: FD1S3DX port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - FF_7: FD1S3DX + FF_15: FD1S3DX port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - FF_6: FD1S3DX + FF_14: FD1S3DX port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - FF_5: FD1S3DX + FF_13: FD1S3DX port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - FF_4: FD1S3DX + FF_12: FD1S3DX port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - FF_3: FD1S3DX + FF_11: FD1S3DX port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - FF_2: FD1S3DX + FF_10: FD1S3DX port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - FF_1: FD1S3BX + FF_9: FD1S3DX + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); + + FF_8: FD1S3DX + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); + + FF_7: FD1S3DX + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); + + FF_6: FD1S3DX + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); + + FF_5: FD1S3DX + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); + + FF_4: FD1S3DX + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); + + FF_3: FD1S3DX + port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); + + FF_2: FD1S3BX port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - FF_0: FD1S3DX + FF_1: FD1S3DX port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + FF_0: FD1S3BX + port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); + w_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, @@ -1006,9 +1086,6 @@ begin port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4, NC0=>iwcount_8, NC1=>open); - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - r_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, @@ -1030,25 +1107,52 @@ begin port map (CI=>co2_1, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_1, NC0=>ircount_6, NC1=>open); + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + rcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo, + B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rcount_1, + B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1, + S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r6, B0=>rcount_3, + B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3, + S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_r7, A1=>rcnt_sub_msb, B0=>rcount_5, + B1=>scuba_vlo, BI=>co2_2, BOUT=>co3_2, S0=>rcnt_sub_5, + S1=>rcnt_sub_6); + + rcntd: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_2, COUT=>open, S0=>co3_2d, S1=>open); + empty_cmp_ci_a: FADD2B port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); empty_cmp_0: AGEB2 port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2, - B1=>wcount_r3, CI=>cmp_ci, GE=>co0_2); + B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3); empty_cmp_1: AGEB2 port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4, - B1=>w_g2b_xor_cluster_0, CI=>co0_2, GE=>co1_2); + B1=>w_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3); empty_cmp_2: AGEB2 port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6, - B1=>wcount_r7, CI=>co1_2, GE=>co2_2); + B1=>wcount_r7, CI=>co1_3, GE=>co2_3); empty_cmp_3: AGEB2 port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co2_2, GE=>empty_d_c); + B1=>scuba_vlo, CI=>co2_3, GE=>empty_d_c); a0: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -1061,44 +1165,69 @@ begin full_cmp_0: AGEB2 port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_3); + B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4); full_cmp_1: AGEB2 port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0, - B1=>rcount_w1, CI=>co0_3, GE=>co1_3); + B1=>rcount_w1, CI=>co0_4, GE=>co1_4); full_cmp_2: AGEB2 port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2, - B1=>r_g2b_xor_cluster_0, CI=>co1_3, GE=>co2_3); + B1=>r_g2b_xor_cluster_0, CI=>co1_4, GE=>co2_4); full_cmp_3: AGEB2 port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4, - B1=>rcount_w5, CI=>co2_3, GE=>co3_2); + B1=>rcount_w5, CI=>co2_4, GE=>co3_3); full_cmp_4: AGEB2 port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co3_2, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); + B1=>scuba_vlo, CI=>co3_3, GE=>full_d_c); a1: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, S1=>open); + ae_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + ae_cmp_0: AGEB2 + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_5); + + ae_cmp_1: AGEB2 + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_5, GE=>co1_5); + + ae_cmp_2: AGEB2 + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_5, GE=>co2_5); + + ae_cmp_3: AGEB2 + port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, + B1=>scuba_vlo, CI=>co2_5, GE=>ae_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); + Empty <= empty_i; Full <= full_i; end Structure; -- synopsys translate_off library ecp3; -configuration Structure_CON of fifo_dc_9to36 is +configuration Structure_CON of fifo_dc_9to36_dyn is for Structure for all:AGEB2 use entity ecp3.AGEB2(V); end for; for all:AND2 use entity ecp3.AND2(V); end for; for all:CU2 use entity ecp3.CU2(V); end for; for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd index 2fd8581..7518c95 100644 --- a/nxyter/source/nx_timestamp_fifo_read.vhd +++ b/nxyter/source/nx_timestamp_fifo_read.vhd @@ -41,7 +41,8 @@ architecture Behavioral of nx_timestamp_fifo_read is signal fifo_full : std_logic; signal fifo_write_enable : std_logic; signal frame_tag_o : std_logic; - + signal fifo_reset : std_logic; + -- FRAME_CLOCK_GENERATOR signal frame_clock_ctr : unsigned(1 downto 0); signal nx_frame_clock_o : std_logic; @@ -49,7 +50,7 @@ architecture Behavioral of nx_timestamp_fifo_read is signal frame_clock_ctr_inc_x : std_logic; signal frame_clock_ctr_inc_l : std_logic; signal frame_clock_ctr_inc : std_logic; - + ----------------------------------------------------------------------------- -- CLK_IN Domain ----------------------------------------------------------------------------- @@ -57,14 +58,14 @@ architecture Behavioral of nx_timestamp_fifo_read is -- FIFO Output Handler signal fifo_out : std_logic_vector(35 downto 0); signal fifo_empty : std_logic; - signal fifo_empty_prev : std_logic; + signal fifo_almost_empty : std_logic; + signal fifo_almost_empty_prev : std_logic; signal fifo_read_enable : std_logic; signal fifo_data_valid_x : std_logic; signal fifo_data_valid : std_logic; - signal register_fifo_data : std_logic_vector(31 downto 0); signal fifo_new_frame : std_logic; - + signal frame_clock_ctr_inc_o : std_logic; -- RS Sync FlipFlop @@ -99,7 +100,9 @@ architecture Behavioral of nx_timestamp_fifo_read is signal reset_ctr : std_logic; signal frame_clock_ctr_inc_r : std_logic; - + signal fifo_delay_r : std_logic_vector(5 downto 0); + signal fifo_reset_r : std_logic; + begin DEBUG_OUT(0) <= CLK_IN; @@ -109,9 +112,8 @@ begin DEBUG_OUT(4) <= fifo_data_valid; DEBUG_OUT(5) <= fifo_new_frame; DEBUG_OUT(6) <= NX_NEW_TIMESTAMP_OUT; - DEBUG_OUT(7) <= frame_tag_o; - -- DEBUG_OUT(15 downto 8) <= NX_TIMESTAMP_IN; - DEBUG_OUT(15 downto 8) <= fifo_out(7 downto 0); + DEBUG_OUT(7) <= fifo_almost_empty; + DEBUG_OUT(15 downto 8) <= (others => '0'); -- DEBUG_OUT(0) <= CLK_IN; -- @@ -129,23 +131,26 @@ begin -- Dual Clock FIFO 9bit to 36bit ----------------------------------------------------------------------------- - -- Send data to FIFO - fifo_dc_9to36_1: fifo_dc_9to36 + -- Send data to FIFO, depth is 256 + fifo_dc_9to36_dyn_1: fifo_dc_9to36_dyn port map ( - Data(7 downto 0) => NX_TIMESTAMP_IN, - Data(8) => frame_tag_o, - WrClock => NX_TIMESTAMP_CLK_IN, - RdClock => CLK_IN, - WrEn => fifo_write_enable, - RdEn => fifo_read_enable, - Reset => RESET_IN, - RPReset => RESET_IN, - Q => fifo_out, - Empty => fifo_empty, - Full => fifo_full + Data(7 downto 0) => NX_TIMESTAMP_IN, + Data(8) => frame_tag_o, + WrClock => NX_TIMESTAMP_CLK_IN, + RdClock => CLK_IN, + WrEn => fifo_write_enable, + RdEn => fifo_read_enable, + Reset => fifo_reset, + RPReset => fifo_reset, + AmEmptyThresh => fifo_delay_r, + Q => fifo_out, + Empty => fifo_empty, + Full => fifo_full, + AlmostEmpty => fifo_almost_empty ); fifo_write_enable <= not RESET_IN; + fifo_reset <= RESET_IN or fifo_reset_r; ----------------------------------------------------------------------------- -- FIFO Input Handler @@ -220,24 +225,24 @@ begin begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - fifo_empty_prev <= '0'; - fifo_read_enable <= '0'; - fifo_data_valid_x <= '0'; - fifo_data_valid <= '0'; + fifo_almost_empty_prev <= '0'; + fifo_read_enable <= '0'; + fifo_data_valid_x <= '0'; + fifo_data_valid <= '0'; else - if (fifo_empty = '0' and fifo_empty_prev = '1') then - fifo_read_enable <= '1'; + if (fifo_almost_empty = '0' and fifo_almost_empty_prev = '1') then + fifo_read_enable <= '1'; else - fifo_read_enable <= '0'; + fifo_read_enable <= '0'; + end if; - fifo_empty_prev <= fifo_empty; - fifo_data_valid_x <= fifo_read_enable; - fifo_data_valid <= fifo_data_valid_x; + fifo_almost_empty_prev <= fifo_almost_empty; + fifo_data_valid_x <= fifo_read_enable; + fifo_data_valid <= fifo_data_valid_x; end if; end if; end process PROC_FIFO_READ_ENABLE; - -- Read only in case FIFO is not empty, i.e. data_valid is set PROC_FIFO_READ: process(CLK_IN) @@ -435,6 +440,8 @@ begin slv_no_more_data_o <= '0'; frame_clock_ctr_inc_r <= '0'; reset_ctr <= '0'; + fifo_delay_r <= "000010"; + fifo_reset_r <= '0'; else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -442,6 +449,7 @@ begin slv_no_more_data_o <= '0'; frame_clock_ctr_inc_r <= '0'; reset_ctr <= '0'; + fifo_reset_r <= '0'; if (SLV_READ_IN = '1') then case SLV_ADDR_IN is @@ -464,6 +472,11 @@ begin slv_data_out_o(31 downto 8) <= (others => '0'); slv_ack_o <= '1'; + when x"0003" => + slv_data_out_o(5 downto 0) <= fifo_delay_r; + slv_data_out_o(31 downto 6) <= (others => '0'); + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; end case; @@ -477,7 +490,15 @@ begin when x"0002" => reset_ctr <= '1'; slv_ack_o <= '1'; - + + when x"0003" => + if (SLV_DATA_IN < x"0000003c" and + SLV_DATA_IN > x"00000001") then + fifo_delay_r <= SLV_DATA_IN(5 downto 0); + fifo_reset_r <= '1'; + end if; + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; end case; diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd index 2af5df3..d45da91 100644 --- a/nxyter/source/nxyter.vhd +++ b/nxyter/source/nxyter.vhd @@ -10,6 +10,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; +use work.trb3_components.all; use work.nxyter_components.all; -- ADCM use work.adcmv3_components.all; @@ -57,7 +58,7 @@ entity nXyter_FEE_board is REGIO_WRITE_ACK_OUT : out std_logic; REGIO_NO_MORE_DATA_OUT : out std_logic; REGIO_UNKNOWN_ADDR_OUT : out std_logic; - + -- Debug Signals CLK_128_IN : in std_logic; DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) @@ -131,7 +132,16 @@ architecture Behavioral of nXyter_FEE_board is -- Trigger Generator signal trigger : std_logic; signal nx_testpulse_o : std_logic; - + + + -- ADC FIFO + signal adc_ref_clk : std_logic; + signal adc_dat_clk : std_logic; + signal adc_data_word : std_logic_vector(11 downto 0); + signal adc_data_valid : std_logic; + signal adc_fco : std_logic; + signal adc_restart : std_logic; + begin ------------------------------------------------------------------------------- @@ -153,15 +163,30 @@ begin -- -- DEBUG_LINE_OUT(14 downto 13) <= timestamp_status; -- DEBUG_LINE_OUT(15) <= slv_ack(3); - + DEBUG_LINE_OUT(0) <= CLK_IN; DEBUG_LINE_OUT(1) <= trigger; DEBUG_LINE_OUT(2) <= trigger_ack; DEBUG_LINE_OUT(3) <= trigger_busy; - DEBUG_LINE_OUT(4) <= nx_new_timestamp; - DEBUG_LINE_OUT(5) <= timestamp_valid; - DEBUG_LINE_OUT(6) <= nx_token_return; - DEBUG_LINE_OUT(7) <= nx_nomore_data; + --DEBUG_LINE_OUT(4) <= nx_new_timestamp; + --DEBUG_LINE_OUT(5) <= timestamp_valid; + --DEBUG_LINE_OUT(6) <= nx_token_return; + --DEBUG_LINE_OUT(7) <= nx_nomore_data; + + DEBUG_LINE_OUT(4) <= '0'; + DEBUG_LINE_OUT(5) <= '0'; + DEBUG_LINE_OUT(6) <= adc_fco; + DEBUG_LINE_OUT(7) <= adc_data_valid; + + + DEBUG_LINE_OUT(8) <= ADC_FCLK_IN; + DEBUG_LINE_OUT(9) <= ADC_DCLK_IN; + DEBUG_LINE_OUT(10) <= ADC_SC_CLK32_OUT; + DEBUG_LINE_OUT(11) <= ADC_A_IN; + DEBUG_LINE_OUT(12) <= ADC_B_IN; + DEBUG_LINE_OUT(13) <= ADC_NX_IN; + DEBUG_LINE_OUT(14) <= ADC_D_IN; + DEBUG_LINE_OUT(15) <= '0'; --DEBUG_LINE_OUT(15 downto 8) <= (others => '0'); @@ -180,6 +205,15 @@ begin NX_CLK256A_OUT <= clk_256_o; + clock10MHz_1: clock10MHz + port map ( + CLK => CLK_IN, + CLKOP => adc_ref_clk, + LOCK => open + ); + + + THE_BUS_HANDLER: trb_net16_regio_bus_handler generic map( PORT_NUMBER => 9, @@ -573,8 +607,9 @@ begin SLV_ACK_OUT => slv_ack(8), SLV_NO_MORE_DATA_OUT => slv_no_more_data(8), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8), - DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8), - DEBUG_OUT(15 downto 8) => open + -- DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8), + -- DEBUG_OUT(15 downto 8) => open + DEBUG_OUT(15 downto 0) => open ); ------------------------------------------------------------------------------- @@ -602,6 +637,38 @@ begin ); data_buffer_reset <= RESET_IN or data_fifo_reset; + +------------------------------------------------------------------------------- +-- ADC 9228 Handler +------------------------------------------------------------------------------- + adc_ad9222_1: adc_ad9222 + generic map ( + CHANNELS => 4, + DEVICES => 2, + RESOLUTION => 12 + ) + port map ( + CLK => CLK_IN, + CLK_ADCREF => adc_ref_clk, + CLK_ADCDAT => adc_dat_clk, + RESTART_IN => adc_restart, + ADCCLK_OUT => ADC_SC_CLK32_OUT, + ADC_DATA(0) => ADC_NX_IN, + ADC_DATA(7 downto 1) => open, + ADC_DCO(0) => ADC_DCLK_IN, + ADC_DCO(1) => ADC_DCLK_IN, + ADC_FCO(0) => ADC_FCLK_IN, + ADC_FCO(1) => open, + DATA_OUT(11 downto 0) => adc_data_word, + DATA_OUT(95 downto 12) => open, + FCO_OUT => open, +-- FCO_OUT(23 downto 1) => open, + DATA_VALID_OUT(0) => adc_data_valid, + DATA_VALID_OUT(1) => open, + DEBUG => open + ); + + adc_restart <= '0'; ------------------------------------------------------------------------------- -- nXyter Signals @@ -610,6 +677,11 @@ begin NX_RESET_OUT <= not nx_ts_reset_o; NX_TESTPULSE_OUT <= nx_testpulse_o; +------------------------------------------------------------------------------- +-- ADC Signals +------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------- -- I2C Signals ------------------------------------------------------------------------------- @@ -618,7 +690,7 @@ begin I2C_REG_RESET_OUT <= not i2c_reg_reset_o; - ADC_SC_CLK32_OUT <= nx_frame_clock_o; +-- ADC_SC_CLK32_OUT <= nx_frame_clock_o; ------------------------------------------------------------------------------- -- END diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 727f199..8a6c82c 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -52,6 +52,44 @@ component nXyter_FEE_board ); end component; +------------------------------------------------------------------------------- +-- TrbNet Data Interface +------------------------------------------------------------------------------- + +component nXyter_data_handler + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); + REGIO_DATA_IN : in std_logic_vector(31 downto 0); + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); + REGIO_READ_ENABLE_IN : in std_logic; + REGIO_WRITE_ENABLE_IN : in std_logic; + REGIO_TIMEOUT_IN : in std_logic; + REGIO_DATAREADY_OUT : out std_logic; + REGIO_WRITE_ACK_OUT : out std_logic; + REGIO_NO_MORE_DATA_OUT : out std_logic; + REGIO_UNKNOWN_ADDR_OUT : out std_logic; + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; + LVL1_INVALID_TRG_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + FEE_TRG_RELEASE_OUT : out std_logic; + FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + FEE_DATA_ALMOST_FULL_IN : in std_logic; + DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) + ); +end component; + + ------------------------------------------------------------------------------- -- nXyter I2C Interface ------------------------------------------------------------------------------- @@ -204,18 +242,28 @@ component nxyter_registers ); end component; -component fifo_dc_9to36 +component clock10MHz + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic + ); +end component; + +component fifo_dc_9to36_dyn port ( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic + Data : in std_logic_vector(8 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + AmEmptyThresh: in std_logic_vector(5 downto 0); + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic ); end component; diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index 6142ff3..bbae5cb 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -40,6 +40,7 @@ w: trigger resync 0x8502 : r/w r: get resync counter(8bit) w: clear resync counter +0x8503 : r/w FIFO Delay, i.e. Trigger Delay (6bit, in 3.1ns, range 2 .. 60) -- Data Buffer 0x8600 : r read FIFO buffer diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index c1bf9e4..3561bf0 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -146,10 +146,11 @@ add_file -vhdl -lib "work" "./source/adcmv3_components.vhd" add_file -vhdl -lib "work" "./source/nxyter_components.vhd" add_file -vhdl -lib "work" "./source/nxyter.vhd" +add_file -vhdl -lib "work" "./source/nxyter_data_handler.vhd" add_file -vhdl -lib "work" "./source/pll_nx_clk256.vhd" add_file -vhdl -lib "work" "./source/nxyter_registers.vhd" +add_file -vhdl -lib "work" "./source/fifo_dc_9to36_dyn.vhd" add_file -vhdl -lib "work" "./source/nx_timestamp_fifo_read.vhd" -add_file -vhdl -lib "work" "./source/fifo_dc_9to36.vhd" add_file -vhdl -lib "work" "./source/level_to_pulse.vhd" add_file -vhdl -lib "work" "./source/gray_decoder.vhd" add_file -vhdl -lib "work" "./source/gray_encoder.vhd" @@ -157,6 +158,9 @@ add_file -vhdl -lib "work" "./source/nx_data_buffer.vhd" add_file -vhdl -lib "work" "./source/fifo_32_data.vhd" add_file -vhdl -lib "work" "./source/nx_timer.vhd" +add_file -vhdl -lib "work" "./source/nx_timestamp_decode.vhd" +add_file -vhdl -lib "work" "./source/nx_timestamp_process.vhd" + add_file -vhdl -lib "work" "./source/nx_i2c_master.vhd" add_file -vhdl -lib "work" "./source/nx_i2c_startstop.vhd" add_file -vhdl -lib "work" "./source/nx_i2c_sendbyte.vhd" @@ -166,4 +170,17 @@ add_file -vhdl -lib "work" "./source/adc_spi_master.vhd" add_file -vhdl -lib "work" "./source/adc_spi_sendbyte.vhd" add_file -vhdl -lib "work" "./source/adc_spi_readbyte.vhd" +add_file -vhdl -lib "work" "./source/nx_fpga_timestamp.vhd" +add_file -vhdl -lib "work" "./source/nx_trigger_generator.vhd" +add_file -vhdl -lib "work" "./source/nx_trigger_handler.vhd" add_file -vhdl -lib "work" "./source/nx_timestamp_sim.vhd" + +add_file -vhdl -lib "work" "./source/clock10MHz.vhd" + +# Needed by ADC9222 Entity +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd" +add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200.vhd" +add_file -vhdl -lib "work" "../base/cores/pll_adc12bit.vhd" +add_file -vhdl -lib "work" "../base/cores/fifo_32x512.vhd" +add_file -vhdl -lib "work" "../base/code/adc_ad9222.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index d6a6f83..919e241 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -369,7 +369,8 @@ begin REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg ADDRESS_MASK => x"FFFF", BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => x"45", + --BROADCAST_SPECIAL_ADDR => x"45", + BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), REGIO_HARDWARE_VERSION => x"91000003", REGIO_INIT_ADDRESS => x"f305", @@ -635,11 +636,49 @@ begin LED_YELLOW <= not med_stat_op(11); +------------------------------------------------------------------------------- +-- nXyter Data Handler +------------------------------------------------------------------------------- + nXyter_data_handler_1: nXyter_data_handler + port map ( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + + REGIO_ADDR_IN => open, --REGIO_ADDR_IN, + REGIO_DATA_IN => open, --REGIO_DATA_IN, + REGIO_DATA_OUT => open, --REGIO_DATA_OUT, + REGIO_READ_ENABLE_IN => open, --REGIO_READ_ENABLE_IN, + REGIO_WRITE_ENABLE_IN => open, --REGIO_WRITE_ENABLE_IN, + REGIO_TIMEOUT_IN => open, --REGIO_TIMEOUT_IN, + REGIO_DATAREADY_OUT => open, --REGIO_DATAREADY_OUT, + REGIO_WRITE_ACK_OUT => open, --REGIO_WRITE_ACK_OUT, + REGIO_NO_MORE_DATA_OUT => open, --REGIO_NO_MORE_DATA_OUT, + REGIO_UNKNOWN_ADDR_OUT => open, --REGIO_UNKNOWN_ADDR_OUT, + + LVL1_TRG_DATA_VALID_IN => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, + LVL1_INVALID_TRG_IN => trg_invalid_i, + LVL1_TRG_TYPE_IN => trg_type_i, + LVL1_TRG_NUMBER_IN => trg_number_i, + LVL1_TRG_CODE_IN => trg_code_i, + LVL1_TRG_INFORMATION_IN => trg_information_i, + LVL1_INT_TRG_NUMBER_IN => trg_int_number_i, + + FEE_TRG_RELEASE_OUT => fee_trg_release_i, + FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i, + FEE_DATA_OUT => fee_data_i, + FEE_DATA_WRITE_OUT => fee_data_write_i, + FEE_DATA_FINISHED_OUT => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i, + + -- DEBUG_LINE_OUT => TEST_LINE + DEBUG_LINE_OUT => open + ); - - ----------------------------------------------------------------------------- - -- The xXyter-FEB - ----------------------------------------------------------------------------- +----------------------------------------------------------------------------- +-- The xXyter-FEB +----------------------------------------------------------------------------- nXyter_FEE_board_1: nXyter_FEE_board port map ( @@ -657,8 +696,8 @@ begin NX_CLK128_IN => NX1_CLK128_IN, NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN, --- NX_CLK128_IN => nx1_clk128_sim_o, --- NX_TIMESTAMP_IN => nx1_timestamp_sim_o, + -- NX_CLK128_IN => nx1_clk128_sim_o, + -- NX_TIMESTAMP_IN => nx1_timestamp_sim_o, NX_RESET_OUT => NX1_RESET_OUT, NX_CLK256A_OUT => NX1_CLK256A_OUT, @@ -688,26 +727,16 @@ begin -- DEBUG_LINE_OUT => open ); - -- TEST_LINE(0) <= clk_100_i; - -- TEST_LINE(1) <= clk_200_i; - -- TEST_LINE(2) <= NX1_CLK128_IN; - -- TEST_LINE(3) <= NX2_CLK128_IN; - -- TEST_LINE(7 downto 4) <= (others => '0'); - -- TEST_LINE(11 downto 8) <= NX1_TIMESTAMP_IN(3 downto 0); - -- TEST_LINE(15 downto 12) <= NX2_TIMESTAMP_IN(3 downto 0); - - - ------------------------------------------------------------------------------- -- Timestamp Simulator ------------------------------------------------------------------------------- --- nxyter_timestamp_sim_1: nxyter_timestamp_sim --- port map ( --- CLK_IN => CLK_GPLL_LEFT, --- RESET_IN => reset_i, --- TIMESTAMP_OUT => nx1_timestamp_sim_o, --- CLK128_OUT => nx1_clk128_sim_o --- ); + nxyter_timestamp_sim_1: nxyter_timestamp_sim + port map ( + CLK_IN => CLK_GPLL_LEFT, + RESET_IN => reset_i, + TIMESTAMP_OUT => nx1_timestamp_sim_o, + CLK128_OUT => nx1_clk128_sim_o + ); --------------------------------------------------------------------------- -- 2.43.0