From ec68357a0cc4d64fb55b7ddf5f5a75571d27fb1c Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 19 Oct 2007 13:20:55 +0000 Subject: [PATCH] bram fifo tested, Jan --- trb_net16_apimbuf.vhd | 2 +- trb_net16_base_api.vhd | 18 ++++- trb_net16_ibuf.vhd | 6 +- xilinx/trb_net16_bram_fifo.vhd | 122 ++++++++++++--------------------- xilinx/trb_net_fifo_arch.vhd | 4 +- 5 files changed, 65 insertions(+), 87 deletions(-) diff --git a/trb_net16_apimbuf.vhd b/trb_net16_apimbuf.vhd index f494dab..e2ce1c7 100644 --- a/trb_net16_apimbuf.vhd +++ b/trb_net16_apimbuf.vhd @@ -487,7 +487,7 @@ begin APL_DTYPE_IN => APL_DTYPE_IN, APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => (others => '0'), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, -- Receiver port APL_DATA_OUT => APL_DATA_OUT, APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, diff --git a/trb_net16_base_api.vhd b/trb_net16_base_api.vhd index 71e697c..5c65226 100644 --- a/trb_net16_base_api.vhd +++ b/trb_net16_base_api.vhd @@ -704,9 +704,25 @@ begin -- --------------------------------------- + --get target address from active APL + gentarget1: if API_TYPE = 1 generate + combined_header_F2 <= APL_TARGET_ADDRESS_IN; + end generate; + --save target address for passive api + gentarget0: if API_TYPE = 0 generate + reg_hdr_f1: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + combined_header_F2 <= (others => '1'); + elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_packet_num_out = "01" then + combined_header_F2 <= fifo_to_apl_data_out; + end if; + end if; + end process; + end generate; -- combine the next header combined_header_F1 <= APL_MY_ADDRESS_IN; - combined_header_F2 <= APL_TARGET_ADDRESS_IN; combined_header_F3(15 downto 14) <= (others => '0'); -- LAY combined_header_F3(13 downto 12) <= (others => '0'); -- VERS combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 98dee34..6a55e25 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -299,7 +299,7 @@ begin reg_hdr_f1: process(CLK) begin if rising_edge(CLK) then - if RESET = '0' then + if RESET = '1' then current_last_header_F1 <= (others => '0'); elsif reading_header = '1' and fifo_packet_num_out = "01" then current_last_header_F1 <= fifo_data_out; @@ -309,7 +309,7 @@ begin reg_hdr_f2: process(CLK) begin if rising_edge(CLK) then - if RESET = '0' then + if RESET = '1' then current_last_header_F2 <= (others => '0'); elsif reading_header = '1' and fifo_packet_num_out = "10" then current_last_header_F2 <= fifo_data_out; @@ -319,7 +319,7 @@ begin reg_hdr_f3: process(CLK) begin if rising_edge(CLK) then - if RESET = '0' then + if RESET = '1' then current_last_header_F3 <= (others => '0'); elsif reading_header = '1' and fifo_packet_num_out = "11" then current_last_header_F3 <= fifo_data_out; diff --git a/xilinx/trb_net16_bram_fifo.vhd b/xilinx/trb_net16_bram_fifo.vhd index 8cce89d..4879bde 100644 --- a/xilinx/trb_net16_bram_fifo.vhd +++ b/xilinx/trb_net16_bram_fifo.vhd @@ -70,9 +70,8 @@ architecture trb_net16_bram_fifo_arch of trb_net16_bram_fifo is signal gnd_bus: std_logic_vector(17 downto 0); signal gnd: std_logic; signal pwr: std_logic; - signal last_write_data: std_logic_vector(17 downto 0); - signal not_read_since_emtpy: std_logic; - signal last_first_write_allow: std_logic; + signal read_after_write: std_logic; + signal read_after_empty: std_logic; component BUFG port ( @@ -103,66 +102,19 @@ component RAMB16_S18_S18 end component; begin - read_enable <= read_enable_in or last_first_write_allow; - write_enable <= write_enable_in; - fifo_gsr <= fifo_gsr_in; - write_data <= write_data_in; - read_data_out <= - read_data; --- write_data_in when empty = '1' else --- last_write_data when not_read_since_emtpy = '1' else + read_enable <= read_enable_in; + write_enable <= write_enable_in; + fifo_gsr <= fifo_gsr_in; + write_data <= write_data_in; + read_data_out <= read_data; + full_out <= full; - empty_out <= empty and not fcounter(0); gnd_bus <= "000000000000000000"; gnd <= '0'; pwr <= '1'; + empty_out <= (empty or read_after_write) and read_after_empty; + clock <= clock_in; --- process(clock_in) --- begin --- if rising_edge(clock_in) then --- if fifo_gsr = '1' then --- empty_out <= '0'; --- else --- empty_out <= emptyg; --- end if; --- end if; --- end process; - - process(clock_in) - begin - if rising_edge(clock_in) then - if fifo_gsr = '1' then - last_write_data <= (others => '0'); - elsif write_enable = '1' and empty = '1' then - last_write_data <= write_data_in; - end if; - end if; - end process; - - process(clock_in) - begin - if rising_edge(clock_in) then - if fifo_gsr = '1' then - not_read_since_emtpy <= '1'; - else - if empty = '1' then - not_read_since_emtpy <= '1'; - end if; - if read_enable = '1' then - not_read_since_emtpy <= '0'; - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- -- --- A global buffer is instantianted to avoid skew problems. -- --- -- --------------------------------------------------------------------------- - ---gclk1: BUFG port map (I => clock_in, O => clock); -clock <= clock_in; -------------------------------------------------------------------------- -- -- -- Block RAM instantiation for FifO. Module is 1024x18, of which one -- @@ -189,10 +141,8 @@ bram1: RAMB16_S18_S18 port map (ADDRA => read_addr, ADDRB => write_addr, -- begin -- if (fifo_gsr = '1') then -- read_allow <= '0'; --- read_active <= '0'; -- elsif (clock'EVENT AND clock = '1') then -- read_allow <= read_enable AND NOT emptyg; --- read_active <= read_enable and not (emptyg or (empty and write_enable)); -- end if; -- end process proc1; -- @@ -206,20 +156,34 @@ bram1: RAMB16_S18_S18 port map (ADDRA => read_addr, ADDRB => write_addr, -- end process proc2; write_allow <= write_enable AND NOT fullg; -read_allow <= (read_enable AND (NOT empty or fcounter(0))); +read_allow <= (read_enable or read_after_write) AND NOT empty;-- ; +fcnt_allow <= write_allow XOR read_allow; -- and not read_after_write -fcnt_allow <= (write_allow XOR read_allow) or (write_enable and empty) ; +proc33: process (clock) +begin + if rising_edge(clock) then + if (fifo_gsr = '1') then + read_after_write <= '0'; + else + if empty = '1' and write_enable = '1' then + read_after_write <= '1'; + else + read_after_write <= '0'; + end if; + end if; + end if; +end process; - process(clock_in) - begin - if rising_edge(clock_in) then - if fifo_gsr = '1' then - last_first_write_allow <= '0'; - else - last_first_write_allow <= write_enable and empty; - end if; +process(clock) + begin + if rising_edge(clock) then + if fifo_gsr = '1' or (empty = '0' and emptyg = '1') then + read_after_empty <= '0'; + elsif read_enable_in = '1' then + read_after_empty <= '1'; end if; - end process; + end if; + end process; --------------------------------------------------------------- -- -- @@ -232,7 +196,7 @@ fcnt_allow <= (write_allow XOR read_allow) or (write_enable and empty) ; ra_or_fcnt0 <= (read_allow OR NOT fcounter(0)); -emptyg <= (not or_all(fcounter(9 downto 0)) AND ra_or_fcnt0); -- AND NOT write_allow +emptyg <= (not or_all(fcounter(9 downto 1)) AND ra_or_fcnt0) AND NOT write_allow; -- proc3: process (clock, fifo_gsr) begin @@ -249,15 +213,13 @@ end process proc3; -- first valid clock edge after fifo_gsr is removed), or -- -- when on the next clock cycle, Read Enable is low, and -- -- either the FifOcount is equal to 3FF (hex), or it is -- --- equal to 1FE and the Write Enable is high (about to go -- +-- equal to 3FE and the Write Enable is high (about to go -- -- Full). -- -- -- --------------------------------------------------------------- wa_or_fcnt0 <= (write_allow OR fcounter(0)); ---fcntandout(2) <= (fcounter(4) AND fcounter(3) AND fcounter(2) AND fcounter(1)); ---fcntandout(3) <= (fcounter(8) AND fcounter(7) AND fcounter(6) AND fcounter(5)); -fullg <= (and_all(fcounter(9 downto 1)) AND NOT read_allow); -- AND wa_or_fcnt0 +fullg <= (and_all(fcounter(9 downto 1)) AND wa_or_fcnt0 AND NOT read_allow); proc4: process (clock, fifo_gsr) begin @@ -282,7 +244,7 @@ begin if (fifo_gsr = '1') then read_addr <= "0000000000"; elsif (clock'EVENT AND clock = '1') then - if (read_allow = '1') then -- or(write_enable='1' and empty='1') + if (read_allow = '1') then read_addr <= read_addr + '1'; end if; end if; @@ -315,10 +277,10 @@ begin fcounter <= "0000000000"; elsif (clock'EVENT AND clock = '1') then if (fcnt_allow = '1') then - if (read_allow = '0') then - fcounter <= fcounter + '1'; - elsE + if (read_allow = '1') then -- and read_after_write = '0' fcounter <= fcounter - '1'; + elsE + fcounter <= fcounter + '1'; end if; end if; end if; diff --git a/xilinx/trb_net_fifo_arch.vhd b/xilinx/trb_net_fifo_arch.vhd index 47a9b6b..289c234 100644 --- a/xilinx/trb_net_fifo_arch.vhd +++ b/xilinx/trb_net_fifo_arch.vhd @@ -50,7 +50,7 @@ architecture arch_trb_net_fifo of trb_net_fifo is begin - gen_shiftreg : if DEPTH /= 6 or WIDTH /= 18 or FORCE_LUT = 1 generate + gen_shiftreg : if DEPTH /= 8 or WIDTH /= 18 or FORCE_LUT = 1 generate FULL_OUT <= current_FULL; EMPTY_OUT <= current_EMPTY; @@ -176,7 +176,7 @@ begin - gen_BRAM : if (DEPTH = 6 and WIDTH = 18) and FORCE_LUT = 0 generate + gen_BRAM : if (DEPTH = 8 and WIDTH = 18) and FORCE_LUT = 0 generate bram_fifo:trb_net16_bram_fifo port map ( clock_in => CLK, -- 2.43.0