From ec774e5ba38ccb966b0a572664aefe4c561c60fa Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 18 May 2015 14:32:35 +0200 Subject: [PATCH] brought the project up-to-date with tdc_v2.1.3 --- wasa/compile_constraints.pl | 6 +-- wasa/compile_periph_gsi.pl | 35 +++++++----- wasa/currentRelease | 1 - wasa/tdc_release | 2 +- wasa/trb3_periph_padiwa.prj | 105 ++++++++++++++++++------------------ wasa/trb3_periph_padiwa.vhd | 2 +- 6 files changed, 80 insertions(+), 71 deletions(-) delete mode 120000 wasa/currentRelease diff --git a/wasa/compile_constraints.pl b/wasa/compile_constraints.pl index 48c67d7..769081c 100755 --- a/wasa/compile_constraints.pl +++ b/wasa/compile_constraints.pl @@ -7,9 +7,9 @@ my $TOPNAME = "trb3_periph_padiwa"; #Name of top-level entity #create full lpf file system("cp ../base/$TOPNAME.lpf diamond/trb3_periph.lpf"); -system("cat currentRelease/trbnet_constraints.lpf >> diamond/trb3_periph.lpf"); -system("cat currentRelease/tdc_constraints_64.lpf >> diamond/trb3_periph.lpf"); -system("cat currentRelease/unimportant_lines_constraints.lpf >> diamond/trb3_periph.lpf"); +system("cat tdc_release/trbnet_constraints.lpf >> diamond/trb3_periph.lpf"); +system("cat tdc_release/tdc_constraints_64.lpf >> diamond/trb3_periph.lpf"); +system("cat tdc_release/unimportant_lines_constraints.lpf >> diamond/trb3_periph.lpf"); system("cat unimportant_lines_constraints.lpf >> diamond/trb3_periph.lpf"); diff --git a/wasa/compile_periph_gsi.pl b/wasa/compile_periph_gsi.pl index 0ebaa09..bde934e 100755 --- a/wasa/compile_periph_gsi.pl +++ b/wasa/compile_periph_gsi.pl @@ -8,11 +8,12 @@ use Getopt::Long; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_padiwa"; #Name of top-level entity -my $lattice_path = '/opt/lattice/diamond/3.0_x64/'; +my $lattice_path = '/opt/lattice/diamond/3.4_x64/'; my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed -my $synplify_path = '/opt/synplicity/I-2013.09-SP1'; +my $synplify_path = '/opt/synplicity/J-2014.09-SP2'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +my $synplify_locale_workaround = "en_US\@UTF-8"; ################################################################################### ################################################################################### @@ -41,7 +42,7 @@ my $result = GetOptions ( if($help) { print "Usage: compile_priph_gsi.de \n\n"; print "-h --help\tPrints the usage manual.\n"; - print "-a --all\tRun all compile script. By default the script is going to rung the whole process.\n"; + print "-a --all\tRun all compile script. By default the script is going to run the whole process.\n"; print "-s --syn\tRun synthesis part of the compile script.\n"; print "-mp --map\tRun map part of the compile script.\n"; print "-p --par\tRun par part of the compile script.\n"; @@ -75,8 +76,10 @@ while (<$SOURCE>) { close $SOURCE; + $ENV{'PAR_DESIGN_NAME'}=$TOPNAME; $ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'LC_ALL'}="en_US\@UTF-8"; $ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; @@ -94,12 +97,14 @@ unless(-d $WORKDIR) { system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); #create full lpf file -system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); -system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); -system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); -system("cat currentRelease/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); -system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +#system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); +#system("cat tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +#system("cat tdc_release/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); +#system("cat tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +#system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +#copy delay line to project folder +system("cp tdc_release/Adder_304.ngo $WORKDIR/"); #generate timestamp my $t=time; @@ -142,7 +147,7 @@ if($syn==1 || $all==1){ foreach (@a) { - if(/\@E:/) + if(/\@E|/) { print "\n"; $c="cat $TOPNAME.srr | grep \"\@E\""; @@ -153,6 +158,8 @@ if($syn==1 || $all==1){ } } + + $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; if($map==1 || $all==1){ @@ -176,7 +183,7 @@ if($map==1 || $all==1){ $fh -> close; foreach (@a) { - if(/FC_|HitInvert|ff_en_/) + if(/FC_|hitBuf_|ff_en_/) { print "\n\n"; print "#################################################\n"; @@ -198,8 +205,11 @@ if($par==1 || $all==1){ { #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -t 1 -e 100 -exp parDisablePgroup=0:parUseNBR=1:parCDP=1:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parDisablePgroup=0:parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; - $c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + + $c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -w -i 15 -l 5 -y -s 8 -t 1 -c 1 -e 2 -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=1:parHoldLimit=10000:paruseNBR=1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; execute($c); + # find and copy the .ncd file which has met the timing constraints $fh = new FileHandle("<$TOPNAME".".par"); my @a = <$fh>; @@ -233,7 +243,8 @@ if($par==1 || $all==1){ else { #$c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; - $c=qq|par -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + #$c=qq|par -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + $c=qq|par -p "../$TOPNAME.p2t" -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; execute($c); my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; system($c); diff --git a/wasa/currentRelease b/wasa/currentRelease deleted file mode 120000 index b10de14..0000000 --- a/wasa/currentRelease +++ /dev/null @@ -1 +0,0 @@ -../../tdc/releases/tdc_v2.1.2 \ No newline at end of file diff --git a/wasa/tdc_release b/wasa/tdc_release index b10de14..776b998 120000 --- a/wasa/tdc_release +++ b/wasa/tdc_release @@ -1 +1 @@ -../../tdc/releases/tdc_v2.1.2 \ No newline at end of file +../../tdc/releases/tdc_v2.1.3 \ No newline at end of file diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj index fa6e310..0f0d657 100644 --- a/wasa/trb3_periph_padiwa.prj +++ b/wasa/trb3_periph_padiwa.prj @@ -52,25 +52,17 @@ impl -active "workdir" #add_file options add_file -vhdl -lib work "version.vhd" -add_file -vhdl -lib work "currentRelease/tdc_version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "../base/trb3_components.vhd" -add_file -vhdl -lib work "../base/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" @@ -93,18 +85,31 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" -add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" @@ -127,54 +132,48 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" - add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" - add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" -add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" - - - - -############### -#Change path to tdc release also in compile script! -############### - -#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd" -add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd" -add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd" -add_file -vhdl -lib "work" "currentRelease/Channel.vhd" -add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd" -add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd" -add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd" -add_file -vhdl -lib "work" "currentRelease/Readout.vhd" -#add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd" -add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd" -add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd" -add_file -vhdl -lib "work" "currentRelease/TDC.vhd" -add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd" -add_file -vhdl -lib "work" "currentRelease/up_counter.vhd" -add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd" -add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" -add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_36x32_OutReg.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x32_OutReg.vhd" -add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd" -add_file -vhdl -lib "work" "../base/code/input_statistics.vhd" -add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" - - -add_file -vhdl -lib "work" "trb3_periph_padiwa.vhd" +add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib work "../base/code/input_statistics.vhd" +add_file -vhdl -lib work "../base/code/sedcheck.vhd" + +#add_file -vhdl -lib work "tdc_release/Adder_304.vhd" +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" + +add_file -vhdl -lib work "trb3_periph_padiwa.vhd" diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index 5c4fe53..d026c49 120000 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -1 +1 @@ -currentRelease/trb3_periph_padiwa.vhd \ No newline at end of file +tdc_release/trb3_periph_padiwa.vhd \ No newline at end of file -- 2.43.0