From eca4d17ef46fe9eeca90b0180856ca5002705f8e Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Mon, 12 Oct 2020 12:39:20 +0200 Subject: [PATCH] Derive system clock from downlink reference clock This gets rid of the separate fabric clock input port and prevents timing errors stemming from the separate clock sources. --- hub_test/constrs/hub_test.xdc | 4 - hub_test/ip/clk_wiz_0/clk_wiz_0.xci | 24 +++++- hub_test/ip/clk_wiz_0/clk_wiz_0.xml | 122 ++++++++++++++++++++++++++-- hub_test/src/hub_test.vhd | 26 +++--- 4 files changed, 145 insertions(+), 31 deletions(-) diff --git a/hub_test/constrs/hub_test.xdc b/hub_test/constrs/hub_test.xdc index 190d9a6..0ae6022 100644 --- a/hub_test/constrs/hub_test.xdc +++ b/hub_test/constrs/hub_test.xdc @@ -5,10 +5,6 @@ create_clock -period 5.000 -name CLK_200_P [get_ports CLK_200_P] set_property PACKAGE_PIN AR21 [get_ports SI5345_IN0_P] set_property IOSTANDARD LVDS [get_ports SI5345_IN0_P] -set_property PACKAGE_PIN AY37 [get_ports SI5345_OUT7_P] -set_property IOSTANDARD LVDS [get_ports SI5345_OUT7_P] -create_clock -period 10.000 -name SI5345_OUT7_P [get_ports SI5345_OUT7_P] - set_property PACKAGE_PIN K10 [get_ports MPOD_RX1_RESET_N] set_property IOSTANDARD LVTTL [get_ports MPOD_RX1_RESET_N] set_property PACKAGE_PIN K11 [get_ports MPOD_RX2_RESET_N] diff --git a/hub_test/ip/clk_wiz_0/clk_wiz_0.xci b/hub_test/ip/clk_wiz_0/clk_wiz_0.xci index 788e7fa..25b41b3 100644 --- a/hub_test/ip/clk_wiz_0/clk_wiz_0.xci +++ b/hub_test/ip/clk_wiz_0/clk_wiz_0.xci @@ -17,6 +17,13 @@ 100000000 false 100000000 + + + + 100000000 + 0 + 0 + 0.000 @@ -344,7 +351,7 @@ 100.000 0.010 10.000 - Differential_clock_capable_pin + No_buffer psclk psdone psen @@ -385,7 +392,7 @@ 0 0 0 - 0 + 1 0 1 0 @@ -605,7 +612,7 @@ 100.000 0.010 10.000 - Differential_clock_capable_pin + No_buffer psclk psdone psen @@ -643,7 +650,7 @@ false false false - false + true false true false @@ -693,12 +700,19 @@ + + + + + + + @@ -706,6 +720,8 @@ + + diff --git a/hub_test/ip/clk_wiz_0/clk_wiz_0.xml b/hub_test/ip/clk_wiz_0/clk_wiz_0.xml index 4eae428..7c84f5c 100644 --- a/hub_test/ip/clk_wiz_0/clk_wiz_0.xml +++ b/hub_test/ip/clk_wiz_0/clk_wiz_0.xml @@ -752,7 +752,7 @@ - true + false @@ -1013,6 +1013,91 @@ + + clock_CLK_IN1 + + + + + + + CLK_IN1 + + + clk_in1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + clock_CLK_OUT1 @@ -1185,7 +1270,7 @@ outputProductCRC - 9:40f10733 + 9:c19c43be @@ -1630,7 +1715,7 @@ - true + false @@ -1652,7 +1737,7 @@ - true + false @@ -2037,6 +2122,18 @@ + + clk_in1 + + in + + + std_logic + xilinx_elaborateports + + + + clk_out1 @@ -2185,7 +2282,7 @@ C_USE_PHASE_ALIGNMENT - 0 + 1 C_PRIM_IN_JITTER @@ -2265,7 +2362,7 @@ C_PRIM_SOURCE - Differential_clock_capable_pin + No_buffer C_PHASESHIFT_MODE @@ -3572,7 +3669,7 @@ USE_PHASE_ALIGNMENT - false + true USE_MIN_POWER @@ -3920,7 +4017,7 @@ PRIM_SOURCE - Differential_clock_capable_pin + No_buffer CLKOUT1_DRIVES @@ -4560,12 +4657,19 @@ + + + + + + + @@ -4573,6 +4677,8 @@ + + diff --git a/hub_test/src/hub_test.vhd b/hub_test/src/hub_test.vhd index 7ace952..5783343 100644 --- a/hub_test/src/hub_test.vhd +++ b/hub_test/src/hub_test.vhd @@ -18,8 +18,6 @@ entity hub_test is SI5345_IN0_P : out std_logic; -- 100 MHz SI5345_IN0_N : out std_logic; - SI5345_OUT7_P : in std_logic; -- 100 MHz, derived from SI5345_IN0_P - SI5345_OUT7_N : in std_logic; MPOD_RX1_RESET_N : out std_logic; MPOD_RX2_RESET_N : out std_logic; @@ -33,7 +31,7 @@ entity hub_test is PEX_I2C_SEL1 : out std_logic; UC_RESET_N : out std_logic; - MGTREFCLK0P_232 : in std_logic; -- 100 MHz, sync. with SI5345_OUT7_P + MGTREFCLK0P_232 : in std_logic; -- 100 MHz, derived from SI5345_IN0_P MGTREFCLK0N_232 : in std_logic; MGTREFCLK0P_231 : in std_logic; -- 200 MHz, free-running @@ -69,12 +67,11 @@ architecture behavioral of hub_test is component clk_wiz_0 port ( - clk_out1 : out std_logic; - clk_out2 : out std_logic; - reset : in std_logic; - locked : out std_logic; - clk_in1_p : in std_logic; - clk_in1_n : in std_logic + clk_out1 : out std_logic; + clk_out2 : out std_logic; + reset : in std_logic; + locked : out std_logic; + clk_in1 : in std_logic ); end component; @@ -231,12 +228,11 @@ begin THE_SYSCLK : clk_wiz_0 port map ( - clk_out1 => sysclk_100, - clk_out2 => sysclk_200, - reset => mb_sysclk_reset, - locked => sysclk_locked, - clk_in1_p => SI5345_OUT7_P, - clk_in1_n => SI5345_OUT7_N + clk_out1 => sysclk_100, + clk_out2 => sysclk_200, + reset => mb_sysclk_reset, + locked => sysclk_locked, + clk_in1 => mgtrefclk_downlink_bufg ); THE_MGTREFCLK0_232 : IBUFDS_GTE3 -- 2.43.0