From ed3eefdcd141124411b4369b127f45c06b8e87aa Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 22 Oct 2007 14:39:26 +0000 Subject: [PATCH] small changes to different files --- testbench/trb_net16_dummy_apl.vhd | 2 +- testbench/trb_net16_dummy_passive_apl.vhd | 2 +- trb_net16_io_multiplexer.vhd | 27 +- trb_net_med_8bit_fast.vhd | 2 +- trb_net_med_8bit_slow.vhd | 391 ++++++++++++++++++++++ 5 files changed, 419 insertions(+), 5 deletions(-) create mode 100644 trb_net_med_8bit_slow.vhd diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd index 91eec58..2aa45e5 100644 --- a/testbench/trb_net16_dummy_apl.vhd +++ b/testbench/trb_net16_dummy_apl.vhd @@ -18,7 +18,7 @@ entity trb_net16_dummy_apl is TRANSFER_LENGTH : integer := 3 -- length of dummy data -- might not work with transfer_length > api_fifo -- because of incorrect handling of fifo_full_in! - -- shorttransfer is not working too + ); port( -- Misc diff --git a/testbench/trb_net16_dummy_passive_apl.vhd b/testbench/trb_net16_dummy_passive_apl.vhd index 19fa02b..320ff89 100644 --- a/testbench/trb_net16_dummy_passive_apl.vhd +++ b/testbench/trb_net16_dummy_passive_apl.vhd @@ -1,6 +1,6 @@ -- this is a dummy apl, just sending data into an active api ---THIS IS NOT WORKING !!!! +-- THIS IS NOT WORKING !!!! LIBRARY IEEE; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index 689aa67..60b04cb 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -115,6 +115,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal demux_sbuf_data_out: std_logic_vector((DATA_WIDTH+2)*(2**MUX_WIDTH)-1 downto 0); signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0); signal current_mux_packet_number : std_logic_vector (1 downto 0); + signal last_mux_enable : std_logic; begin ------------------------------------------------------------------------------- -- DEMUX @@ -262,8 +263,30 @@ ARBITER: trb_net_priority_arbiter end if; end process; - current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0' - else final_INT_READ_OUT; + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + last_mux_enable <= '0'; + else + last_mux_enable <= mux_enable; + end if; + end if; + end process; + + process(tmp_INT_READ_OUT, endpoint_locked, final_INT_READ_OUT) + begin + if endpoint_locked = '0' then + current_INT_READ_OUT <= tmp_INT_READ_OUT; + else + current_INT_READ_OUT <= final_INT_READ_OUT; + end if; + if last_mux_enable = '0' then + current_INT_READ_OUT <= (others => '0'); + end if; + end process; +-- current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0' +-- else final_INT_READ_OUT; STAT(17 downto 16) <= current_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH) xor current_mux_packet_number; diff --git a/trb_net_med_8bit_fast.vhd b/trb_net_med_8bit_fast.vhd index cd51bd1..1eb18fe 100644 --- a/trb_net_med_8bit_fast.vhd +++ b/trb_net_med_8bit_fast.vhd @@ -237,7 +237,7 @@ U_DCM_RECV: DCM CLKIN_PERIOD => 10.00, -- 30.30ns STARTUP_WAIT => FALSE, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", - PHASE_SHIFT => 30, + PHASE_SHIFT => 70, CLKOUT_PHASE_SHIFT => "FIXED" ) port map ( diff --git a/trb_net_med_8bit_slow.vhd b/trb_net_med_8bit_slow.vhd new file mode 100644 index 0000000..cab45c0 --- /dev/null +++ b/trb_net_med_8bit_slow.vhd @@ -0,0 +1,391 @@ +--This entity provides data transfer (64bit) via a smaller (16bit) Bus +--with three bits for debugging (13bit data + 3bit control) +--first 56bit via Bus are for dataword, transmitted Bits 64 downto 56 Bits +--are for debugging + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +use work.trb_net_std.all; + +entity trb_net_med_8bit_slow is +generic( + TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 2 --even values only! + ); + + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Internal direction port (MII) + -- do not change this interface!!! + -- 1st part: from the medium to the internal logic (trbnet) + INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media + --and ready to be read out (the IOBUF MUST read) + INT_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word + INT_PACKET_NUM_OUT:out STD_LOGIC_VECTOR (1 downto 0); + INT_READ_IN: in STD_LOGIC; + INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits + -- 2nd part: from the internal logic (trbnet) to the medium + INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media + INT_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); + INT_READ_OUT: out STD_LOGIC; -- offered word is read + INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits + -- (end do not change this interface!!!) + + + -- Media direction port + -- in this case for the cable => 32 lines in total + MED_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word + --(incl. debugging errorbits) + MED_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word + + -- Status and control port => this never can hurt + STAT: out STD_LOGIC_VECTOR (31 downto 0); + --STAT(0): Busy reading from media + --STAT(1): Busy writing to media + --STAT(31 downto 28): packets_in (mod 16) + --STAT(27 downto 24): packets_out (mod 16) + --STAT(11 downto 8): INT2MED state + --STAT(15 downto 12): MED2INT state + + CTRL: in STD_LOGIC_VECTOR (31 downto 0) + --CTRL(24..31) -> lvds-data(63 downto 56) via lvds + --once for each packet + + ); +end entity trb_net_med_8bit_slow; + +architecture trb_net_med_8bit_slow_arch of trb_net_med_8bit_slow is + + signal buf_INT_DATA_IN, next_buf_INT_DATA_IN :std_logic_vector(7 downto 0); + signal buf_INT_PACKET_NUM_IN, next_buf_INT_PACKET_NUM_IN :std_logic_vector(1 downto 0); + + signal next_INT_DATA_OUT, buf_INT_DATA_OUT: std_logic_vector(15 downto 0); + signal next_INT_PACKET_NUM_OUT, buf_INT_PACKET_NUM_OUT: std_logic_vector(1 downto 0); + signal next_INT_DATAREADY_OUT, buf_INT_DATAREADY_OUT: std_logic; + signal next_buf_INT_READ_OUT, buf_INT_READ_OUT: std_logic; + signal reg_MED_FIRST_PACKET_IN : std_logic; + signal next_buf_MED_DATA_OUT, buf_MED_DATA_OUT: std_logic_vector(7 downto 0); + signal buf_MED_TRANSMISSION_CLK_OUT: std_logic; + signal buf_MED_CARRIER_OUT, next_MED_CARRIER_OUT: STD_LOGIC; + signal buf_MED_PARITY_OUT, next_MED_PARITY_OUT: STD_LOGIC; + signal buf_MED_FIRST_PACKET_OUT, next_MED_FIRST_PACKET_OUT : std_logic; + signal my_error,next_my_error : std_logic_vector(2 downto 0); + signal fatal_error, media_not_connected : std_logic; + signal next_media_not_connected : std_logic; + signal transmission_clk_Counter : std_logic_vector(4 downto 0); + signal next_transmission_clk_Counter : std_logic_vector(4 downto 0); + signal next_TRANSMISSION_CLK: std_logic; + signal buf_CTRL, next_STAT, buf_STAT : std_logic_vector(31 downto 0); + signal next_RECV_STAT, RECV_STAT : std_logic_vector(8 downto 0); + + signal last_TRCLK, this_TRCLK: std_logic; + signal CLK_counter,next_CLK_counter: std_logic_vector(7 downto 0); + + signal packets_in_counter, next_packets_in_counter: std_logic_vector(7 downto 0); + signal packets_in_compl_counter, next_packets_in_compl_counter: std_logic_vector(3 downto 0); + signal packets_out_counter, next_packets_out_counter: std_logic_vector(3 downto 0); + + signal last_MED_TRANSMISSION_CLK_IN : std_logic; + signal reg_MED_DATA_IN : std_logic_vector(7 downto 0); + signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic; + signal reg_MED_PARITY_IN : std_logic; + signal med2int_state_sig :std_logic_vector(2 downto 0); + signal recv_counter : std_logic_vector(2 downto 0); + signal transmission_running, next_transmission_running : std_logic; + signal buf_MED_DATA_IN, next_buf_MED_DATA_IN : std_logic_vector(7 downto 0); +begin +INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; +INT_DATA_OUT <= buf_INT_DATA_OUT; +INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; +INT_ERROR_OUT <= my_error; +INT_READ_OUT <= buf_INT_READ_OUT; +STAT <= buf_STAT; + +MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT; +MED_DATA_OUT(10 downto 8) <= (others => '0'); +MED_DATA_OUT(11) <= '1'; +MED_DATA_OUT(12) <= buf_MED_FIRST_PACKET_OUT; +MED_DATA_OUT(13) <= buf_MED_TRANSMISSION_CLK_OUT; +MED_DATA_OUT(14) <= buf_MED_CARRIER_OUT; +MED_DATA_OUT(15) <= buf_MED_PARITY_OUT; + + +--TODO: +-------------------------------- +fatal_error <= '0'; + + + +--CTRL register +-------------------------------- +CTRL_reg: process (CLK,RESET) + begin + if RESET = '1' then + buf_CTRL <= (others => '0'); + elsif rising_edge(CLK) then + buf_CTRL <= CTRL; + else + buf_CTRL <= buf_CTRL; + end if; + end process; + + + +--My error bits +-------------------------------- +gen_my_error: process(media_not_connected,fatal_error) + begin + if media_not_connected = '1' then + next_my_error <= "100"; + elsif fatal_error = '1' then + next_my_error <= "011"; + else + next_my_error <= "000"; + end if; + end process; + + +reg_my_error: process(CLK,RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + my_error <= "000"; + else + my_error <= next_my_error; + end if; + end if; + end process; + + +--Transmission clock generator +-------------------------------- +trans_clk_counter: process (transmission_clk_Counter, buf_MED_TRANSMISSION_CLK_OUT) + begin + if transmission_clk_Counter = (TRANSMISSION_CLOCK_DIVIDER/2) - 1 then + next_transmission_clk_Counter <= (others => '0'); + next_TRANSMISSION_CLK <= not buf_MED_TRANSMISSION_CLK_OUT; + else + next_transmission_clk_Counter <= transmission_clk_Counter + 1; + next_TRANSMISSION_CLK <= buf_MED_TRANSMISSION_CLK_OUT; + end if; + end process; + + +trans_clk_counter_reg: process (CLK,RESET) + begin + if RESET = '1' then + transmission_clk_Counter <= (others => '0'); + buf_MED_TRANSMISSION_CLK_OUT <= '0'; + elsif rising_edge(CLK) then + transmission_clk_Counter <= next_transmission_clk_Counter; + buf_MED_TRANSMISSION_CLK_OUT <= next_TRANSMISSION_CLK; + else + transmission_clk_Counter <= transmission_clk_Counter; + buf_MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT; + end if; + end process; + + + +--Transmission Clock detection +-------------------------------- +trans_clk_reg: process (RESET,CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + last_TRCLK <= '0'; + this_TRCLK <= '0'; + CLK_counter <= (others => '0'); + media_not_connected <= '0'; + else + last_TRCLK <= this_TRCLK; + this_TRCLK <= reg_MED_TRANSMISSION_CLK_IN; + CLK_counter <= next_CLK_counter; + media_not_connected <= next_media_not_connected; + end if; + end if; + end process; + + + +transCLK_counter: process (this_TRCLK, last_TRCLK, CLK_counter, + buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, + buf_MED_PARITY_OUT, buf_CTRL) + begin + next_media_not_connected <= '0'; + if last_TRCLK = '0' and this_TRCLK = '1' then + next_CLK_counter <= (others => '0'); + elsif CLK_counter = 255 then + next_media_not_connected <= '1'; + next_CLK_counter <= CLK_counter; + else + next_CLK_counter <= CLK_counter + 1; + end if; + end process; + + + + +--INT to MED direction +-------------------------------- +INT2MED_fsm: process(buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, buf_MED_PARITY_OUT, buf_INT_DATA_IN, + transmission_running, buf_MED_FIRST_PACKET_OUT, next_TRANSMISSION_CLK, + buf_MED_TRANSMISSION_CLK_OUT, INT_DATAREADY_IN, INT_DATA_IN) +begin + next_buf_MED_DATA_OUT <= buf_MED_DATA_OUT; + next_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; + next_MED_PARITY_OUT <= buf_MED_PARITY_OUT; + next_buf_INT_DATA_IN <= buf_INT_DATA_IN; + next_buf_INT_READ_OUT <= buf_INT_READ_OUT; + next_transmission_running <= transmission_running; + next_MED_FIRST_PACKET_OUT <= buf_MED_FIRST_PACKET_OUT; + buf_INT_READ_OUT <= '0'; + if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' and transmission_running = '0' then + next_MED_CARRIER_OUT <= '0'; + end if; + if(INT_DATAREADY_IN = '1' and transmission_running = '0') then + if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then + next_buf_MED_DATA_OUT <= INT_DATA_IN(15 downto 8); + next_buf_INT_DATA_IN <= INT_DATA_IN(7 downto 0); + next_MED_CARRIER_OUT <= '1'; + next_transmission_running <= '1'; + buf_INT_READ_OUT <= '1'; + if INT_PACKET_NUM_IN = "00" then + next_MED_FIRST_PACKET_OUT <= '1'; + else + next_MED_FIRST_PACKET_OUT <= '0'; + end if; + end if; + elsif transmission_running = '1' then + if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then + next_buf_MED_DATA_OUT <= buf_INT_DATA_IN; + next_transmission_running <= '0'; + end if; + end if; +end process; + + +INT2MED_fsm_reg: process(CLK,RESET) + begin + if rising_edge(CLK) then + if RESET='1' then + buf_MED_DATA_OUT <= (others => '0'); + buf_INT_DATA_IN <= (others => '0'); + buf_MED_CARRIER_OUT <= '0'; + buf_MED_PARITY_OUT <= '0'; + buf_MED_FIRST_PACKET_OUT <= '0'; + transmission_running <= '0'; + else + buf_INT_DATA_IN <= next_buf_INT_DATA_IN; + buf_MED_DATA_OUT <= next_buf_MED_DATA_OUT; + buf_MED_FIRST_PACKET_OUT <= next_MED_FIRST_PACKET_OUT; + buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT; + buf_MED_PARITY_OUT <= next_MED_PARITY_OUT; + transmission_running <= next_transmission_running; + end if; + end if; + end process; + + + + + + + + + + + + + + + +--MED to INT direction +-------------------------------- + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + recv_counter <= "111"; + elsif reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then + recv_counter <= recv_counter + 1; + end if; + end if; + end process; + + + +MED2INT_fsm: process(buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT, buf_MED_DATA_IN, last_MED_TRANSMISSION_CLK_IN, + reg_MED_TRANSMISSION_CLK_IN, reg_MED_DATA_IN, recv_counter, INT_READ_IN) + begin + next_INT_DATA_OUT <= buf_INT_DATA_OUT; + next_INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; + next_buf_MED_DATA_IN <= buf_MED_DATA_IN; + + if last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then + if recv_counter(0) = '1' then + next_buf_MED_DATA_IN <= reg_MED_DATA_IN; + else + next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN; + next_INT_DATA_OUT(15 downto 8) <= buf_MED_DATA_IN; + next_INT_PACKET_NUM_OUT <= recv_counter(2 downto 1); + next_INT_DATAREADY_OUT <= '1'; + end if; + end if; + if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then + next_INT_DATAREADY_OUT <= '0'; + end if; + + end process; + + +MED2INT_fsm_reg: process(CLK) + begin + if rising_edge(CLK) then + if RESET='1' then + buf_INT_DATAREADY_OUT <= '0'; + buf_INT_DATA_OUT <= (others => '0'); + last_MED_TRANSMISSION_CLK_IN <= '1'; + buf_MED_DATA_IN <= (others => '0'); + buf_INT_PACKET_NUM_OUT <= "00"; + else + buf_INT_DATA_OUT <= next_INT_DATA_OUT; + buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT; + last_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN; + buf_MED_DATA_IN <= next_buf_MED_DATA_IN; + buf_INT_PACKET_NUM_OUT <= next_INT_PACKET_NUM_OUT; + end if; + end if; + end process; + +LVDS_IN_reg: process(CLK) + begin + if rising_edge(CLK) then + if RESET='1' then + reg_MED_TRANSMISSION_CLK_IN <= '0'; + reg_MED_CARRIER_IN <= '0'; + reg_MED_PARITY_IN <= '0'; + reg_MED_DATA_IN <= (others => '0'); + reg_MED_FIRST_PACKET_IN <= '0'; + else + reg_MED_TRANSMISSION_CLK_IN <= MED_DATA_IN(13); + reg_MED_CARRIER_IN <= MED_DATA_IN(14); + reg_MED_PARITY_IN <= MED_DATA_IN(15); + reg_MED_DATA_IN <= MED_DATA_IN(7 downto 0); + reg_MED_FIRST_PACKET_IN <= MED_DATA_IN(12); + end if; + end if; + end process; + + +end architecture; + -- 2.43.0