From ee1c2f2acad7c9f5caa42dc335f19acb3ad8fab1 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Thu, 19 Jul 2018 14:45:27 +0200 Subject: [PATCH] get rid of some warnings due to unassigned pins. --- base/trb3_periph_mupix8.lpf | 28 ++++++++++++++-------------- mupix/Mupix8/trb3_periph.vhd | 23 +++++++++++++---------- 2 files changed, 27 insertions(+), 24 deletions(-) diff --git a/base/trb3_periph_mupix8.lpf b/base/trb3_periph_mupix8.lpf index 87b2fe6..04cb591 100644 --- a/base/trb3_periph_mupix8.lpf +++ b/base/trb3_periph_mupix8.lpf @@ -7,8 +7,8 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; #LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; -LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; -LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; #LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; #LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; @@ -31,18 +31,18 @@ IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; # To central FPGA ################################################################# -LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; -LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; -LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; -LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; -LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; -LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; -LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; -LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; -LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; -LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; -LOCATE COMP "FPGA5_COMM_10" SITE "V10"; -LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +LOCATE COMP "FPGA5_COMM0" SITE "AD4"; +#LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM2" SITE "AA7"; +#LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +#LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +#LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +#LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +#LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +#LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +#LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +#LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +#LOCATE COMP "FPGA5_COMM_11" SITE "W10"; DEFINE PORT GROUP "FPGA_group" "FPGA*" ; IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd index 1f323e3..2e2bc4b 100644 --- a/mupix/Mupix8/trb3_periph.vhd +++ b/mupix/Mupix8/trb3_periph.vhd @@ -31,22 +31,23 @@ entity trb3_periph is TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out --Serdes - CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible - CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + --CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems SERDES_INT_TX : out std_logic_vector(3 downto 0); SERDES_INT_RX : in std_logic_vector(3 downto 0); --SERDES_ADDON_TX : out std_logic_vector(11 downto 0); --SERDES_ADDON_RX : in std_logic_vector(11 downto 0); mupix_serdes_rx : in std_logic_vector(7 downto 0); --Inter-FPGA Communication - FPGA5_COMM : inout std_logic_vector(11 downto 0); + --FPGA5_COMM : inout std_logic_vector(11 downto 0); + FPGA5_COMM0 : inout std_logic; + FPGA5_COMM2 : inout std_logic; --Bit 0/1 input, serial link RX active --Bit 2/3 output, serial link TX active --------------------------------------------------------------------------- -- BEGIN SenorBoard MuPix --------------------------------------------------------------------------- - spare_line : in std_logic_vector(5 downto 0); --spare lines led_addon : out std_logic_vector(3 downto 0); --trb addon board leds --slow control signals testpulse : out std_logic; --generate injection pulse @@ -76,8 +77,8 @@ entity trb3_periph is syncres : out std_logic; --reset of mupix timestamps and counters --fast data comes in via serdes addon (see above) --link simulation - simlink : out std_logic; - simclk : out std_logic; + simlink : out std_logic; -- spare link 0 + simclk : out std_logic; -- spare link 2 --------------------------------------------------------------------------- -- END SensorBoard MuPix @@ -116,7 +117,9 @@ entity trb3_periph is attribute syn_useioff of FLASH_CS : signal is true; attribute syn_useioff of FLASH_DIN : signal is true; attribute syn_useioff of FLASH_DOUT : signal is true; - attribute syn_useioff of FPGA5_COMM : signal is true; + --attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of FPGA5_COMM0 : signal is true; + attribute syn_useioff of FPGA5_COMM2 : signal is true; attribute syn_useioff of TEST_LINE : signal is true; --attribute syn_useioff of INP : signal is false; --attribute syn_useioff of DAC_SDO : signal is true; @@ -461,9 +464,9 @@ begin SD_TXD_N_OUT => SERDES_INT_TX(3), SD_REFCLK_P_IN => open, SD_REFCLK_N_IN => open, - SD_PRSNT_N_IN => FPGA5_COMM(0), - SD_LOS_IN => FPGA5_COMM(0), - SD_TXDIS_OUT => FPGA5_COMM(2), + SD_PRSNT_N_IN => FPGA5_COMM0, + SD_LOS_IN => FPGA5_COMM0, + SD_TXDIS_OUT => FPGA5_COMM2, -- Status and control port STAT_OP => med_stat_op, CTRL_OP => med_ctrl_op, -- 2.43.0