From ef23b97d1a46fae1a7d793b4caf5072ccab943bf Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 19 Feb 2019 12:37:39 +0100 Subject: [PATCH] Resize media interface region. --- dirich/dirich.lpf | 2 +- dirich/dirich.vhd | 29 +++-------------------------- 2 files changed, 4 insertions(+), 27 deletions(-) diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf index ad3d878..f5287ed 100644 --- a/dirich/dirich.lpf +++ b/dirich/dirich.lpf @@ -36,7 +36,7 @@ GSR_NET NET "clear_i"; # LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; -REGION "MEDIA" "R81C45D" 12 40; +REGION "MEDIA" "R81C44D" 13 30; LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index a4df977..2e83864 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -98,7 +98,6 @@ architecture dirich_arch of dirich is signal pwm_i : std_logic_vector(31 downto 0); signal timer : TIMERS; - signal lcd_data : std_logic_vector(511 downto 0); signal hdr_io : std_logic_vector(9 downto 0); signal led_off : std_logic; --TDC @@ -111,10 +110,6 @@ architecture dirich_arch of dirich is attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; --- type a_t is array(0 to 15) of std_logic_vector(4000 downto 0); --- signal c : a_t; --- attribute syn_keep of c : signal is true; --- attribute syn_preserve of c : signal is true; signal link_stat_in_reg : std_logic; @@ -318,7 +313,7 @@ THE_CAL_PLL : entity work.pll_in3125_out50 HEADER_IO => hdr_io, ADDITIONAL_REG(0) => led_off, --LCD - LCD_DATA_IN => lcd_data, + LCD_DATA_IN => (others => '0'), --ADC ADC_CS => ADC_CS, ADC_MOSI => ADC_DIN, @@ -388,17 +383,7 @@ end generate; --TEST_LINE(8 downto 1) <= med_stat_debug(7 downto 0); --TEST_LINE(8 downto 1) <= clk_sys & med_stat_debug(9) & med_stat_debug(10) & med_stat_debug(11) & clear_i & reset_i & link_stat_out & link_stat_in_reg; -- TEST_LINE(8 downto 3) <= clear_i & reset_i & link_stat_out & link_stat_in_reg & debug_clock_reset(0) & med_stat_debug(4);-- & med_stat_debug(5) & med_stat_debug(6); ---------------------------------------------------------------------------- --- LCD Data to display ---------------------------------------------------------------------------- - lcd_data(15 downto 0) <= timer.network_address; - lcd_data(47 downto 16) <= timer.microsecond; - lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)); - lcd_data(91 downto 80) <= timer.temperature; - lcd_data(95 downto 92) <= x"0"; - lcd_data(159 downto 96) <= timer.uid; - lcd_data(191 downto 160) <= debug_tools; - lcd_data(511 downto 192) <= (others => '0'); + --------------------------------------------------------------------------- -- LED @@ -451,18 +436,10 @@ end generate; LOGIC_ANALYSER_OUT => logic_analyser_i ); --- For single edge measurements gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate hit_in_i <= INPUT; end generate; --- --- -- For ToT Measurements --- gen_double : if DOUBLE_EDGE_TYPE = 2 generate --- Gen_Hit_In_Signals : for i in 1 to 16 generate --- hit_in_i(i*2-1) <= INPUT(i); --- hit_in_i(i*2) <= not INPUT(i); --- end generate Gen_Hit_In_Signals; --- end generate; + -- readout_tx(0).data_finished <= '1'; -- 2.43.0