From efa462c63c220c1a59835f2cc452462b1ce3ee2f Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 27 Jun 2013 16:05:25 +0200 Subject: [PATCH] TDC slow control registers are updated --- trb3/TdcSlowControl.tex | 59 ++++++++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 21 deletions(-) diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex index 9affaaa..aa6f237 100644 --- a/trb3/TdcSlowControl.tex +++ b/trb3/TdcSlowControl.tex @@ -78,24 +78,18 @@ the control registers are given in Table \ref{tab:tdcControlReg}. \hline FSM debug & \multicolumn{2}{c|}{Explanation}\\ \hline \hline - x"01" & IDLE & waiting for a readout trigger\\\hline - x"02" & WAIT\_FOR\_TRG\_WIND\_END & waiting until the end of the trigger window\\\hline - x"03" & WR\_HEADER & sending signals to write TDC header\\\hline - x"04" & WAIT\_FOR\_FIFO\_NR\_A &\multirow{2}{7cm}{waiting for the decision of the next channel buffer to read}\\ - x"05" & WAIT\_FOR\_FIFO\_NR\_B &\\\hline - \multirow{2}{*}{x"06"} & \multirow{2}{*}{APPLY\_MASK} &\multirow{2}{7cm}{checking if there is any other channel buffer to read}\\ + x"1" & IDLE & waiting for a readout trigger\\\hline + x"2" & WAIT\_FOR\_TRG\_WIND\_END & waiting until the end of the trigger window\\\hline + x"3" & RD\_CH & sending read signals to the TDC channels\\\hline + x"4" & WAIT\_FOR\_LVL1\_TRG\_A &\multirow{3}{7cm}{waiting for a trigger data validation and checking if it was a spurious trigger}\\ + x"5" & WAIT\_FOR\_LVL1\_TRG\_B &\\ + x"6" & WAIT\_FOR\_LVL1\_TRG\_C &\\\hline + \multirow{2}{*}{x"7"} & \multirow{2}{*}{SEND\_STATUS} &\multirow{2}{7cm}{writing status information in case of a type "E" trigger or enabled \textit{Debug Mode}}\\ & &\\\hline - x"07" & RD\_CHANNEL\_A &\multirow{3}{7cm}{sending necessary signals to read the buffer, writing the date to the endpoint buffer, checking the end of the buffer}\\ - x"08" & RD\_CHANNEL\_B &\\ - x"09" & RD\_CHANNEL\_C &\\\hline - x"0A" & WAIT\_FOR\_LVL1\_TRG\_A &\multirow{3}{7cm}{waiting for a trigger data validation and checking if it was a spurious trigger}\\ - x"0B" & WAIT\_FOR\_LVL1\_TRG\_B &\\ - x"0C" & WAIT\_FOR\_LVL1\_TRG\_C &\\\hline - \multirow{2}{*}{x"0D"} & \multirow{2}{*}{SEND\_STATUS} &\multirow{2}{7cm}{writing status information in case of a type "E" trigger or enabled \textit{Debug Mode}}\\ - & &\\\hline - \multirow{3}{1cm}{x"0E" x"0F"} & \multirow{3}{4.31cm}{SEND\_TRG\_RELEASE\_A SEND\_TRG\_RELEASE\_B} &\multirow{3}{7cm}{sending a trigger release signal and waiting one extra clock cycle before going to the IDLE state}\\ - & &\\ + \multirow{3}{1cm}{x"8" x"9"} & \multirow{3}{4.31cm}{SEND\_TRG\_RELEASE\_A SEND\_TRG\_RELEASE\_B} &\multirow{3}{7cm}{sending a trigger release signal and waiting one extra clock cycle before going to the IDLE state}\\ & &\\ + & &\\\hline + \multirow{2}{*}{x"F"} & \multirow{2}{*}{OTHERS} & should never be in this state. If yes, there is a problem.\\ \hline \end{tabularx} \caption{TDC Readout FSM debug word bitmap.} @@ -103,6 +97,22 @@ the control registers are given in Table \ref{tab:tdcControlReg}. \end{center} \end{table} +\begin{table}[htbp] + \begin{center} + \begin{tabularx}{\textwidth}{|W{1cm}|rL|} + \hline + FSM debug & \multicolumn{2}{c|}{Explanation}\\ + \hline \hline + x"1" & IDLE & waiting for the trigger window end\\\hline + x"2" & WR\_CH & writing channel data information to trbnet buffers\\\hline + x"F" & OTHERS & should never be in this state. If yes, there is a problem.\\ + \hline + \end{tabularx} + \caption{TDC Writeout FSM debug word bitmap.} + \label{tab:tdcWriteoutFsm} + \end{center} +\end{table} + \begin{table}[htbp] \begin{center} \begin{tabularx}{\textwidth}{|W{1cm}|rL|} @@ -125,16 +135,20 @@ the control registers are given in Table \ref{tab:tdcControlReg}. \hline Address & \multicolumn{1}{c|}{Name} & Bits & \multicolumn{1}{c|}{Explanation}\\ \hline \hline - \multirow{5}{*}{0xc100} & \multirow{5}{3.5cm}{Basic controls} & 7-0 & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\ - & & 15-8 & Implemented channel number.\\ + \multirow{8}{*}{0xc100} & \multirow{8}{3.5cm}{Basic controls} & 3-0 & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\ + & & 7-4 & Debug word of the TDC writeout FSM (see \ref{tab:tdcWriteoutFsm})\\ + & & 15-8 & Implemented channel number.\\ & & 16 & Reference time synchronised to 100~MHz TrbNet clock.\\ - & & 31-17 & reserved\\ \hline + & & 27-17 & reserved\\ + & & 31-28 & Trigger type\\ \hline + 0xc101 & Empty channels 1 & 31-0 & Empty signals of the channels 32-1\\ \hline 0xc102 & Empty channels 2 & 31-0 & Empty signals of the channels 64-33\\ \hline - \multirow{6}{*}{0xc103} & \multirow{6}{3.5cm}{Trigger window controls} & 10-0 & Trigger window width before the trigger with granularity of 5~ns\\ + \multirow{7}{*}{0xc103} & \multirow{7}{3.5cm}{Trigger window controls} & 10-0 & Trigger window width before the trigger with granularity of 5~ns\\ & & 15-11 & reserved\\ & & 26-16 & Trigger window width after the trigger with granularity of 5~ns\\ - & & 31-27 & reserved\\ \hline + & & 30-27 & reserved\\ + & & 31 & Trigger window status (1:enabled 0:disabled)\\ \hline \multirow{2}{*}{0xc104} & \multirow{2}{3.5cm}{Trigger number} & 23-0 & Number of valid triggers received\\ & & 31-24 & reserved\\ \hline \multirow{2}{*}{0xc105} & \multirow{2}{3.5cm}{Valid timing trigger number} & 23-0 & Number of valid timing triggers received\\ @@ -175,6 +189,9 @@ the control registers are given in Table \ref{tab:tdcControlReg}. & & 31-24 & reserved\\ \hline \multirow{3}{*}{0xc111} & \multirow{3}{3.5cm}{Timeout Number} & 23-0 & Number of timeouts detected (too long delay after the timing trigger)\\ & & 31-24 & reserved\\ \hline + \multirow{2}{*}{0xc112} & \multirow{2}{3.5cm}{Finished number} & 23-0 & Number of sent finished signals\\ + & & 31-24 & reserved\\ \hline + \end{tabularx} \caption{The status registers of the TDC. (Continue)} \label{tab:tdcStatusReg2} -- 2.43.0