From efb227f25a313cdc0b759628754203ef08710683 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 18 Nov 2021 13:05:38 +0100 Subject: [PATCH] TX and RX control cleaned up, simulated --- media_interfaces/sync/rx_control_RS.vhd | 24 +++---- media_interfaces/sync/tx_control_RS.vhd | 91 ++++++++++++++++++------- 2 files changed, 77 insertions(+), 38 deletions(-) diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 60ac3a2..065ea6b 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -5,7 +5,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.med_sync_define.all; +use work.med_sync_define_RS.all; entity rx_control_RS is port( @@ -25,13 +25,13 @@ entity rx_control_RS is RX_K_IN : in std_logic; --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM - RX_DLM : out std_logic := '0'; - RX_DLM_WORD : out std_logic_vector( 7 downto 0) := (others => '0'); + RX_DLM_OUT : out std_logic := '0'; + RX_DLM_WORD_OUT : out std_logic_vector( 7 downto 0) := (others => '0'); --other signals RX_ALLOW_IN : in std_logic := '0'; --clk_sys - RX_RESET_FINISHED : in std_logic := '0'; --clk_rx - GOT_LINK_READY : out std_logic := '0'; --clk_rx + RX_RESET_DONE_IN : in std_logic := '0'; --clk_rx + GOT_LINK_READY_OUT : out std_logic := '0'; --clk_rx DEBUG_OUT : out std_logic_vector(31 downto 0); STAT_REG_OUT : out std_logic_vector(31 downto 0) @@ -77,10 +77,10 @@ begin ---------------------------------------------------------------------- ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; -buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty when rising_edge(CLK_100); +buf_rx_write_out <= (last_ct_fifo_read and not last_ct_fifo_empty) when rising_edge(CLK_100); -RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; -RX_WRITE_OUT <= buf_rx_write_out; +RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; +RX_WRITE_OUT <= buf_rx_write_out; RX_PACKET_NUMBER_OUT <= rx_packet_num; last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100); @@ -192,7 +192,7 @@ PROC_RX_FSM : process begin end case; - if RESET_IN = '1' or RX_RESET_FINISHED = '0' then + if RESET_IN = '1' or RX_RESET_DONE_IN = '0' then rx_state <= SLEEP; end if; end process; @@ -205,10 +205,10 @@ WORD_SYNC_OUT <= sync_k_i; --reg_rx_k_in; ---------------------------------------------------------------------- -- Signals out ---------------------------------------------------------------------- -GOT_LINK_READY <= got_link_ready_i; +GOT_LINK_READY_OUT <= got_link_ready_i; -RX_DLM <= rx_dlm_i when rising_edge(CLK_200); -RX_DLM_WORD <= rx_dlm_word_i when rising_edge(CLK_200); +RX_DLM_OUT <= rx_dlm_i when rising_edge(CLK_200); +RX_DLM_WORD_OUT <= rx_dlm_word_i when rising_edge(CLK_200); ---------------------------------------------------------------------- -- Debug and Status diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index a7b5d20..74a0493 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -5,7 +5,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.med_sync_define.all; +use work.med_sync_define_RS.all; entity tx_control_RS is port( @@ -24,8 +24,11 @@ entity tx_control_RS is TX_K_OUT : out std_logic; TX_CD_OUT : out std_logic; - SEND_DLM : in std_logic := '0'; - SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0'); + SEND_DLM_IN : in std_logic := '0'; + SEND_DLM_WORD_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + + SEND_RST_IN : in std_logic := '0'; + SEND_RST_WORD_IN : in std_logic_vector( 7 downto 0) := (others => '0'); TX_ALLOW_IN : in std_logic := '0'; RX_ALLOW_IN : in std_logic := '0'; @@ -35,11 +38,10 @@ entity tx_control_RS is ); end entity; - - architecture arch of tx_control_RS is - type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H); + type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H, + SEND_RST_L, SEND_RST_H); signal current_state : state_t; signal state_bits : std_logic_vector(3 downto 0); @@ -57,8 +59,11 @@ architecture arch of tx_control_RS is signal ram_empty : std_logic; signal ram_afull : std_logic; - signal send_dlm_in_i : std_logic; signal send_dlm_i : std_logic; + signal send_dlm_word_i : std_logic_vector(7 downto 0); + + signal send_rst_i : std_logic; + signal send_rst_word_i : std_logic_vector(7 downto 0); signal buf_tx_read_out : std_logic; signal tx_data_200 : std_logic_vector(17 downto 0); @@ -82,12 +87,12 @@ architecture arch of tx_control_RS is signal load_eop : std_logic; signal first_idle : std_logic; signal toggle_idle : std_logic; + begin ---------------------------------------------------------------------- -- Clock Domain Transfer ---------------------------------------------------------------------- --- gk 05.10.10 THE_CT_FIFO : lattice_ecp3_fifo_18x16_dualport_oreg port map( Data(15 downto 0) => TX_DATA_IN, @@ -238,7 +243,15 @@ begin debug_sending_dlm <= '1'; when SEND_DLM_H => - TX_DATA_OUT <= SEND_DLM_WORD; + TX_DATA_OUT <= send_dlm_word_i; + + when SEND_RST_L => + TX_DATA_OUT <= K_RST; + TX_K_OUT <= '1'; + current_state <= SEND_RST_H; + + when SEND_RST_H => + TX_DATA_OUT <= send_rst_word_i; when others => current_state <= SEND_IDLE_L; @@ -246,11 +259,14 @@ begin if current_state = SEND_IDLE_H or current_state = SEND_DATA_H or - current_state = SEND_DLM_H then + current_state = SEND_DLM_H or + current_state = SEND_RST_H then if tx_allow_qtx = '0' then current_state <= SEND_IDLE_L; elsif send_dlm_i = '1' then current_state <= SEND_DLM_L; + elsif send_rst_i = '1' then + current_state <= SEND_RST_L; elsif ram_empty = '0' then current_state <= SEND_DATA_L; else @@ -260,9 +276,8 @@ begin end if; end if; --async because of oreg. - if (current_state = SEND_IDLE_H or current_state = SEND_DATA_H or current_state = SEND_DLM_H) - and ram_empty = '0' and tx_allow_qtx = '1' - and send_dlm_i = '0' then --TODO: Sync this signal? + if (current_state = SEND_IDLE_H or current_state = SEND_DATA_H or current_state = SEND_DLM_H or current_state = SEND_RST_H) + and ram_empty = '0' and tx_allow_qtx = '1' and send_dlm_i = '0' and send_rst_i = '0' then ram_read <= '1'; else ram_read <= '0'; @@ -286,23 +301,47 @@ begin D_IN(0) => tx_allow_qtx, D_OUT(0) => tx_allow_q); - send_dlm_in_i <= SEND_DLM; - --Send DLM message - THE_STORE_DLM_PROC : process(CLK_200, RESET_IN) + THE_STORE_DLM_PROC: process( CLK_200, RESET_IN ) begin - if RESET_IN = '1' then - send_dlm_i <= '0'; - elsif rising_edge(CLK_200) then - if tx_allow_qtx = '0' then - send_dlm_i <= '0'; - elsif send_dlm_in_i = '1' then - send_dlm_i <= '1'; - elsif current_state = SEND_DLM_L then - send_dlm_i <= '0'; + if( RESET_IN = '1' ) then + send_dlm_i <= '0'; + send_dlm_word_i <= (others => '0'); + elsif( rising_edge(CLK_200) ) then + if ( tx_allow_qtx = '0' ) then + send_dlm_i <= '0'; + send_dlm_word_i <= (others => '0'); + elsif( SEND_DLM_IN = '1' ) then + send_dlm_i <= '1'; + send_dlm_word_i <= SEND_DLM_WORD_IN; + elsif( current_state = SEND_DLM_L ) then + send_dlm_i <= '0'; + elsif( current_state = SEND_DLM_H ) then + send_dlm_word_i <= (others => '0'); end if; end if; - end process; + end process THE_STORE_DLM_PROC; + +--Send RST message + THE_STORE_RST_PROC: process( CLK_200, RESET_IN ) + begin + if( RESET_IN = '1' ) then + send_rst_i <= '0'; + send_rst_word_i <= (others => '0'); + elsif( rising_edge(CLK_200) ) then + if ( tx_allow_qtx = '0' ) then + send_rst_i <= '0'; + send_rst_word_i <= (others => '0'); + elsif( SEND_RST_IN = '1' ) then + send_rst_i <= '1'; + send_rst_word_i <= SEND_RST_WORD_IN; + elsif( current_state = SEND_RST_L ) then + send_rst_i <= '0'; + elsif( current_state = SEND_RST_H ) then + send_rst_word_i <= (others => '0'); + end if; + end if; + end process THE_STORE_RST_PROC; ---------------------------------------------------------------------- -- Debug -- 2.43.0